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| author | York Sun <york.sun@nxp.com> | 2016-05-19 04:11:19 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 21:12:06 (GMT) |
| commit | 5605dc6135f6f26560ef3b0c6ebc5141c531179a (patch) | |
| tree | 261ba20afcda83bd9e50ea82f9981eac9b151752 /doc/README.mpc5xx | |
| parent | c4f97b1f53a48ab52efc221b73a235797375fbfb (diff) | |
| download | u-boot-fsl-qoriq-5605dc6135f6f26560ef3b0c6ebc5141c531179a.tar.xz | |
drivers/ddr/fsl: Fix timing_cfg_2 register
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'doc/README.mpc5xx')
0 files changed, 0 insertions, 0 deletions