diff options
author | wdenk <wdenk> | 2004-07-10 21:45:47 (GMT) |
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committer | wdenk <wdenk> | 2004-07-10 21:45:47 (GMT) |
commit | 8b07a1103dc7dcadc80c4a9681cfa7d225e8e224 (patch) | |
tree | 8017b2826d62ec6d8289b8f1170627dc5c21ffcf /doc/README.sbc8560 | |
parent | 0ac6f8b7498d3608bd1de2280a014e9e23d7b1f2 (diff) | |
download | u-boot-fsl-qoriq-8b07a1103dc7dcadc80c4a9681cfa7d225e8e224.tar.xz |
* Patch by Fred Klatt, 25 Jun 2004:
Add support for WindRiver's SBC8560 board
* Patch by Nicolas Lacressonniere, 24 Jun 2004
Small Bugs fixes for "at91rm9200dk" board:
- Timing modifications for SPI DataFlash access
- Fix NAND flash detection bug
* Patch by Nicolas Lacressonniere, 24 Jun 2004:
Add Support for Flash AT49BV6416 for AT91RM9200DK board
Diffstat (limited to 'doc/README.sbc8560')
-rw-r--r-- | doc/README.sbc8560 | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/doc/README.sbc8560 b/doc/README.sbc8560 new file mode 100644 index 0000000..52592e3 --- /dev/null +++ b/doc/README.sbc8560 @@ -0,0 +1,53 @@ +The port was tested on Wind River System Sbc8560 board <www.windriver.com>. +U-Boot was installed on the flash memory of the CPU card (no the SODIMM). + +NOTE: Please configure uboot compile to the proper PCI frequency and +setup the appropriate DIP switch settings. + +SBC8560 board: + +Make sure boards switches are set to their appropriate conditions. +Refer to the Engineering Reference Guide ERG-00300-002. Of particular +importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which +select the on-board FLASH device (Intel 28F128Jx); 2) The settings +for the Clock SW9 (33 MHz or 66 MHz). + + Note: SW9 Settings: 66 MHz + 4:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on + Note: SW9 Settings: 33 MHz + 8:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on + + +Flashing the FLASH device with the "Wind River ICE": + +1) Properly connect and configure the Wind River ICE to the + target JTAG port. This includes running the SBC8560 register script. + Make sure target memory can be read and written. + +2) Build the u-boot image: + make distclean + make SBC8560_66_config or SBC8560_33_config + make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all + + Note: reference is made to the ELDK3.0 compiler but any 85xx cross-compiler + should suffice. + +3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter). + The bin file should be converted from fffc0000 to ffffffff + +4) Setup the Flash Utility (tools menu) for: + + Determine the clock speed of the PCI bus and set SW9 accordingly + Note: the speed of the PCI bus defaults to the slowest PCI card + PlayBack the "default" register file for the SBC8560 + Select the uboot.bin file with zero bias + Select the initialize Target prior to programming + Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm + Select the erase base address from FFFC0000 to FFFFFFFF + Select the start address from 0 with size of 4000 + +5) Erase and Program |