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author | Stefan Roese <sr@denx.de> | 2015-01-09 13:39:22 (GMT) |
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committer | Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> | 2015-04-22 11:19:51 (GMT) |
commit | ed62756dcf5544e277d87c461a84c6274f42b765 (patch) | |
tree | 9695aa03ae956788fdfa983c9f57312528c238c2 /doc/SPL | |
parent | d15e74f16cc521da0e08060cda2c87307bd4363f (diff) | |
download | u-boot-fsl-qoriq-ed62756dcf5544e277d87c461a84c6274f42b765.tar.xz |
cmd_sf: Fix problem with "sf update" and unaligned length
On SoCFPGA, using "sf update" with an non-4byte aligned length leads
to a hangup (and reboot via watchdog). This is because of the unaligned
access in the cadence QSPI driver which is hard to prevent since the
data is written into a 4-byte wide FIFO. This patch fixes this problem
by changing the behavior of the last sector write (not sector aligned).
The new code is even simpler and copies the source data into the temp
buffer and now uses the temp buffer to write the complete sector. So
only one SPI sector write is used now instead of 2 in the old version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'doc/SPL')
0 files changed, 0 insertions, 0 deletions