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| author | Dave Liu <daveliu@freescale.com> | 2009-12-16 16:24:39 (GMT) |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 19:50:07 (GMT) |
| commit | 3e731aaba30c7011edf6391072eee845ed1b816f (patch) | |
| tree | ff32b3e1f2bbec7abfcd740f4dda254bd92cf0ab /doc | |
| parent | 1aa3d08a0244506b94031522e54fe06ee7a5ae0e (diff) | |
| download | u-boot-fsl-qoriq-3e731aaba30c7011edf6391072eee845ed1b816f.tar.xz | |
fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'doc')
0 files changed, 0 insertions, 0 deletions