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| author | Marek Vasut <marex@denx.de> | 2015-08-01 17:50:56 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 12:14:26 (GMT) |
| commit | 0ef88300379bb13b8de6c309ae60c9ca255dcc8d (patch) | |
| tree | b27da7770f9c97be6492f184d299ea10c2d2f2d4 /drivers/ddr/altera/sdram.c | |
| parent | 60bd0df018f5f1b6baa41d782b3b9b7065f04b68 (diff) | |
| download | u-boot-fsl-qoriq-0ef88300379bb13b8de6c309ae60c9ca255dcc8d.tar.xz | |
ddr: altera: sdram: Clean up set_sdr_addr_rw()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/ddr/altera/sdram.c')
| -rw-r--r-- | drivers/ddr/altera/sdram.c | 30 |
1 files changed, 10 insertions, 20 deletions
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index f4f3545..143f41b 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -371,34 +371,24 @@ static void set_sdr_dram_timing(void) static void set_sdr_addr_rw(void) { - int rows; - - debug("Configuring DRAMADDRW\n"); - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB); /* * SDRAM Failure When Accessing Non-Existent Memory - * Update Preloader to artificially increase the number of rows so - * that the memory thinks it has 4GB of RAM. - */ - rows = get_errata_rows(); - - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK, - rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB); - /* SDRAM Failure When Accessing Non-Existent Memory * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to * log2(number of chip select bits). Since there's only * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, * which is the same as "chip selects" - 1. */ - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK, - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << + const int rows = get_errata_rows(); + const u32 dram_addrw = + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | + (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB); + debug("Configuring DRAMADDRW\n"); + writel(dram_addrw, &sdr_ctrl->dram_addrw); } static void set_sdr_static_cfg(void) |