diff options
author | Simon Schwarz <simonschwarzcor@googlemail.com> | 2011-09-14 19:30:16 (GMT) |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-30 20:00:54 (GMT) |
commit | 12c2f1ee3c3e26950b39b779db4b6636759778ff (patch) | |
tree | 0d5ff19233dad1274a905c3ec5fd7bd662e3353e /drivers/mtd/nand/omap_gpmc.c | |
parent | bb085b87e587b5ea98519d95c8b24f603d91360a (diff) | |
download | u-boot-fsl-qoriq-12c2f1ee3c3e26950b39b779db4b6636759778ff.tar.xz |
spl: add NAND Library to new SPL
Adds NAND library to SPL.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'drivers/mtd/nand/omap_gpmc.c')
-rw-r--r-- | drivers/mtd/nand/omap_gpmc.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 99b9cef..5bbec48 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -61,6 +61,14 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, writeb(cmd, this->IO_ADDR_W); } +#ifdef CONFIG_SPL_BUILD +/* Check wait pin as dev ready indicator */ +int omap_spl_dev_ready(struct mtd_info *mtd) +{ + return gpmc_cfg->status & (1 << 8); +} +#endif + /* * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in * GPMC controller @@ -224,6 +232,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) } } +#ifndef CONFIG_SPL_BUILD /* * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc. * The default is to come up on s/w ecc @@ -280,6 +289,7 @@ void omap_nand_switch_ecc(int32_t hardware) nand->options &= ~NAND_OWN_BUFFERS; } +#endif /* CONFIG_SPL_BUILD */ /* * Board-specific NAND initialization. The following members of the @@ -338,7 +348,24 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay = 100; /* Default ECC mode */ +#ifndef CONFIG_SPL_BUILD nand->ecc.mode = NAND_ECC_SOFT; +#else + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_nand_oob; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + omap_hwecc_init(nand); + + if (nand->options & NAND_BUSWIDTH_16) + nand->read_buf = nand_read_buf16; + else + nand->read_buf = nand_read_buf; + nand->dev_ready = omap_spl_dev_ready; +#endif return 0; } |