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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-04-20 20:05:53 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-05-10 19:37:21 (GMT) |
| commit | 315e6a38f9d6380eb8295098f4a88a929cb02cde (patch) | |
| tree | d77442fdf18aa3d9093c913bc9cf1ac0e2f6fa77 /drivers/pinctrl | |
| parent | 9fc354e246fe466ad634617e12d092d6053503ed (diff) | |
| download | u-boot-fsl-qoriq-315e6a38f9d6380eb8295098f4a88a929cb02cde.tar.xz | |
rockchip: pinctrl: rk3399: add support for the SPI5 controller
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
through SPI5 to the appropriate pin-config
function; implements the pin-configuration
for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index 507bec4..6eb657f 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); break; + case PERIPH_ID_SPI5: + if (cs != 0) + goto err; + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK + | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK, + GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT + | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT + | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT + | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT); + break; default: + printf("%s: spi_id %d is not supported.\n", __func__, spi_id); goto err; } @@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + case PERIPH_ID_SPI5: pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); break; case PERIPH_ID_UART0: @@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_SPI1; case 52: return PERIPH_ID_SPI2; + case 132: + return PERIPH_ID_SPI5; case 57: return PERIPH_ID_I2C0; case 59: /* Note strange order */ |