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authorBin Meng <bmeng.cn@gmail.com>2017-03-16 14:26:27 (GMT)
committerBin Meng <bmeng.cn@gmail.com>2017-04-10 02:02:03 (GMT)
commitd24c7fbcc5e530bb5a2b5326869aaa2d7a61d607 (patch)
tree554bd94a3cad5bd697a9adfc6fc54cca60fbd3d1 /drivers/rtc
parentc04cf0a5717372f8546d07cdb6a13abcdcc5be85 (diff)
downloadu-boot-fsl-qoriq-d24c7fbcc5e530bb5a2b5326869aaa2d7a61d607.tar.xz
dm: rtc: Add 16-bit read/write support
At present there are only 8-bit and 32-bit read/write routines in the rtc uclass driver. This adds the 16-bit support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/rtc')
-rw-r--r--drivers/rtc/rtc-uclass.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c
index 300e9b3..89312c5 100644
--- a/drivers/rtc/rtc-uclass.c
+++ b/drivers/rtc/rtc-uclass.c
@@ -60,6 +60,36 @@ int rtc_write8(struct udevice *dev, unsigned int reg, int val)
return ops->write8(dev, reg, val);
}
+int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep)
+{
+ u16 value = 0;
+ int ret;
+ int i;
+
+ for (i = 0; i < sizeof(value); i++) {
+ ret = rtc_read8(dev, reg + i);
+ if (ret < 0)
+ return ret;
+ value |= ret << (i << 3);
+ }
+
+ *valuep = value;
+ return 0;
+}
+
+int rtc_write16(struct udevice *dev, unsigned int reg, u16 value)
+{
+ int i, ret;
+
+ for (i = 0; i < sizeof(value); i++) {
+ ret = rtc_write8(dev, reg + i, (value >> (i << 3)) & 0xff);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep)
{
u32 value = 0;