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authorJagan Teki <jagan@amarulasolutions.com>2017-06-06 05:31:48 (GMT)
committerStefano Babic <sbabic@denx.de>2017-07-12 07:42:33 (GMT)
commit97548d59478afec7e8041ed8463cc5248a61f30b (patch)
treede2aa517f00449e1a8a559a659bdca708433b9fe /drivers/serial
parent57d3e98f570a8d4cd0dac9c738d4574e00872d90 (diff)
downloadu-boot-fsl-qoriq-97548d59478afec7e8041ed8463cc5248a61f30b.tar.xz
serial: mxc: Move common init into _mxc_serial_init
Move the common initialization code into _mxc_serial_init so-that dm and non-dm can call this func. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/serial_mxc.c37
1 files changed, 17 insertions, 20 deletions
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index cf6f044..7a51e13 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -137,6 +137,21 @@ struct mxc_uart {
u32 ts;
};
+static void _mxc_serial_init(struct mxc_uart *base)
+{
+ writel(0, &base->cr1);
+ writel(0, &base->cr2);
+
+ while (!(readl(&base->cr2) & UCR2_SRST));
+
+ writel(0x704 | UCR3_ADNIMP, &base->cr3);
+ writel(0x8000, &base->cr4);
+ writel(0x2b, &base->esc);
+ writel(0, &base->tim);
+
+ writel(0, &base->ts);
+}
+
#ifndef CONFIG_DM_SERIAL
#ifndef CONFIG_MXC_UART_BASE
@@ -205,17 +220,7 @@ static int mxc_serial_tstc(void)
*/
static int mxc_serial_init(void)
{
- writel(0, &mxc_base->cr1);
- writel(0, &mxc_base->cr2);
-
- while (!(readl(&mxc_base->cr2) & UCR2_SRST));
-
- writel(0x704 | UCR3_ADNIMP, &mxc_base->cr3);
- writel(0x8000, &mxc_base->cr4);
- writel(0x2b, &mxc_base->esc);
- writel(0, &mxc_base->tim);
-
- writel(0, &mxc_base->ts);
+ _mxc_serial_init(mxc_base);
serial_setbrg();
@@ -271,16 +276,8 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
static int mxc_serial_probe(struct udevice *dev)
{
struct mxc_serial_platdata *plat = dev->platdata;
- struct mxc_uart *const uart = plat->reg;
- writel(0, &uart->cr1);
- writel(0, &uart->cr2);
- while (!(readl(&uart->cr2) & UCR2_SRST));
- writel(0x704 | UCR3_ADNIMP, &uart->cr3);
- writel(0x8000, &uart->cr4);
- writel(0x2b, &uart->esc);
- writel(0, &uart->tim);
- writel(0, &uart->ts);
+ _mxc_serial_init(plat->reg);
return 0;
}