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| author | Phil Edworthy <PHIL.EDWORTHY@renesas.com> | 2016-11-29 12:58:32 (GMT) |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2016-12-15 15:57:27 (GMT) |
| commit | 3c5695321929d3c3d1936cb8a7773566af0886b5 (patch) | |
| tree | 8cbc67503f2086e35dccf3f0e37e100141c066f7 /drivers/spi | |
| parent | 7d403f284c814d6df9f1d116e691d6468c75282a (diff) | |
| download | u-boot-fsl-qoriq-3c5695321929d3c3d1936cb8a7773566af0886b5.tar.xz | |
spi: cadence_qspi: Remove returns from end of void functions
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e81d678..39e31f6 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -199,7 +199,6 @@ void cadence_qspi_apb_controller_enable(void *reg_base) reg = readl(reg_base + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_ENABLE; writel(reg, reg_base + CQSPI_REG_CONFIG); - return; } void cadence_qspi_apb_controller_disable(void *reg_base) @@ -208,7 +207,6 @@ void cadence_qspi_apb_controller_disable(void *reg_base) reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~CQSPI_REG_CONFIG_ENABLE; writel(reg, reg_base + CQSPI_REG_CONFIG); - return; } /* Return 1 if idle, otherwise return 0 (busy). */ @@ -260,7 +258,6 @@ void cadence_qspi_apb_readdata_capture(void *reg_base, writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE); cadence_qspi_apb_controller_enable(reg_base); - return; } void cadence_qspi_apb_config_baudrate_div(void *reg_base, @@ -291,7 +288,6 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base, writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); - return; } void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) @@ -310,7 +306,6 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); - return; } void cadence_qspi_apb_chipselect(void *reg_base, @@ -345,7 +340,6 @@ void cadence_qspi_apb_chipselect(void *reg_base, writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); - return; } void cadence_qspi_apb_delay(void *reg_base, @@ -383,7 +377,6 @@ void cadence_qspi_apb_delay(void *reg_base, writel(reg, reg_base + CQSPI_REG_DELAY); cadence_qspi_apb_controller_enable(reg_base); - return; } void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) @@ -411,7 +404,6 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) writel(0, plat->regbase + CQSPI_REG_IRQMASK); cadence_qspi_apb_controller_enable(plat->regbase); - return; } static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, |