diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2017-04-10 22:02:50 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 15:38:41 (GMT) |
| commit | 890bafd752460b79c607e829f58bf88f0f8484b7 (patch) | |
| tree | ab339a62abdc6747fdc74e8e689831acbd3508b9 /drivers/spi | |
| parent | 5bf5250e9d1555aa388a810213fd85106a60388e (diff) | |
| download | u-boot-fsl-qoriq-890bafd752460b79c607e829f58bf88f0f8484b7.tar.xz | |
stm32f7: use clock driver to enable qspi controller clock
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/stm32_qspi.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 05358eb..f0434a4 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -17,6 +17,7 @@ #include <errno.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_defs.h> +#include <clk.h> DECLARE_GLOBAL_DATA_PTR; @@ -457,7 +458,20 @@ static int stm32_qspi_probe(struct udevice *bus) priv->max_hz = plat->max_hz; - clock_setup(QSPI_CLOCK_CFG); +#ifdef CONFIG_CLK + int ret; + struct clk clk; + ret = clk_get_by_index(bus, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(bus, "failed to enable clock\n"); + return ret; + } +#endif setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); |