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authorPhil Sutter <phil@nwl.cc>2015-12-25 13:41:19 (GMT)
committerStefan Roese <sr@denx.de>2016-01-14 13:08:59 (GMT)
commit7e1e59a7b7da45361761ab1439c2751f4cae4163 (patch)
tree70e477b55b37f09fdfffe1a34a1dd71c09a9c601 /drivers
parent3c1496cd4d964ba1a46c449289b49230cd712ddb (diff)
downloadu-boot-fsl-qoriq-7e1e59a7b7da45361761ab1439c2751f4cae4163.tar.xz
axp: Fix debugging support in DDR3 write leveling
If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing. In addition to that, get rid of debug output printing non-existent counter variable. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ddr/marvell/axp/ddr3_write_leveling.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c
index df3a3df..da384f3 100644
--- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c
+++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c
@@ -22,6 +22,8 @@
DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n")
#ifdef MV_DEBUG_WL
+#define DEBUG_WL_S(s) puts(s)
+#define DEBUG_WL_D(d, l) printf("%x", d)
#define DEBUG_RL_S(s) \
debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s)
#define DEBUG_RL_D(d, l) \
@@ -1229,8 +1231,6 @@ static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
DEBUG_WL_FULL_D((u32) phase, 1);
DEBUG_WL_FULL_S(", Delay = ");
DEBUG_WL_FULL_D((u32) delay, 1);
- DEBUG_WL_FULL_S(", Counter = ");
- DEBUG_WL_FULL_D((u32) i, 1);
DEBUG_WL_FULL_S("\n");
/* Drive DQS high for one cycle - All data PUPs */