diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2015-08-10 11:22:54 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-28 16:33:19 (GMT) |
| commit | 8af1be7678c1fd9bc03b28f0756c586fb3d47d29 (patch) | |
| tree | 62cab0e53154b1b52ed734761f5f469dda2fec92 /drivers | |
| parent | 2d9efa1227262249d381ed5d9d341cbdba76e62d (diff) | |
| download | u-boot-fsl-qoriq-8af1be7678c1fd9bc03b28f0756c586fb3d47d29.tar.xz | |
usb: dwc3: dwc3-omap: Use the clear register inorder to clear the interrupts
Writing "0x00" to the USBOTGSS_IRQENABLE_SET_MISC and
USBOTGSS_IRQENABLE_SET_0 doesn't disable the interrupts. Used
USBOTGSS_IRQENABLE_CLR_MISC and USBOTGSS_IRQENABLE_CLR_0 instead.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/dwc3/dwc3-omap.c | 46 |
1 files changed, 28 insertions, 18 deletions
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index 46af109..ac9a856 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -91,6 +91,16 @@ #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) +#define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \ + USBOTGSS_IRQMISC_DRVVBUS_RISE | \ + USBOTGSS_IRQMISC_CHRGVBUS_RISE | \ + USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \ + USBOTGSS_IRQMISC_IDPULLUP_RISE | \ + USBOTGSS_IRQMISC_DRVVBUS_FALL | \ + USBOTGSS_IRQMISC_CHRGVBUS_FALL | \ + USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \ + USBOTGSS_IRQMISC_IDPULLUP_FALL) + /* UTMI_OTG_CTRL REGISTER */ #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) @@ -187,6 +197,18 @@ static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) omap->irq0_offset, value); } +static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) +{ + dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + + omap->irqmisc_offset, value); +} + +static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) +{ + dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - + omap->irq0_offset, value); +} + static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, enum omap_dwc3_vbus_id_status status) { @@ -285,30 +307,18 @@ static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) { - u32 reg; - /* enable all IRQs */ - reg = USBOTGSS_IRQO_COREIRQ_ST; - dwc3_omap_write_irq0_set(omap, reg); - - reg = (USBOTGSS_IRQMISC_OEVT | - USBOTGSS_IRQMISC_DRVVBUS_RISE | - USBOTGSS_IRQMISC_CHRGVBUS_RISE | - USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | - USBOTGSS_IRQMISC_IDPULLUP_RISE | - USBOTGSS_IRQMISC_DRVVBUS_FALL | - USBOTGSS_IRQMISC_CHRGVBUS_FALL | - USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | - USBOTGSS_IRQMISC_IDPULLUP_FALL); - - dwc3_omap_write_irqmisc_set(omap, reg); + dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST); + + dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS); } static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) { /* disable all IRQs */ - dwc3_omap_write_irqmisc_set(omap, 0x00); - dwc3_omap_write_irq0_set(omap, 0x00); + dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST); + + dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS); } static void dwc3_omap_map_offset(struct dwc3_omap *omap) |