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authorAndy Fleming <afleming@freescale.com>2009-02-04 00:26:41 (GMT)
committerBen Warren <biggerbadderben@gmail.com>2009-02-10 06:52:32 (GMT)
commit9e5be8214ba751436e57c3be044bf6dccb9a6687 (patch)
treec3e969d2f69338bc9b1f078a45c40238004fdf67 /include/asm-mips/isadep.h
parent09fcc8b5d86903b76e7e4d1d879d6f4bca25c27b (diff)
downloadu-boot-fsl-qoriq-9e5be8214ba751436e57c3be044bf6dccb9a6687.tar.xz
tsec: Fix a bug in soft-resetting
SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30 clock cycles, so it's been mostly working. But we had no guarantee, and at slower bitrates, it's just over a microsecond (over 1000 clock cycles). This enforces a 2 microsecond gap between assertion and deassertion. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'include/asm-mips/isadep.h')
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