diff options
| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-11-21 03:36:48 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-12-05 16:31:45 (GMT) |
| commit | 02fb2761576be8096ebf1b3f961a2cdb21b422ae (patch) | |
| tree | 70cd556e7498ef63f2d51519958cfc2994c73950 /include/fsl_ddr_sdram.h | |
| parent | 5a17b8b5dab8973089b7400d05f8503d56f29370 (diff) | |
| download | u-boot-fsl-qoriq-02fb2761576be8096ebf1b3f961a2cdb21b422ae.tar.xz | |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
| -rw-r--r-- | include/fsl_ddr_sdram.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 36bd9d7..1404c57 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -374,7 +374,8 @@ typedef struct memctl_options_s { unsigned int additive_latency_override_value; unsigned int clk_adjust; /* */ - unsigned int cpo_override; + unsigned int cpo_override; /* override timing_cfg_2[CPO]*/ + unsigned int cpo_sample; /* optimize debug_29[24:31] */ unsigned int write_data_delay; /* DQS adjust */ unsigned int cswl_override; |