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authorYork Sun <yorksun@freescale.com>2014-08-21 23:13:22 (GMT)
committerYork Sun <yorksun@freescale.com>2014-09-25 15:36:18 (GMT)
commitbb5783224b9b12eecf406761f82e3de2a2ca9dae (patch)
tree5ac9b5958714c356191ecf2a7a2cd03d76cd6aac /include/fsl_ddr_sdram.h
parentd9c68b1444acb383684636eb856fd7e4cec04129 (diff)
downloadu-boot-fsl-qoriq-bb5783224b9b12eecf406761f82e3de2a2ca9dae.tar.xz
driver/ddr/fsl: Fix tXP and tCKE
The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
-rw-r--r--include/fsl_ddr_sdram.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index d03901f..5b03c14 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -51,7 +51,6 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_SYS_FSL_DDR3)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
@@ -352,7 +351,6 @@ typedef struct memctl_options_s {
unsigned int twot_en;
unsigned int threet_en;
unsigned int bstopre;
- unsigned int tcke_clock_pulse_width_ps; /* tCKE */
unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
/* Rtt impedance */