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| author | Stefan Roese <sr@denx.de> | 2008-10-13 08:45:14 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-21 15:35:02 (GMT) |
| commit | 43cbce69d48d052574d71f50724be546d90a46a4 (patch) | |
| tree | 99013b2e419ce379b21591d2b2ecb3f476eb120f /include | |
| parent | d7b26d58328f137471ea97de382bfa63f7239931 (diff) | |
| download | u-boot-fsl-qoriq-43cbce69d48d052574d71f50724be546d90a46a4.tar.xz | |
ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/ppc4xx-ebc.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h index d180e04..9680f70 100644 --- a/include/asm-ppc/ppc4xx-ebc.h +++ b/include/asm-ppc/ppc4xx-ebc.h @@ -35,7 +35,38 @@ #define CONFIG_EBC_PPC4xx_IBM_VER1 #endif +/* + * Define the max number of EBC banks (chip selects) + */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EZ) || \ + defined(CONFIG_440GP) || defined(CONFIG_440GX) +#define EBC_NUM_BANKS 8 +#endif + +#if defined(CONFIG_405EP) +#define EBC_NUM_BANKS 5 +#endif + +#if defined(CONFIG_405EX) || \ + defined(CONFIG_460SX) +#define EBC_NUM_BANKS 4 +#endif + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define EBC_NUM_BANKS 6 +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define EBC_NUM_BANKS 3 +#endif + /* Bank Configuration Register */ +#define EBC_BXCR(n) (n) +#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) + #define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) #define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) #define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) |