diff options
| -rw-r--r-- | arch/nios2/cpu/cpu.c | 3 | ||||
| -rw-r--r-- | arch/nios2/cpu/interrupts.c | 22 | ||||
| -rw-r--r-- | arch/nios2/cpu/sysid.c | 8 | ||||
| -rw-r--r-- | arch/nios2/cpu/u-boot.lds | 2 | ||||
| -rw-r--r-- | arch/nios2/include/asm/nios2.h (renamed from include/nios2.h) | 6 | ||||
| -rw-r--r-- | board/altera/common/epled.c | 46 | ||||
| -rw-r--r-- | board/altera/nios2-generic/Makefile | 2 | ||||
| -rw-r--r-- | board/altera/nios2-generic/custom_fpga.h | 127 | ||||
| -rw-r--r-- | board/altera/nios2-generic/nios2-generic.c | 3 | ||||
| -rw-r--r-- | board/altera/nios2-generic/text_base.S | 21 | ||||
| -rw-r--r-- | board/altera/nios2-generic/u-boot.lds | 118 | ||||
| -rw-r--r-- | drivers/serial/altera_jtag_uart.c | 20 | ||||
| -rw-r--r-- | drivers/serial/altera_uart.c | 39 | ||||
| -rw-r--r-- | drivers/serial/opencores_yanu.c | 87 | ||||
| -rw-r--r-- | include/configs/nios2-generic.h | 11 | ||||
| -rw-r--r-- | include/nios2-io.h | 153 | ||||
| -rw-r--r-- | include/nios2-yanu.h | 99 |
17 files changed, 253 insertions, 514 deletions
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 86f94b7..39ae972 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -6,8 +6,7 @@ */ #include <common.h> -#include <nios2.h> -#include <nios2-io.h> +#include <asm/nios2.h> #include <asm/cache.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index c4bed22..9d7e193 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -9,8 +9,7 @@ */ -#include <nios2.h> -#include <nios2-io.h> +#include <asm/nios2.h> #include <asm/types.h> #include <asm/io.h> #include <asm/ptrace.h> @@ -21,6 +20,25 @@ #include <status_led.h> #endif +typedef volatile struct { + unsigned status; /* Timer status reg */ + unsigned control; /* Timer control reg */ + unsigned periodl; /* Timeout period low */ + unsigned periodh; /* Timeout period high */ + unsigned snapl; /* Snapshot low */ + unsigned snaph; /* Snapshot high */ +} nios_timer_t; + +/* status register */ +#define NIOS_TIMER_TO (1 << 0) /* Timeout */ +#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ + +/* control register */ +#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ +#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ +#define NIOS_TIMER_START (1 << 2) /* Start timer */ +#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ + #if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) #error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) #endif diff --git a/arch/nios2/cpu/sysid.c b/arch/nios2/cpu/sysid.c index 943bff8..50819b2 100644 --- a/arch/nios2/cpu/sysid.c +++ b/arch/nios2/cpu/sysid.c @@ -11,12 +11,16 @@ #include <command.h> #include <asm/io.h> -#include <nios2-io.h> #include <linux/time.h> +typedef volatile struct { + unsigned id; /* The system build id */ + unsigned timestamp; /* Timestamp */ +} nios_sysid_t; + void display_sysid (void) { - struct nios_sysid_t *sysid = (struct nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE; + nios_sysid_t *sysid = (nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE; struct tm t; char asc[32]; time_t stamp; diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index be92e8e..6e174be 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> OUTPUT_FORMAT("elf32-littlenios2") OUTPUT_ARCH(nios2) @@ -12,6 +13,7 @@ ENTRY(_start) SECTIONS { + . = CONFIG_SYS_MONITOR_BASE; .text : { arch/nios2/cpu/start.o (.text) diff --git a/include/nios2.h b/arch/nios2/include/asm/nios2.h index 0539ec3..abe4df3 100644 --- a/include/nios2.h +++ b/arch/nios2/include/asm/nios2.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __NIOS2_H__ -#define __NIOS2_H__ +#ifndef __ASM_NIOS2_H__ +#define __ASM_NIOS2_H__ /*------------------------------------------------------------------------ * Control registers -- use with wrctl() & rdctl() @@ -37,4 +37,4 @@ #define CACHE_BYPASS(a) ((a) | 0x80000000) #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) -#endif /* __NIOS2_H__ */ +#endif /* __ASM_NIOS2_H__ */ diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c deleted file mode 100644 index 580d590..0000000 --- a/board/altera/common/epled.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <nios2-io.h> -#include <status_led.h> - -/* The LED port is configured as output only, so we - * must track the state manually. - */ -static led_id_t val = 0; - -void __led_init (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_set (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - writel (val, &pio->data); -} - -void __led_toggle (led_id_t mask) -{ - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; - - val ^= mask; - writel (val, &pio->data); -} diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile index aa362b3..5e4192c 100644 --- a/board/altera/nios2-generic/Makefile +++ b/board/altera/nios2-generic/Makefile @@ -8,5 +8,3 @@ obj-y := nios2-generic.o obj-$(CONFIG_CMD_IDE) += ../common/cfide.o -obj-$(CONFIG_EPLED) += ../common/epled.o -obj-y += text_base.o diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index fd3ec9a..cf75d35 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -1,78 +1,89 @@ /* - * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * This header is generated by sopc2dts + * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl> + * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file is generated by sopc-create-config-files. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CUSTOM_FPGA_H_ #define _CUSTOM_FPGA_H_ -/* generated from std_1c20.sopc */ - -/* cpu.data_master is a altera_nios2 */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SYS_RESET_ADDR 0x00000000 -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 -#define CONFIG_SYS_ICACHE_SIZE 4096 -#define CONFIG_SYS_ICACHELINE_SIZE 32 -#define CONFIG_SYS_DCACHE_SIZE 2048 -#define CONFIG_SYS_DCACHELINE_SIZE 4 - -/* sdram.s1 is a altera_avalon_new_sdram_controller */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 - -/* uart1.s1 is a altera_avalon_uart */ -#define CONFIG_SYS_UART_BASE 0x82120840 -#define CONFIG_SYS_UART_FREQ 50000000 -#define CONFIG_SYS_UART_BAUD 115200 - -/* lan91c111.s1 is a altera_avalon_lan91c111 */ -#define CONFIG_SMC91111_BASE 0x82110300 -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT - -/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ -#define EPCS_CONTROLLER_REG_BASE 0x82100200 -#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } -#define CONFIG_ALTERA_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO +/* generated from qsys_ghrd_3c120.sopcinfo */ + +/* Dumping slaves of cpu.data_master */ + +/* cpu.jtag_debug_module is a altera_nios2_qsys */ +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_DCACHELINE_SIZE 32 +#define CONFIG_SYS_ICACHELINE_SIZE 32 +#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020 +#define CONFIG_SYS_ICACHE_SIZE 32768 +#define CONFIG_SYS_RESET_ADDR 0xc2800000 +#define IO_REGION_BASE 0xE0000000 + +/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */ + +/* ddr2_bot.s1 is a altmemddr2 */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_io.m0 */ + +/* timer_1ms.s1 is a altera_avalon_timer */ +#define CONFIG_SYS_TIMER_IRQ 11 +#define CONFIG_SYS_TIMER_FREQ 125000000 +#define CONFIG_SYS_TIMER_BASE 0xE8400000 + +/* sysid.control_slave is a altera_avalon_sysid_qsys */ +#define CONFIG_SYS_SYSID_BASE 0xE8004D40 /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ -#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 +#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50 + +/* tse_mac.control_port is a triple_speed_ethernet */ +#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400 +#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000 +#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000 +#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000 +#define CONFIG_ALTERA_TSE +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18 +#define CONFIG_SYS_ALTERA_TSE_FLAGS 1 + +/* uart.s1 is a altera_avalon_uart */ +#define CONFIG_SYS_UART_BAUD 115200 +#define CONFIG_SYS_UART_BASE 0xE8004C80 +#define CONFIG_SYS_UART_FREQ 62500000 + +/* user_led_pio_8out.s1 is a altera_avalon_pio */ +#define USER_LED_PIO_8OUT_BASE 0xE8004CC0 -/* led_pio.s1 is a altera_avalon_pio */ -#define LED_PIO_BASE 0x82120870 -#define LED_PIO_WIDTH 8 -#define LED_PIO_RSTVAL 0x0 +/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */ +#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0 +#define USER_DIPSW_PIO_8IN_IRQ 8 -/* high_res_timer.s1 is a altera_avalon_timer */ -#define CONFIG_SYS_TIMER_BASE 0x82120820 -#define CONFIG_SYS_TIMER_IRQ 3 -#define CONFIG_SYS_TIMER_FREQ 50000000 +/* user_pb_pio_4in.s1 is a altera_avalon_pio */ +#define USER_PB_PIO_4IN_BASE 0xE8004D00 +#define USER_PB_PIO_4IN_IRQ 9 + +/* cfi_flash_64m.uas is a altera_generic_tristate_controller */ +#define CFI_FLASH_64M_BASE 0xE0000000 /* ext_flash.s1 is a altera_avalon_cfi_flash */ -#define CONFIG_SYS_FLASH_BASE 0x80000000 +#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 -#define CONFIG_SYS_SRAM_SIZE 0x00100000 - -/* sysid.control_slave is a altera_avalon_sysid */ -#define CONFIG_SYS_SYSID_BASE 0x821208b8 +#define CONFIG_SYS_MAX_FLASH_SECT 512 #endif /* _CUSTOM_FPGA_H_ */ diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index 5ab9471..834cbeb 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -14,8 +14,6 @@ #include <asm/io.h> #include <asm/gpio.h> -void text_base_hook(void); /* nop hook for text_base.S */ - #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \ defined(CONFIG_CFI_FLASH_MTD) static void __early_flash_cmd_reset(void) @@ -30,7 +28,6 @@ void early_flash_cmd_reset(void) int board_early_init_f(void) { - text_base_hook(); #ifdef CONFIG_ALTERA_PIO #ifdef LED_PIO_BASE altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o', diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S deleted file mode 100644 index f236db1..0000000 --- a/board/altera/nios2-generic/text_base.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * text_base - * - * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <config.h> - -#ifdef CONFIG_SYS_MONITOR_BASE - .text - /* text base used in link script u-boot.lds */ - .global text_base - .equ text_base,CONFIG_SYS_MONITOR_BASE - /* dummy func to let linker include this file */ - .global text_base_hook -text_base_hook: - ret -#endif diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds deleted file mode 100644 index e35fae5..0000000 --- a/board/altera/nios2-generic/u-boot.lds +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -OUTPUT_FORMAT("elf32-littlenios2") -OUTPUT_ARCH(nios2) -ENTRY(_start) - -SECTIONS -{ - . = text_base; - .text : - { - arch/nios2/cpu/start.o (.text) - *(.text) - *(.text.*) - *(.gnu.linkonce.t*) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - *(.gnu.linkonce.r*) - } - . = ALIGN (4); - _etext = .; - PROVIDE (etext = .); - - /* CMD TABLE - sandwich this in between text and data so - * the initialization code relocates the command table as - * well -- admittedly, this is just pure laziness ;-) - */ - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - /* INIT DATA sections - "Small" data (see the gcc -G option) - * is always gp-relative. Here we make all init data sections - * adjacent to simplify the startup code -- and provide - * the global pointer for gp-relative access. - */ - _data = .; - .data : - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - } - - . = ALIGN(16); - _gp = .; /* Global pointer addr */ - PROVIDE (gp = .); - - .sdata : - { - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - } - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* UNINIT DATA - Small uninitialized data is first so it's - * adjacent to sdata and can be referenced via gp. The normal - * bss follows. We keep it adjacent to simplify init code. - */ - __bss_start = .; - .sbss (NOLOAD) : - { - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } - . = ALIGN(4); - .bss (NOLOAD) : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - *(.scommon) - } - . = ALIGN(4); - __bss_end = .; - PROVIDE (end = .); - - /* DEBUG -- symbol table, string table, etc. etc. - */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 0573c7a..9a81402 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -8,10 +8,28 @@ #include <common.h> #include <watchdog.h> #include <asm/io.h> -#include <nios2-io.h> #include <linux/compiler.h> #include <serial.h> +typedef volatile struct { + unsigned data; /* Data register */ + unsigned control; /* Control register */ +} nios_jtag_t; + +/* data register */ +#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ +#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ +#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ + +/* control register */ +#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ +#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ +#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ +#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ +#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ +#define NIOS_JTAG_RRDY (1 << 12) /* read available */ +#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ + DECLARE_GLOBAL_DATA_PTR; /*------------------------------------------------------------------ diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index d620528..d6b1484 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -9,10 +9,47 @@ #include <common.h> #include <watchdog.h> #include <asm/io.h> -#include <nios2-io.h> #include <linux/compiler.h> #include <serial.h> +typedef volatile struct { + unsigned rxdata; /* Rx data reg */ + unsigned txdata; /* Tx data reg */ + unsigned status; /* Status reg */ + unsigned control; /* Control reg */ + unsigned divisor; /* Baud rate divisor reg */ + unsigned endofpacket; /* End-of-packet reg */ +} nios_uart_t; + +/* status register */ +#define NIOS_UART_PE (1 << 0) /* parity error */ +#define NIOS_UART_FE (1 << 1) /* frame error */ +#define NIOS_UART_BRK (1 << 2) /* break detect */ +#define NIOS_UART_ROE (1 << 3) /* rx overrun */ +#define NIOS_UART_TOE (1 << 4) /* tx overrun */ +#define NIOS_UART_TMT (1 << 5) /* tx empty */ +#define NIOS_UART_TRDY (1 << 6) /* tx ready */ +#define NIOS_UART_RRDY (1 << 7) /* rx ready */ +#define NIOS_UART_E (1 << 8) /* exception */ +#define NIOS_UART_DCTS (1 << 10) /* cts change */ +#define NIOS_UART_CTS (1 << 11) /* cts */ +#define NIOS_UART_EOP (1 << 12) /* eop detected */ + +/* control register */ +#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ +#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ +#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ +#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ +#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ +#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ +#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ +#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ +#define NIOS_UART_IE (1 << 8) /* exception int ena */ +#define NIOS_UART_TBRK (1 << 9) /* transmit break */ +#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ +#define NIOS_UART_RTS (1 << 11) /* rts */ +#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ + DECLARE_GLOBAL_DATA_PTR; /*------------------------------------------------------------------ diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index d4ed60c..f68c8d0 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -1,4 +1,8 @@ /* + * Altera NiosII YANU serial interface by Imagos + * please see http://www.opencores.org/project,yanu for + * information/downloads + * * Copyright 2010, Renato Andreola <renato.andreola@imagos.it> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,7 +11,6 @@ #include <common.h> #include <watchdog.h> #include <asm/io.h> -#include <nios2-yanu.h> #include <serial.h> DECLARE_GLOBAL_DATA_PTR; @@ -16,6 +19,88 @@ DECLARE_GLOBAL_DATA_PTR; /* YANU Imagos serial port */ /*-----------------------------------------------------------------*/ +#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ +#define YANU_FIFO_SIZE (16) +#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) +#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) + +#define YANU_RXFIFO_DLY (10*11) +#define YANU_TXFIFO_THR (10) +#define YANU_DATA_CHAR_MASK (0xFF) + +/* data register */ +#define YANU_DATA_OFFSET (0) /* data register offset */ + +#define YANU_CONTROL_OFFSET (4) /* control register offset */ +/* interrupt enable */ +#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ +#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ +#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ +#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ +#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ +#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ +/* control bits */ +#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ +#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */ +#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */ +#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */ +#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */ +#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */ +#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */ +#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */ +/* tuning part */ +#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */ +#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */ +#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */ +#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */ + +#define YANU_BAUD_OFFSET (8) /* baud register offset */ +#define YANU_BAUDM (1<<0) /* baud mantissa lsb */ +#define YANU_BAUDM_N (12) /* ...its bit filed length */ +#define YANU_BAUDE (1<<12) /* baud exponent lsb */ +#define YANU_BAUDE_N (4) /* ...its bit field length */ + +#define YANU_ACTION_OFFSET (12) /* action register... write only */ +#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */ +#define YANU_ACTION_ROE (1<<1) /* reset oe */ +#define YANU_ACTION_RBRK (1<<2) /* reset brk */ +#define YANU_ACTION_RFE (1<<3) /* reset fe */ +#define YANU_ACTION_RPE (1<<4) /* reset pe */ +#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */ +#define YANU_ACTION_SOE (1<<6) /* set oe */ +#define YANU_ACTION_SBRK (1<<7) /* set brk */ +#define YANU_ACTION_SFE (1<<8) /* set fe */ +#define YANU_ACTION_SPE (1<<9) /* set pe */ +#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */ +#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */ +#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */ +#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */ +#define YANU_ACTION_STRDY (1<<14) /* set trdy */ + +#define YANU_STATUS_OFFSET (16) +#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */ +#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */ +#define YANU_STATUS_OE (1<<2) /* rx overrun error */ +#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */ +#define YANU_STATUS_FE (1<<4) /* rx framing error flag */ +#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */ +#define YANU_RFIFO_CHARS_POS (6) +#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */ +#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ +#define YANU_TFIFO_CHARS_POS (11) +#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */ +#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ + +typedef volatile struct { + volatile unsigned data; + volatile unsigned control; /* control register (RW) 32-bit */ + volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */ + volatile unsigned action; /* action register (W) 32-bit */ + volatile unsigned status; /* status register (R) 32-bit */ + volatile unsigned magic; /* magic register (R) 32-bit */ +} yanu_uart_t; + static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; static void oc_serial_setbrg(void) diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 51b1d00..6247bf1 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -22,7 +22,7 @@ /* * SERIAL */ -#define CONFIG_ALTERA_UART +#define CONFIG_ALTERA_JTAG_UART #if defined(CONFIG_ALTERA_JTAG_UART) # define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE #else @@ -56,6 +56,9 @@ #define CONFIG_BOARD_SPECIFIC_LED #define CONFIG_GPIO_LED /* Enable GPIO LED driver */ #define CONFIG_GPIO /* Enable GPIO driver */ +#define LED_PIO_BASE USER_LED_PIO_8OUT_BASE +#define LED_PIO_WIDTH 8 +#define LED_PIO_RSTVAL 0xff #define STATUS_LED_BIT 0 /* Bit-0 on GPIO */ #define STATUS_LED_STATE 1 /* Blinking */ @@ -86,6 +89,10 @@ # define CONFIG_CMD_PING #endif +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the @@ -95,7 +102,7 @@ */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ #define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \ CONFIG_SYS_MONITOR_LEN) | \ diff --git a/include/nios2-io.h b/include/nios2-io.h deleted file mode 100644 index 6f1ae50..0000000 --- a/include/nios2-io.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * Altera Nios2 Standard Peripherals - ************************************************************************/ - -#ifndef __NIOS2IO_H__ -#define __NIOS2IO_H__ - -/*------------------------------------------------------------------------ - * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_uart_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned divisor; /* Baud rate divisor reg */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_uart_t; - -/* status register */ -#define NIOS_UART_PE (1 << 0) /* parity error */ -#define NIOS_UART_FE (1 << 1) /* frame error */ -#define NIOS_UART_BRK (1 << 2) /* break detect */ -#define NIOS_UART_ROE (1 << 3) /* rx overrun */ -#define NIOS_UART_TOE (1 << 4) /* tx overrun */ -#define NIOS_UART_TMT (1 << 5) /* tx empty */ -#define NIOS_UART_TRDY (1 << 6) /* tx ready */ -#define NIOS_UART_RRDY (1 << 7) /* rx ready */ -#define NIOS_UART_E (1 << 8) /* exception */ -#define NIOS_UART_DCTS (1 << 10) /* cts change */ -#define NIOS_UART_CTS (1 << 11) /* cts */ -#define NIOS_UART_EOP (1 << 12) /* eop detected */ - -/* control register */ -#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ -#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ -#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ -#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ -#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_UART_IE (1 << 8) /* exception int ena */ -#define NIOS_UART_TBRK (1 << 9) /* transmit break */ -#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ -#define NIOS_UART_RTS (1 << 11) /* rts */ -#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ - - -/*------------------------------------------------------------------------ - * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_timer_t { - unsigned status; /* Timer status reg */ - unsigned control; /* Timer control reg */ - unsigned periodl; /* Timeout period low */ - unsigned periodh; /* Timeout period high */ - unsigned snapl; /* Snapshot low */ - unsigned snaph; /* Snapshot high */ -}nios_timer_t; - -/* status register */ -#define NIOS_TIMER_TO (1 << 0) /* Timeout */ -#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ - -/* control register */ -#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ -#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ -#define NIOS_TIMER_START (1 << 2) /* Start timer */ -#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ - - -/*------------------------------------------------------------------------ - * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_pio_t { - unsigned int data; /* Data value at each PIO in/out */ - unsigned int direction; /* Data direct. for each PIO bit */ - unsigned int interruptmask; /* Per-bit IRQ enable/disable */ - unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ -}nios_pio_t; - -/* direction register */ -#define NIOS_PIO_OUT (1) /* PIO bit is output */ -#define NIOS_PIO_IN (0) /* PIO bit is input */ - - -/*------------------------------------------------------------------------ - * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf) - *----------------------------------------------------------------------*/ -typedef volatile struct nios_spi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; /* (master only) */ - unsigned slaveselect; /* SPI slave select mask (master only) */ -}nios_spi_t; - -/* status register */ -#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ -#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ -#define NIOS_SPI_TMT (1 << 5) /* tx empty */ -#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ -#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ -#define NIOS_SPI_E (1 << 8) /* exception */ - -/* control register */ -#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_SPI_IE (1 << 8) /* exception int ena */ -#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ - -/*------------------------------------------------------------------------ - * JTAG UART - *----------------------------------------------------------------------*/ -typedef volatile struct nios_jtag_t { - unsigned data; /* Data register */ - unsigned control; /* Control register */ -}nios_jtag_t; - -/* data register */ -#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ -#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ -#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ - -/* control register */ -#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ -#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ -#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ -#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ -#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ -#define NIOS_JTAG_RRDY (1 << 12) /* read available */ -#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ - -/*------------------------------------------------------------------------ - * SYSTEM ID - *----------------------------------------------------------------------*/ -typedef volatile struct nios_sysid_t { - unsigned id; /* The system build id*/ - unsigned timestamp; /* Timestamp */ -}nios_sysid_t; - -#endif /* __NIOS2IO_H__ */ diff --git a/include/nios2-yanu.h b/include/nios2-yanu.h deleted file mode 100644 index 6c16f5b..0000000 --- a/include/nios2-yanu.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2006, Imagos S.a.s <www.imagos.it> - * Renato Andreola <renato.andreola@imagos.it> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * Altera NiosII YANU serial interface by Imagos - * please see http://www.opencores.org/project,yanu for - * information/downloads - ************************************************************************/ - -#ifndef __NIOS2_YANU_H__ -#define __NIOS2_YANU_H__ - -#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ -#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ -#define YANU_FIFO_SIZE (16) -#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) -#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) - -#define YANU_RXFIFO_DLY (10*11) -#define YANU_TXFIFO_THR (10) -#define YANU_DATA_CHAR_MASK (0xFF) - -/* data register */ -#define YANU_DATA_OFFSET (0) /* data register offset */ - -#define YANU_CONTROL_OFFSET (4) /* control register offset */ -/* interrupt enable */ -#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ -#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ -#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ -#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ -#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ -#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ -/* control bits */ -#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ -#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */ -#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */ -#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */ -#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */ -#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */ -#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */ -#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */ -/* tuning part */ -#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */ -#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */ -#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */ -#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */ - -#define YANU_BAUD_OFFSET (8) /* baud register offset */ -#define YANU_BAUDM (1<<0) /* baud mantissa lsb */ -#define YANU_BAUDM_N (12) /* ...its bit filed length */ -#define YANU_BAUDE (1<<12) /* baud exponent lsb */ -#define YANU_BAUDE_N (4) /* ...its bit field length */ - -#define YANU_ACTION_OFFSET (12) /* action register... write only */ -#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */ -#define YANU_ACTION_ROE (1<<1) /* reset oe */ -#define YANU_ACTION_RBRK (1<<2) /* reset brk */ -#define YANU_ACTION_RFE (1<<3) /* reset fe */ -#define YANU_ACTION_RPE (1<<4) /* reset pe */ -#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */ -#define YANU_ACTION_SOE (1<<6) /* set oe */ -#define YANU_ACTION_SBRK (1<<7) /* set brk */ -#define YANU_ACTION_SFE (1<<8) /* set fe */ -#define YANU_ACTION_SPE (1<<9) /* set pe */ -#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */ -#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */ -#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */ -#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */ -#define YANU_ACTION_STRDY (1<<14) /* set trdy */ - -#define YANU_STATUS_OFFSET (16) -#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */ -#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */ -#define YANU_STATUS_OE (1<<2) /* rx overrun error */ -#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */ -#define YANU_STATUS_FE (1<<4) /* rx framing error flag */ -#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */ -#define YANU_RFIFO_CHARS_POS (6) -#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */ -#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ -#define YANU_TFIFO_CHARS_POS (11) -#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */ -#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ - -typedef volatile struct yanu_uart_t { - volatile unsigned data; - volatile unsigned control; /* control register (RW) 32-bit */ - volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */ - volatile unsigned action; /* action register (W) 32-bit */ - volatile unsigned status; /* status register (R) 32-bit */ - volatile unsigned magic; /* magic register (R) 32-bit */ -} yanu_uart_t; - -#endif |