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-rw-r--r--arch/arm/include/asm/arch-rockchip/grf_rk3288.h178
-rw-r--r--drivers/pinctrl/rockchip/pinctrl_rk3288.c118
2 files changed, 296 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index fbc4a0d..818e4c5 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -283,6 +283,163 @@ enum {
GPIO3C0_EMMC_CMD,
};
+/* GRF_GPIO3DL_IOMUX */
+enum {
+ GPIO3D3_SHIFT = 12,
+ GPIO3D3_MASK = 7,
+ GPIO3D3_GPIO = 0,
+ GPIO3D3_FLASH1_DATA3,
+ GPIO3D3_HOST_DOUT3,
+ GPIO3D3_MAC_RXD3,
+ GPIO3D3_SDIO1_DATA3,
+
+ GPIO3D2_SHIFT = 8,
+ GPIO3D2_MASK = 7,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_FLASH1_DATA2,
+ GPIO3D2_HOST_DOUT2,
+ GPIO3D2_MAC_RXD2,
+ GPIO3D2_SDIO1_DATA2,
+
+ GPIO3D1_SHIFT = 4,
+ GPIO3D1_MASK = 7,
+ GPIO3D1_GPIO = 0,
+ GPIO3DL1_FLASH1_DATA1,
+ GPIO3D1_HOST_DOUT1,
+ GPIO3D1_MAC_TXD3,
+ GPIO3D1_SDIO1_DATA1,
+
+ GPIO3D0_SHIFT = 0,
+ GPIO3D0_MASK = 7,
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_FLASH1_DATA0,
+ GPIO3D0_HOST_DOUT0,
+ GPIO3D0_MAC_TXD2,
+ GPIO3D0_SDIO1_DATA0,
+};
+
+/* GRF_GPIO3HL_IOMUX */
+enum {
+ GPIO3D7_SHIFT = 12,
+ GPIO3D7_MASK = 7,
+ GPIO3D7_GPIO = 0,
+ GPIO3D7_FLASH1_DATA7,
+ GPIO3D7_HOST_DOUT7,
+ GPIO3D7_MAC_RXD1,
+ GPIO3D7_SDIO1_INTN,
+
+ GPIO3D6_SHIFT = 8,
+ GPIO3D6_MASK = 7,
+ GPIO3D6_GPIO = 0,
+ GPIO3D6_FLASH1_DATA6,
+ GPIO3D6_HOST_DOUT6,
+ GPIO3D6_MAC_RXD0,
+ GPIO3D6_SDIO1_BKPWR,
+
+ GPIO3D5_SHIFT = 4,
+ GPIO3D5_MASK = 7,
+ GPIO3D5_GPIO = 0,
+ GPIO3D5_FLASH1_DATA5,
+ GPIO3D5_HOST_DOUT5,
+ GPIO3D5_MAC_TXD1,
+ GPIO3D5_SDIO1_WRPRT,
+
+ GPIO3D4_SHIFT = 0,
+ GPIO3D4_MASK = 7,
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_FLASH1_DATA4,
+ GPIO3D4_HOST_DOUT4,
+ GPIO3D4_MAC_TXD0,
+ GPIO3D4_SDIO1_DETECTN,
+};
+
+/* GRF_GPIO4AL_IOMUX */
+enum {
+ GPIO4A3_SHIFT = 12,
+ GPIO4A3_MASK = 7,
+ GPIO4A3_GPIO = 0,
+ GPIO4A3_FLASH1_ALE,
+ GPIO4A3_HOST_DOUT9,
+ GPIO4A3_MAC_CLK,
+ GPIO4A3_FLASH0_CSN6,
+
+ GPIO4A2_SHIFT = 8,
+ GPIO4A2_MASK = 7,
+ GPIO4A2_GPIO = 0,
+ GPIO4A2_FLASH1_RDN,
+ GPIO4A2_HOST_DOUT8,
+ GPIO4A2_MAC_RXER,
+ GPIO4A2_FLASH0_CSN5,
+
+ GPIO4A1_SHIFT = 4,
+ GPIO4A1_MASK = 7,
+ GPIO4A1_GPIO = 0,
+ GPIO4A1_FLASH1_WP,
+ GPIO4A1_HOST_CKOUTN,
+ GPIO4A1_MAC_TXDV,
+ GPIO4A1_FLASH0_CSN4,
+
+ GPIO4A0_SHIFT = 0,
+ GPIO4A0_MASK = 3,
+ GPIO4A0_GPIO = 0,
+ GPIO4A0_FLASH1_RDY,
+ GPIO4A0_HOST_CKOUTP,
+ GPIO4A0_MAC_MDC,
+};
+
+/* GRF_GPIO4AH_IOMUX */
+enum {
+ GPIO4A7_SHIFT = 12,
+ GPIO4A7_MASK = 7,
+ GPIO4A7_GPIO = 0,
+ GPIO4A7_FLASH1_CSN1,
+ GPIO4A7_HOST_DOUT13,
+ GPIO4A7_MAC_CSR,
+ GPIO4A7_SDIO1_CLKOUT,
+
+ GPIO4A6_SHIFT = 8,
+ GPIO4A6_MASK = 7,
+ GPIO4A6_GPIO = 0,
+ GPIO4A6_FLASH1_CSN0,
+ GPIO4A6_HOST_DOUT12,
+ GPIO4A6_MAC_RXCLK,
+ GPIO4A6_SDIO1_CMD,
+
+ GPIO4A5_SHIFT = 4,
+ GPIO4A5_MASK = 3,
+ GPIO4A5_GPIO = 0,
+ GPIO4A5_FLASH1_WRN,
+ GPIO4A5_HOST_DOUT11,
+ GPIO4A5_MAC_MDIO,
+
+ GPIO4A4_SHIFT = 0,
+ GPIO4A4_MASK = 7,
+ GPIO4A4_GPIO = 0,
+ GPIO4A4_FLASH1_CLE,
+ GPIO4A4_HOST_DOUT10,
+ GPIO4A4_MAC_TXEN,
+ GPIO4A4_FLASH0_CSN7,
+};
+
+/* GRF_GPIO4BL_IOMUX */
+enum {
+ GPIO4B1_SHIFT = 4,
+ GPIO4B1_MASK = 7,
+ GPIO4B1_GPIO = 0,
+ GPIO4B1_FLASH1_CSN2,
+ GPIO4B1_HOST_DOUT15,
+ GPIO4B1_MAC_TXCLK,
+ GPIO4B1_SDIO1_PWREN,
+
+ GPIO4B0_SHIFT = 0,
+ GPIO4B0_MASK = 7,
+ GPIO4B0_GPIO = 0,
+ GPIO4B0_FLASH1_DQS,
+ GPIO4B0_HOST_DOUT14,
+ GPIO4B0_MAC_COL,
+ GPIO4B0_FLASH1_CSN3,
+};
+
/* GRF_GPIO4C_IOMUX */
enum {
GPIO4C7_SHIFT = 14,
@@ -886,4 +1043,25 @@ enum GRF_SOC_CON8 {
RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
};
+/* GPIO Bias settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
+};
+
+#define GPIO_BIAS_MASK 0x3
+#define GPIO_BIAS_SHIFT(x) ((x) * 2)
+
+enum GPIO_PU_PD {
+ GPIO_PULL_NORMAL = 0,
+ GPIO_PULL_UP,
+ GPIO_PULL_DOWN,
+ GPIO_PULL_REPEAT,
+};
+
+#define GPIO_PULL_MASK 0x3
+#define GPIO_PULL_SHIFT(x) ((x) * 2)
+
#endif
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index de5e834..3c9ae97 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -402,6 +402,119 @@ static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
}
}
+static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ rk_clrsetreg(&grf->gpio3dl_iomux,
+ GPIO3D3_MASK << GPIO3D3_SHIFT |
+ GPIO3D2_MASK << GPIO3D2_SHIFT |
+ GPIO3D2_MASK << GPIO3D1_SHIFT |
+ GPIO3D0_MASK << GPIO3D0_SHIFT,
+ GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT |
+ GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT |
+ GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT |
+ GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT);
+
+ rk_clrsetreg(&grf->gpio3dh_iomux,
+ GPIO3D7_MASK << GPIO3D7_SHIFT |
+ GPIO3D6_MASK << GPIO3D6_SHIFT |
+ GPIO3D5_MASK << GPIO3D5_SHIFT |
+ GPIO3D4_MASK << GPIO3D4_SHIFT,
+ GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT |
+ GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT |
+ GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT |
+ GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT);
+
+ /* switch the Tx pins to 12ma drive-strength */
+ rk_clrsetreg(&grf->gpio1_e[2][3],
+ GPIO_BIAS_MASK |
+ (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) |
+ (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) |
+ (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)),
+ (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) |
+ (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) |
+ (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) |
+ (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5)));
+
+ /* Set normal pull for all GPIO3D pins */
+ rk_clrsetreg(&grf->gpio1_p[2][3],
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
+
+ rk_clrsetreg(&grf->gpio4al_iomux,
+ GPIO4A3_MASK << GPIO4A3_SHIFT |
+ GPIO4A1_MASK << GPIO4A1_SHIFT |
+ GPIO4A0_MASK << GPIO4A0_SHIFT,
+ GPIO4A3_MAC_CLK << GPIO4A3_SHIFT |
+ GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT |
+ GPIO4A0_MAC_MDC << GPIO4A0_SHIFT);
+
+ rk_clrsetreg(&grf->gpio4ah_iomux,
+ GPIO4A6_MASK << GPIO4A6_SHIFT |
+ GPIO4A5_MASK << GPIO4A5_SHIFT |
+ GPIO4A4_MASK << GPIO4A4_SHIFT,
+ GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT |
+ GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT |
+ GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT);
+
+ /* switch GPIO4A4 to 12ma drive-strength */
+ rk_clrsetreg(&grf->gpio1_e[3][0],
+ GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4),
+ GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4));
+
+ /* Set normal pull for all GPIO4A pins */
+ rk_clrsetreg(&grf->gpio1_p[3][0],
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
+
+ /* switch GPIO4B1 to 12ma drive-strength */
+ rk_clrsetreg(&grf->gpio1_e[3][1],
+ GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
+ GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
+
+ /* Set pull normal for GPIO4B1, pull up for GPIO4B0 */
+ rk_clrsetreg(&grf->gpio1_p[3][1],
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
+ (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
+ (GPIO_PULL_UP << GPIO_PULL_SHIFT(0)) |
+ (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
+
+ break;
+ default:
+ printf("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+
#ifndef CONFIG_SPL_BUILD
static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
{
@@ -465,6 +578,9 @@ static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_SDMMC1:
pinctrl_rk3288_sdmmc_config(priv->grf, func);
break;
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3288_gmac_config(priv->grf, func);
+ break;
default:
return -EINVAL;
}
@@ -484,6 +600,8 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
return -EINVAL;
switch (cell[1]) {
+ case 27:
+ return PERIPH_ID_GMAC;
case 44:
return PERIPH_ID_SPI0;
case 45:
generated by cgit v0.10.2 at 2024-11-17 02:07:31 (GMT)