diff options
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 66 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/cpu.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/gpio.h | 10 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 3 | ||||
| -rw-r--r-- | board/Marvell/db-88f6820-gp/MAINTAINERS | 6 | ||||
| -rw-r--r-- | drivers/block/ahci.c | 3 | ||||
| -rw-r--r-- | drivers/mmc/sdhci.c | 25 | ||||
| -rw-r--r-- | drivers/usb/host/ehci-marvell.c | 36 | ||||
| -rw-r--r-- | include/configs/db-88f6820-gp.h | 41 |
9 files changed, 184 insertions, 8 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0121db8..9bc9f00 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -6,10 +6,13 @@ #include <common.h> #include <netdev.h> +#include <ahci.h> +#include <linux/mbus.h> #include <asm/io.h> #include <asm/pl310.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include <sdhci.h> #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) @@ -245,6 +248,69 @@ int cpu_eth_init(bd_t *bis) } #endif +#ifdef CONFIG_MV_SDHCI +int board_mmc_init(bd_t *bis) +{ + mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, + SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); + + return 0; +} +#endif + +#ifdef CONFIG_SCSI_AHCI_PLAT +#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 +#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 + +#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) +#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) +#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) + +static void ahci_mvebu_mbus_config(void __iomem *base) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + for (i = 0; i < 4; i++) { + writel(0, base + AHCI_WINDOW_CTRL(i)); + writel(0, base + AHCI_WINDOW_BASE(i)); + writel(0, base + AHCI_WINDOW_SIZE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + writel((cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + AHCI_WINDOW_CTRL(i)); + writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); + writel(((cs->size - 1) & 0xffff0000), + base + AHCI_WINDOW_SIZE(i)); + } +} + +static void ahci_mvebu_regret_option(void __iomem *base) +{ + /* + * Enable the regret bit to allow the SATA unit to regret a + * request that didn't receive an acknowlegde and avoid a + * deadlock + */ + writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); + writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); +} + +void scsi_init(void) +{ + printf("MVEBU SATA INIT\n"); + ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); + ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); + ahci_init((void __iomem *)MVEBU_SATA0_BASE); +} +#endif + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 3b48460..4bdb633 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -114,6 +114,8 @@ void mvebu_sdram_size_adjust(enum memory_bank bank); int mvebu_mbus_probe(struct mbus_win windows[], int count); int mvebu_soc_family(void); +int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h new file mode 100644 index 0000000..09e3c50 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/gpio.h @@ -0,0 +1,10 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_MVEBU_GPIO_H +#define __MACH_MVEBU_GPIO_H + +/* Empty file - sdhci requires this. */ + +#endif diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0a9307c..1aaea67 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -49,8 +49,11 @@ #define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) #define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) +#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) +#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) +#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 diff --git a/board/Marvell/db-88f6820-gp/MAINTAINERS b/board/Marvell/db-88f6820-gp/MAINTAINERS new file mode 100644 index 0000000..f564940 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/MAINTAINERS @@ -0,0 +1,6 @@ +DB_88F6820_GP BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/Marvell/db-88f6820-gp/ +F: include/configs/db-88f6820-gp.h +F: configs/db-88f6820-gp_defconfig diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a57f674..0d19dd2 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -299,9 +299,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(1 << i, mmio + HOST_IRQ_STAT); - /* set irq mask (enables interrupts) */ - writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); debug("SATA port %d status: 0x%x\n", i, tmp); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 75556a3..d89e302 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -13,7 +13,11 @@ #include <mmc.h> #include <sdhci.h> +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) +void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; +#else void *aligned_buffer; +#endif static void sdhci_reset(struct sdhci_host *host, u8 mask) { @@ -133,8 +137,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; unsigned int time = 0, start_addr = 0; - unsigned int retry = 10000; int mmc_dev = mmc->block_dev.dev; + unsigned start = get_timer(0); /* Timeout unit - ms */ static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; @@ -205,6 +209,17 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, memcpy(aligned_buffer, data->src, trans_bytes); } +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) + /* + * Always use this bounce-buffer when + * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined + */ + is_aligned = 0; + start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); +#endif + sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); mode |= SDHCI_TRNS_DMA; #endif @@ -222,15 +237,15 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flush_cache(start_addr, trans_bytes); #endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); + start = get_timer(0); do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) break; - if (--retry == 0) - break; - } while ((stat & mask) != mask); + } while (((stat & mask) != mask) && + (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT)); - if (retry == 0) { + if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) { if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 1a5fd6e..03c489c 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <usb.h> #include "ehci.h" +#include <linux/mbus.h> #include <asm/arch/cpu.h> #if defined(CONFIG_KIRKWOOD) @@ -30,6 +31,40 @@ DECLARE_GLOBAL_DATA_PTR; /* * USB 2.0 Bridge Address Decoding registers setup */ +#ifdef CONFIG_ARMADA_XP + +#define MVUSB0_BASE MVEBU_USB20_BASE + +/* + * Once all the older Marvell SoC's (Orion, Kirkwood) are converted + * to the common mvebu archticture including the mbus setup, this + * will be the only function needed to configure the access windows + */ +static void usb_brg_adrdec_setup(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + for (i = 0; i < 4; i++) { + wrl(USB_WINDOW_CTRL(i), 0); + wrl(USB_WINDOW_BASE(i), 0); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + wrl(USB_WINDOW_CTRL(i), + ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1); + + /* Write base address to base register */ + wrl(USB_WINDOW_BASE(i), cs->base); + } +} +#else static void usb_brg_adrdec_setup(void) { int i; @@ -69,6 +104,7 @@ static void usb_brg_adrdec_setup(void) wrl(USB_WINDOW_BASE(i), base); } } +#endif /* * Create the appropriate control structures to manage diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 24dbf6b..a429107 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -29,12 +29,19 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC #define CONFIG_CMD_PING +#define CONFIG_CMD_SCSI #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT #define CONFIG_CMD_TIME +#define CONFIG_CMD_USB /* I2C */ #define CONFIG_SYS_I2C @@ -48,6 +55,40 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 #define CONFIG_SPI_FLASH_STMICRO +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_MV_SDHCI +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* Partition support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* USB/EHCI configuration */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_MARVELL +#define CONFIG_EHCI_IS_TDI + /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |