5 files changed, 91 insertions, 56 deletions
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index c21fb54..f7595ae 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -12,6 +12,8 @@
 #include <asm/types.h>
 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
 
+#include <asm/arch/hardware.h>
+
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct gptimer {
@@ -57,9 +59,6 @@ struct watchdog {
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/* GPMC BASE */
-#define GPMC_BASE		(OMAP44XX_GPMC_BASE)
-
 /* I2C base */
 #define I2C_BASE1		(OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h
new file mode 100644
index 0000000..f7011b4
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/hardware.h
@@ -0,0 +1,26 @@
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OMAP_HARDWARE_H
+#define __OMAP_HARDWARE_H
+
+#include <asm/arch/omap.h>
+
+/*
+ * Common hardware definitions
+ */
+
+/* BCH Error Location Module */
+#define ELM_BASE			0x48078000
+
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h
new file mode 100644
index 0000000..d2e708b
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mem.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *		Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M		0x0
+#define GPMC_SIZE_128M		0x8
+#define GPMC_SIZE_64M		0xC
+#define GPMC_SIZE_32M		0xE
+#define GPMC_SIZE_16M		0xF
+
+#define M_NAND_GPMC_CONFIG1	0x00000800
+#define M_NAND_GPMC_CONFIG2	0x001e1e00
+#define M_NAND_GPMC_CONFIG3	0x001e1e00
+#define M_NAND_GPMC_CONFIG4	0x16051807
+#define M_NAND_GPMC_CONFIG5	0x00151e1e
+#define M_NAND_GPMC_CONFIG6	0x16000f80
+#define M_NAND_GPMC_CONFIG7	0x00000008
+
+#define STNOR_GPMC_CONFIG1	0x00001200
+#define STNOR_GPMC_CONFIG2	0x00101000
+#define STNOR_GPMC_CONFIG3	0x00030301
+#define STNOR_GPMC_CONFIG4	0x10041004
+#define STNOR_GPMC_CONFIG5	0x000C1010
+#define STNOR_GPMC_CONFIG6	0x08070280
+#define STNOR_GPMC_CONFIG7	0x00000F48
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS		8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG		7
+
+#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index f66da0d..d43dc26 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -60,9 +60,6 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* GPMC */
-#define OMAP44XX_GPMC_BASE	0x50000000
-
 /*
  * Hardware Register Details
  */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 80172f3..83d858f 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -14,6 +14,7 @@
 #include <asm/omap_common.h>
 #include <linux/mtd/omap_gpmc.h>
 #include <asm/arch/mux_omap4.h>
+#include <asm/ti-common/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -53,54 +54,4 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
-
-static inline u32 running_from_sdram(void)
-{
-	u32 pc;
-	asm volatile ("mov %0, pc" : "=r" (pc));
-	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
-	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
-}
-
-static inline u8 uboot_loaded_by_spl(void)
-{
-	/*
-	 * u-boot can be running from sdram either because of configuration
-	 * Header or by SPL. If because of CH, then the romcode sets the
-	 * CHSETTINGS executed bit to true in the boot parameter structure that
-	 * it passes to the bootloader.This parameter is stored in the ch_flags
-	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
-	 * mandatory section if CH is present.
-	 */
-	if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
-		return 0;
-	else
-		return running_from_sdram();
-}
-/*
- * The basic hardware init of OMAP(s_init()) can happen in 4
- * different contexts:
- *  1. SPL running from SRAM
- *  2. U-Boot running from FLASH
- *  3. Non-XIP U-Boot loaded to SDRAM by SPL
- *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
- *     Configuration Header feature
- *
- * This function finds this context.
- * Defining as inline may help in compiling out unused functions in SPL
- */
-static inline u32 omap_hw_init_context(void)
-{
-#ifdef CONFIG_SPL_BUILD
-	return OMAP_INIT_CONTEXT_SPL;
-#else
-	if (uboot_loaded_by_spl())
-		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
-	else if (running_from_sdram())
-		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
-	else
-		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
-#endif
-}
-
 #endif