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-rw-r--r--arch/mips/dts/Makefile3
-rw-r--r--arch/mips/dts/brcm,bcm3380.dtsi154
-rw-r--r--arch/mips/dts/brcm,bcm63268.dtsi11
-rw-r--r--arch/mips/dts/brcm,bcm6328.dtsi11
-rw-r--r--arch/mips/dts/brcm,bcm6338.dtsi118
-rw-r--r--arch/mips/dts/brcm,bcm6348.dtsi127
-rw-r--r--arch/mips/dts/brcm,bcm6358.dtsi11
-rw-r--r--arch/mips/dts/comtrend,ct-5361.dts49
-rw-r--r--arch/mips/dts/netgear,cg3100d.dts96
-rw-r--r--arch/mips/dts/sagem,f@st1704.dts50
-rw-r--r--arch/mips/mach-bmips/Kconfig96
-rw-r--r--arch/mips/mach-bmips/include/ioremap.h4
12 files changed, 729 insertions, 1 deletions
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 4c02c48..a190485 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,8 +9,11 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
+dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
+dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/brcm,bcm3380.dtsi b/arch/mips/dts/brcm,bcm3380.dtsi
new file mode 100644
index 0000000..64245eb
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm3380.dtsi
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm3380-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm3380-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm3380";
+
+ cpus {
+ reg = <0x14e00000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk0: periph-clk@14e00004 {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x14e00004 0x4>;
+ #clock-cells = <1>;
+ };
+
+ periph_clk1: periph-clk@14e00008 {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x14e00008 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ memory-controller@12000000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x12000000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_rst0: reset-controller@14e0008c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x14e0008c 0x4>;
+ #reset-cells = <1>;
+ };
+
+ periph_rst1: reset-controller@14e00090 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x14e00090 0x4>;
+ #reset-cells = <1>;
+ };
+
+ pll_cntl: syscon@14e00094 {
+ compatible = "syscon";
+ reg = <0x14e00094 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ wdt: watchdog@14e000dc {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x14e000dc 0xc>;
+
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ gpio0: gpio-controller@14e00100 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@14e00104 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <3>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@14e00200 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x14e00200 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@14e00220 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x14e00220 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@14e00f00 {
+ compatible = "brcm,bcm6328-leds";
+ reg = <0x14e00f00 0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index b03763f..113a96b 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -84,6 +84,17 @@
#reset-cells = <1>;
};
+ wdt: watchdog@1000009c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x1000009c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
gpio1: gpio-controller@100000c0 {
compatible = "brcm,bcm6345-gpio";
reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index 3926885..a996075 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -78,6 +78,17 @@
mask = <0x1>;
};
+ wdt: watchdog@1000005c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x1000005c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
gpio: gpio-controller@10000084 {
compatible = "brcm,bcm6345-gpio";
reg = <0x10000084 0x4>, <0x1000008c 0x4>;
diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi
new file mode 100644
index 0000000..eb51a43
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6338.dtsi
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6338-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6338-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6338";
+
+ cpus {
+ reg = <0xfffe0000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk: periph-clk {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0xfffe0004 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pflash: nor@1fc00000 {
+ compatible = "cfi-flash";
+ reg = <0x1fc00000 0x400000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ pll_cntl: syscon@fffe0008 {
+ compatible = "syscon";
+ reg = <0xfffe0008 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ periph_rst: reset-controller@fffe0028 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0xfffe0028 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog@fffe021c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0xfffe021c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ uart0: serial@fffe0300 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0300 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ gpio: gpio-controller@fffe0404 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+
+ status = "disabled";
+ };
+
+ memory-controller@fffe3100 {
+ compatible = "brcm,bcm6338-mc";
+ reg = <0xfffe3100 0x38>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
new file mode 100644
index 0000000..711b643
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6348";
+
+ cpus {
+ reg = <0xfffe0000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk: periph-clk {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0xfffe0004 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pflash: nor@1fc00000 {
+ compatible = "cfi-flash";
+ reg = <0x1fc00000 0x2000000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ pll_cntl: syscon@fffe0008 {
+ compatible = "syscon";
+ reg = <0xfffe0008 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ periph_rst: reset-controller@fffe0028 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0xfffe0028 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog@fffe021c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0xfffe021c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ uart0: serial@fffe0300 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0300 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@fffe0400 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <5>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@fffe0404 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ memory-controller@fffe2300 {
+ compatible = "brcm,bcm6338-mc";
+ reg = <0xfffe2300 0x38>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index 0dad998..4f63cf8 100644
--- a/arch/mips/dts/brcm,bcm6358.dtsi
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -87,6 +87,17 @@
#reset-cells = <1>;
};
+ wdt: watchdog@fffe005c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0xfffe005c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
gpio1: gpio-controller@fffe0080 {
compatible = "brcm,bcm6345-gpio";
reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts
new file mode 100644
index 0000000..c909a52
--- /dev/null
+++ b/arch/mips/dts/comtrend,ct-5361.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6348.dtsi"
+
+/ {
+ model = "Comtrend CT-5361";
+ compatible = "comtrend,ct-5361", "brcm,bcm6348";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ power_green {
+ label = "CT-5361:green:power";
+ gpios = <&gpio0 0 1>;
+ };
+
+ alarm_red {
+ label = "CT-5361:red:alarm";
+ gpios = <&gpio0 2 1>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&pflash {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/dts/netgear,cg3100d.dts b/arch/mips/dts/netgear,cg3100d.dts
new file mode 100644
index 0000000..db1e2e7
--- /dev/null
+++ b/arch/mips/dts/netgear,cg3100d.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm3380.dtsi"
+
+/ {
+ model = "Netgear CG3100D";
+ compatible = "netgear,cg3100d", "brcm,bcm3380";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ wifi_green {
+ label = "CG3100D:green:wifi";
+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ wps_green {
+ label = "CG3100D:green:wps";
+ gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_red {
+ label = "CG3100D:red:power";
+ gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&leds {
+ status = "okay";
+
+ led@0 {
+ reg = <0>;
+ active-low;
+ label = "CG3100D:green:power";
+ };
+
+ led@1 {
+ reg = <1>;
+ active-low;
+ label = "CG3100D:green:downlink";
+ };
+
+ led@2 {
+ reg = <2>;
+ active-low;
+ label = "CG3100D:orange:downlink";
+ };
+
+ led@3 {
+ reg = <3>;
+ active-low;
+ label = "CG3100D:green:uplink";
+ };
+
+ led@4 {
+ reg = <4>;
+ active-low;
+ label = "CG3100D:orange:uplink";
+ };
+
+ led@6 {
+ reg = <6>;
+ active-low;
+ label = "CG3100D:green:inet";
+ };
+
+ led@7 {
+ reg = <7>;
+ active-low;
+ label = "CG3100D:green:stby";
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts
new file mode 100644
index 0000000..be15fe5
--- /dev/null
+++ b/arch/mips/dts/sagem,f@st1704.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6338.dtsi"
+
+/ {
+ model = "Sagem F@ST1704";
+ compatible = "sagem,f@st1704", "brcm,bcm6338";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ inet_green {
+ label = "F@ST1704:green:inet";
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ };
+
+ power_green {
+ label = "F@ST1704:green:power";
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ inet_red {
+ label = "F@ST1704:red:inet";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4a0c383..e3e1da3 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -2,13 +2,27 @@ menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
+ default "bcm3380" if SOC_BMIPS_BCM3380
default "bcm6328" if SOC_BMIPS_BCM6328
+ default "bcm6338" if SOC_BMIPS_BCM6338
+ default "bcm6348" if SOC_BMIPS_BCM6348
default "bcm6358" if SOC_BMIPS_BCM6358
default "bcm63268" if SOC_BMIPS_BCM63268
choice
prompt "Broadcom MIPS SoC select"
+config SOC_BMIPS_BCM3380
+ bool "BMIPS BCM3380 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_WATCHDOG
+ help
+ This supports BMIPS BCM3380 family.
+
config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family"
select SUPPORTS_BIG_ENDIAN
@@ -20,6 +34,28 @@ config SOC_BMIPS_BCM6328
help
This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
+config SOC_BMIPS_BCM6338
+ bool "BMIPS BCM6338 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_SYSCON
+ help
+ This supports BMIPS BCM6338 family.
+
+config SOC_BMIPS_BCM6348
+ bool "BMIPS BCM6348 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_WATCHDOG
+ help
+ This supports BMIPS BCM6348 family.
+
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
select SUPPORTS_BIG_ENDIAN
@@ -52,21 +88,78 @@ config BOARD_COMTREND_AR5387UN
bool "Comtrend AR-5387un"
depends on SOC_BMIPS_BCM6328
select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Comtrend AR-5387un boards have a BCM6328 SoC with 64 MB of RAM and 16
+ MB of flash (SPI).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
+ a BCM43225 (PCIe).
+
+config BOARD_COMTREND_CT5361
+ bool "Comtrend CT-5361"
+ depends on SOC_BMIPS_BCM6348
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Comtrend CT-5361 boards have a BCM6348 SoC with 16 MB of RAM and 4 MB
+ of flash (CFI).
+ Between its different peripherals there's a BCM5325 switch with 4
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
+ BCM4312 (miniPCI).
config BOARD_COMTREND_VR3032U
bool "Comtrend VR-3032u board"
depends on SOC_BMIPS_BCM63268
select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Comtrend VR-3032u boards have a BCM63268 SoC with 64 MB of RAM and
+ 128 MB of flash (NAND).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
+ and a BCM6362 (integrated).
config BOARD_HUAWEI_HG556A
bool "Huawei EchoLife HG556a"
depends on SOC_BMIPS_BCM6358
select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Huawei EchoLife HG556a boards have a BCM6358 SoC with 64 MB of RAM
+ and 16 MB of flash (CFI).
+ Between its different peripherals there's a BCM5325 switch with 4
+ ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
+ a RT3062F/AR9223 (PCI).
+
+config BOARD_NETGEAR_CG3100D
+ bool "Netgear CG3100D"
+ depends on SOC_BMIPS_BCM3380
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Netgear CG3100D boards have a BCM3380 SoC with 64 MB of RAM and 8 MB
+ of flash (SPI).
+ Between its different peripherals there's a BCM53115 switch with 4
+ ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
+ (miniPCIe).
+
+config BOARD_SAGEM_FAST1704
+ bool "Sagem F@ST1704"
+ depends on SOC_BMIPS_BCM6338
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Sagem F@ST1704 boards have a BCM6338 SoC with 16 MB of RAM and 4 MB
+ of flash (SPI).
+ Between its different peripherals there's a BCM5325 switch with 4
+ ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM4312
+ (miniPCI).
config BOARD_SFR_NB4_SER
bool "SFR NeufBox 4 (Sercomm)"
depends on SOC_BMIPS_BCM6358
select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ SFR NeufBox 4 (Sercomm) boards have a BCM6358 SoC with 32 MB of RAM
+ and 8 MB of flash (CFI).
+ Between its different peripherals there's a BCM5325 switch with 4
+ ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and
+ a BCM4318 (PCI).
endchoice
@@ -87,8 +180,11 @@ config BMIPS_SUPPORTS_BOOT_RAM
bool
source "board/comtrend/ar5387un/Kconfig"
+source "board/comtrend/ct5361/Kconfig"
source "board/comtrend/vr3032u/Kconfig"
source "board/huawei/hg556a/Kconfig"
+source "board/netgear/cg3100d/Kconfig"
+source "board/sagem/f@st1704/Kconfig"
source "board/sfr/nb4_ser/Kconfig"
endmenu
diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h
index 404690e..a57f55d 100644
--- a/arch/mips/mach-bmips/include/ioremap.h
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -18,7 +18,9 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
static inline int is_bmips_internal_registers(phys_addr_t offset)
{
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6338) || \
+ defined(CONFIG_SOC_BMIPS_BCM6348) || \
+ defined(CONFIG_SOC_BMIPS_BCM6358)
if (offset >= 0xfffe0000)
return 1;
#endif
generated by cgit v0.10.2 at 2024-07-12 19:11:39 (GMT)