diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 11 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 18 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/display2.h | 124 | ||||
-rw-r--r-- | arch/arm/mach-sunxi/Kconfig | 766 | ||||
-rw-r--r-- | arch/arm/mach-sunxi/board.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-sunxi/clock_sun6i.c | 7 |
7 files changed, 933 insertions, 3 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 054ccac..b2d6e80 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -649,6 +649,14 @@ config ARCH_SUNXI select USB_STORAGE if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS select USE_TINY_PRINTF + imply PRE_CONSOLE_BUFFER + imply SPL_GPIO_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT if GENERIC_MMC + imply SPL_POWER_SUPPORT + imply SPL_SERIAL_SUPPORT config TARGET_TS4600 bool "Support TS4600" @@ -1049,6 +1057,8 @@ source "arch/arm/mach-sti/Kconfig" source "arch/arm/mach-stm32/Kconfig" +source "arch/arm/mach-sunxi/Kconfig" + source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-uniphier/Kconfig" @@ -1121,7 +1131,6 @@ source "board/spear/spear320/Kconfig" source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" -source "board/sunxi/Kconfig" source "board/syteco/zmx25/Kconfig" source "board/tcl/sl50/Kconfig" source "board/birdland/bav335x/Kconfig" diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index a44ea77..faa1479 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -25,7 +25,7 @@ struct sunxi_ccm_reg { u32 pll6_cfg; /* 0x28 pll6 control */ u32 reserved5; u32 pll7_cfg; /* 0x30 pll7 control */ - u32 reserved6; + u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */ u32 pll8_cfg; /* 0x38 pll8 control */ u32 reserved7; u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ @@ -58,7 +58,8 @@ struct sunxi_ccm_reg { u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ u32 reserved10[2]; u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ - u32 reserved11[2]; + u32 reserved11; + u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */ u32 usb_clk_cfg; /* 0xcc USB clock control */ u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ u32 reserved12[7]; @@ -224,6 +225,8 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) #define CCM_PLL6_CTRL_LOCK (1 << 28) +#define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */ + #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) #define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) @@ -280,7 +283,12 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif +#ifndef CONFIG_MACH_SUN8I_R40 #define AHB_GATE_OFFSET_USB0 24 +#else +#define AHB_GATE_OFFSET_USB0 25 +#define AHB_GATE_OFFSET_SATA 24 +#endif #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_NAND0 13 @@ -315,6 +323,9 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_PLL6 (0x1 << 24) #define CCM_MMC_CTRL_ENABLE (0x1 << 31) +#define CCM_SATA_CTRL_ENABLE (0x1 << 31) +#define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24) + #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) @@ -417,6 +428,9 @@ struct sunxi_ccm_reg { #define CCM_PLL11_PATTERN 0xf5860000 /* ahb_reset0 offsets */ +#ifdef CONFIG_MACH_SUN8I_R40 +#define AHB_RESET_OFFSET_SATA 24 +#endif #define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 #define AHB_RESET_OFFSET_MMC3 11 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 88c3f13..6aa5e91 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -18,6 +18,8 @@ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ +#define SUNXI_DE2_BASE 0x01000000 + #ifdef CONFIG_MACH_SUN8I_A83T #define SUNXI_CPUCFG_BASE 0x01700000 #endif @@ -46,7 +48,9 @@ #define SUNXI_USB1_BASE 0x01c14000 #endif #define SUNXI_SS_BASE 0x01c15000 +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) #define SUNXI_HDMI_BASE 0x01c16000 +#endif #define SUNXI_SPI2_BASE 0x01c17000 #define SUNXI_SATA_BASE 0x01c18000 #ifdef CONFIG_SUNXI_GEN_SUN4I @@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define SUNXI_HDMI_BASE 0x01ee0000 +#endif + #define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h new file mode 100644 index 0000000..b5875f9 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/display2.h @@ -0,0 +1,124 @@ +/* + * Sunxi platform display controller register and constant defines + * + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * Based on out of tree Linux DRM driver defines: + * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> + * Copyright (c) 2016 Allwinnertech Co., Ltd. +* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DISPLAY2_H +#define _SUNXI_DISPLAY2_H + +/* internal clock settings */ +struct de_clk { + u32 gate_cfg; + u32 bus_cfg; + u32 rst_cfg; + u32 div_cfg; + u32 sel_cfg; +}; + +/* global control */ +struct de_glb { + u32 ctl; + u32 status; + u32 dbuff; + u32 size; +}; + +/* alpha blending */ +struct de_bld { + u32 fcolor_ctl; + struct { + u32 fcolor; + u32 insize; + u32 offset; + u32 dum; + } attr[4]; + u32 dum0[15]; + u32 route; + u32 premultiply; + u32 bkcolor; + u32 output_size; + u32 bld_mode[4]; + u32 dum1[4]; + u32 ck_ctl; + u32 ck_cfg; + u32 dum2[2]; + u32 ck_max[4]; + u32 dum3[4]; + u32 ck_min[4]; + u32 dum4[3]; + u32 out_ctl; +}; + +/* VI channel */ +struct de_vi { + struct { + u32 attr; + u32 size; + u32 coord; + u32 pitch[3]; + u32 top_laddr[3]; + u32 bot_laddr[3]; + } cfg[4]; + u32 fcolor[4]; + u32 top_haddr[3]; + u32 bot_haddr[3]; + u32 ovl_size[2]; + u32 hori[2]; + u32 vert[2]; +}; + +struct de_ui { + struct { + u32 attr; + u32 size; + u32 coord; + u32 pitch; + u32 top_laddr; + u32 bot_laddr; + u32 fcolor; + u32 dum; + } cfg[4]; + u32 top_haddr; + u32 bot_haddr; + u32 ovl_size; +}; + +/* + * DE register constants. + */ +#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) +#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) + +#define SUNXI_DE2_MUX_GLB_REGS 0x00000 +#define SUNXI_DE2_MUX_BLD_REGS 0x01000 +#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 +#define SUNXI_DE2_MUX_CHAN_SZ 0x1000 +#define SUNXI_DE2_MUX_VSU_REGS 0x20000 +#define SUNXI_DE2_MUX_GSU1_REGS 0x30000 +#define SUNXI_DE2_MUX_GSU2_REGS 0x40000 +#define SUNXI_DE2_MUX_GSU3_REGS 0x50000 +#define SUNXI_DE2_MUX_FCE_REGS 0xa0000 +#define SUNXI_DE2_MUX_BWS_REGS 0xa2000 +#define SUNXI_DE2_MUX_LTI_REGS 0xa4000 +#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 +#define SUNXI_DE2_MUX_ASE_REGS 0xa8000 +#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 +#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 + +#define SUNXI_DE2_FORMAT_XRGB_8888 4 +#define SUNXI_DE2_FORMAT_RGB_565 10 + +#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) +#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) +#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) + +#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) + +#endif /* _SUNXI_DISPLAY2_H */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig new file mode 100644 index 0000000..8d9900e --- /dev/null +++ b/arch/arm/mach-sunxi/Kconfig @@ -0,0 +1,766 @@ +if ARCH_SUNXI + +config IDENT_STRING + default " Allwinner Technology" + +config SUNXI_HIGH_SRAM + bool + default n + ---help--- + Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, + with the first SRAM region being located at address 0. + Some newer SoCs map the boot ROM at address 0 instead and move the + SRAM to 64KB, just behind the mask ROM. + Chips using the latter setup are supposed to select this option to + adjust the addresses accordingly. + +# Note only one of these may be selected at a time! But hidden choices are +# not supported by Kconfig +config SUNXI_GEN_SUN4I + bool + ---help--- + Select this for sunxi SoCs which have resets and clocks set up + as the original A10 (mach-sun4i). + +config SUNXI_GEN_SUN6I + bool + ---help--- + Select this for sunxi SoCs which have sun6i like periphery, like + separate ahb reset control registers, custom pmic bus, new style + watchdog, etc. + + +config MACH_SUNXI_H3_H5 + bool + select DM_I2C + select SUNXI_DE2 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + +choice + prompt "Sunxi SoC Variant" + optional + +config MACH_SUN4I + bool "sun4i (Allwinner A10)" + select CPU_V7 + select ARM_CORTEX_CPU_IS_UP + select SUNXI_GEN_SUN4I + select SUPPORT_SPL + +config MACH_SUN5I + bool "sun5i (Allwinner A13)" + select CPU_V7 + select ARM_CORTEX_CPU_IS_UP + select SUNXI_GEN_SUN4I + select SUPPORT_SPL + +config MACH_SUN6I + bool "sun6i (Allwinner A31)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN7I + bool "sun7i (Allwinner A20)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN4I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN8I_A23 + bool "sun8i (Allwinner A23)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN8I_A33 + bool "sun8i (Allwinner A33)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN8I_A83T + bool "sun8i (Allwinner A83T)" + select CPU_V7 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + +config MACH_SUN8I_H3 + bool "sun8i (Allwinner H3)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select MACH_SUNXI_H3_H5 + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN8I_R40 + bool "sun8i (Allwinner R40)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + +config MACH_SUN8I_V3S + bool "sun8i (Allwinner V3s)" + select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN6I + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN9I + bool "sun9i (Allwinner A80)" + select CPU_V7 + select SUNXI_HIGH_SRAM + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + +config MACH_SUN50I + bool "sun50i (Allwinner A64)" + select ARM64 + select DM_I2C + select SUNXI_DE2 + select SUNXI_GEN_SUN6I + select SUNXI_HIGH_SRAM + select SUPPORT_SPL + +config MACH_SUN50I_H5 + bool "sun50i (Allwinner H5)" + select ARM64 + select MACH_SUNXI_H3_H5 + select SUNXI_HIGH_SRAM + +endchoice + +# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" +config MACH_SUN8I + bool + default y if MACH_SUN8I_A23 + default y if MACH_SUN8I_A33 + default y if MACH_SUN8I_A83T + default y if MACH_SUNXI_H3_H5 + default y if MACH_SUN8I_R40 + default y if MACH_SUN8I_V3S + +config RESERVE_ALLWINNER_BOOT0_HEADER + bool "reserve space for Allwinner boot0 header" + select ENABLE_ARM_SOC_BOOT0_HOOK + ---help--- + Prepend a 1536 byte (empty) header to the U-Boot image file, to be + filled with magic values post build. The Allwinner provided boot0 + blob relies on this information to load and execute U-Boot. + Only needed on 64-bit Allwinner boards so far when using boot0. + +config ARM_BOOT_HOOK_RMR + bool + depends on ARM64 + default y + select ENABLE_ARM_SOC_BOOT0_HOOK + ---help--- + Insert some ARM32 code at the very beginning of the U-Boot binary + which uses an RMR register write to bring the core into AArch64 mode. + The very first instruction acts as a switch, since it's carefully + chosen to be a NOP in one mode and a branch in the other, so the + code would only be executed if not already in AArch64. + This allows both the SPL and the U-Boot proper to be entered in + either mode and switch to AArch64 if needed. + +config DRAM_TYPE + int "sunxi dram type" + depends on MACH_SUN8I_A83T + default 3 + ---help--- + Set the dram type, 3: DDR3, 7: LPDDR3 + +config DRAM_CLK + int "sunxi dram clock speed" + default 792 if MACH_SUN9I + default 648 if MACH_SUN8I_R40 + default 312 if MACH_SUN6I || MACH_SUN8I + default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default 672 if MACH_SUN50I + ---help--- + Set the dram clock speed, valid range 240 - 480 (prior to sun9i), + must be a multiple of 24. For the sun9i (A80), the tested values + (for DDR3-1600) are 312 to 792. + +if MACH_SUN5I || MACH_SUN7I +config DRAM_MBUS_CLK + int "sunxi mbus clock speed" + default 300 + ---help--- + Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. + +endif + +config DRAM_ZQ + int "sunxi dram zq value" + default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I + default 127 if MACH_SUN7I + default 3881979 if MACH_SUN8I_R40 + default 4145117 if MACH_SUN9I + default 3881915 if MACH_SUN50I + ---help--- + Set the dram zq value. + +config DRAM_ODT_EN + bool "sunxi dram odt enable" + default n if !MACH_SUN8I_A23 + default y if MACH_SUN8I_A23 + default y if MACH_SUN8I_R40 + default y if MACH_SUN50I + ---help--- + Select this to enable dram odt (on die termination). + +if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I +config DRAM_EMR1 + int "sunxi dram emr1 value" + default 0 if MACH_SUN4I + default 4 if MACH_SUN5I || MACH_SUN7I + ---help--- + Set the dram controller emr1 value. + +config DRAM_TPR3 + hex "sunxi dram tpr3 value" + default 0 + ---help--- + Set the dram controller tpr3 parameter. This parameter configures + the delay on the command lane and also phase shifts, which are + applied for sampling incoming read data. The default value 0 + means that no phase/delay adjustments are necessary. Properly + configuring this parameter increases reliability at high DRAM + clock speeds. + +config DRAM_DQS_GATING_DELAY + hex "sunxi dram dqs_gating_delay value" + default 0 + ---help--- + Set the dram controller dqs_gating_delay parmeter. Each byte + encodes the DQS gating delay for each byte lane. The delay + granularity is 1/4 cycle. For example, the value 0x05060606 + means that the delay is 5 quarter-cycles for one lane (1.25 + cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. + The default value 0 means autodetection. The results of hardware + autodetection are not very reliable and depend on the chip + temperature (sometimes producing different results on cold start + and warm reboot). But the accuracy of hardware autodetection + is usually good enough, unless running at really high DRAM + clocks speeds (up to 600MHz). If unsure, keep as 0. + +choice + prompt "sunxi dram timings" + default DRAM_TIMINGS_VENDOR_MAGIC + ---help--- + Select the timings of the DDR3 chips. + +config DRAM_TIMINGS_VENDOR_MAGIC + bool "Magic vendor timings from Android" + ---help--- + The same DRAM timings as in the Allwinner boot0 bootloader. + +config DRAM_TIMINGS_DDR3_1066F_1333H + bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" + ---help--- + Use the timings of the standard JEDEC DDR3-1066F speed bin for + DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin + for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips + used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 + or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm + that down binning to DDR3-1066F is supported (because DDR3-1066F + uses a bit faster timings than DDR3-1333H). + +config DRAM_TIMINGS_DDR3_800E_1066G_1333J + bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" + ---help--- + Use the timings of the slowest possible JEDEC speed bin for the + selected DRAM_CLK. Depending on the DRAM_CLK value, it may be + DDR3-800E, DDR3-1066G or DDR3-1333J. + +endchoice + +endif + +if MACH_SUN8I_A23 +config DRAM_ODT_CORRECTION + int "sunxi dram odt correction value" + default 0 + ---help--- + Set the dram odt correction value (range -255 - 255). In allwinner + fex files, this option is found in bits 8-15 of the u32 odt_en variable + in the [dram] section. When bit 31 of the odt_en variable is set + then the correction is negative. Usually the value for this is 0. +endif + +config SYS_CLK_FREQ + default 1008000000 if MACH_SUN4I + default 1008000000 if MACH_SUN5I + default 1008000000 if MACH_SUN6I + default 912000000 if MACH_SUN7I + default 1008000000 if MACH_SUN8I + default 1008000000 if MACH_SUN9I + default 816000000 if MACH_SUN50I + +config SYS_CONFIG_NAME + default "sun4i" if MACH_SUN4I + default "sun5i" if MACH_SUN5I + default "sun6i" if MACH_SUN6I + default "sun7i" if MACH_SUN7I + default "sun8i" if MACH_SUN8I + default "sun9i" if MACH_SUN9I + default "sun50i" if MACH_SUN50I + +config SYS_BOARD + default "sunxi" + +config SYS_SOC + default "sunxi" + +config UART0_PORT_F + bool "UART0 on MicroSD breakout board" + default n + ---help--- + Repurpose the SD card slot for getting access to the UART0 serial + console. Primarily useful only for low level u-boot debugging on + tablets, where normal UART0 is difficult to access and requires + device disassembly and/or soldering. As the SD card can't be used + at the same time, the system can be only booted in the FEL mode. + Only enable this if you really know what you are doing. + +config OLD_SUNXI_KERNEL_COMPAT + bool "Enable workarounds for booting old kernels" + default n + ---help--- + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. + +config MACPWR + string "MAC power pin" + default "" + help + Set the pin used to power the MAC. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config MMC0_CD_PIN + string "Card detect pin for mmc0" + default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I + default "" + ---help--- + Set the card detect pin for mmc0, leave empty to not use cd. This + takes a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config MMC1_CD_PIN + string "Card detect pin for mmc1" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC2_CD_PIN + string "Card detect pin for mmc2" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC3_CD_PIN + string "Card detect pin for mmc3" + default "" + ---help--- + See MMC0_CD_PIN help text. + +config MMC1_PINS + string "Pins for mmc1" + default "" + ---help--- + Set the pins used for mmc1, when applicable. This takes a string in the + format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. + +config MMC2_PINS + string "Pins for mmc2" + default "" + ---help--- + See MMC1_PINS help text. + +config MMC3_PINS + string "Pins for mmc3" + default "" + ---help--- + See MMC1_PINS help text. + +config MMC_SUNXI_SLOT_EXTRA + int "mmc extra slot number" + default -1 + ---help--- + sunxi builds always enable mmc0, some boards also have a second sdcard + slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable + support for this. + +config INITIAL_USB_SCAN_DELAY + int "delay initial usb scan by x ms to allow builtin devices to init" + default 0 + ---help--- + Some boards have on board usb devices which need longer than the + USB spec's 1 second to connect from board powerup. Set this config + option to a non 0 value to add an extra delay before the first usb + bus scan. + +config USB0_VBUS_PIN + string "Vbus enable pin for usb0 (otg)" + default "" + ---help--- + Set the Vbus enable pin for usb0 (otg). This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config USB0_VBUS_DET + string "Vbus detect pin for usb0 (otg)" + default "" + ---help--- + Set the Vbus detect pin for usb0 (otg). This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config USB0_ID_DET + string "ID detect pin for usb0 (otg)" + default "" + ---help--- + Set the ID detect pin for usb0 (otg). This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config USB1_VBUS_PIN + string "Vbus enable pin for usb1 (ehci0)" + default "PH6" if MACH_SUN4I || MACH_SUN7I + default "PH27" if MACH_SUN6I + ---help--- + Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes + a string in the format understood by sunxi_name_to_gpio, e.g. + PH1 for pin 1 of port H. + +config USB2_VBUS_PIN + string "Vbus enable pin for usb2 (ehci1)" + default "PH3" if MACH_SUN4I || MACH_SUN7I + default "PH24" if MACH_SUN6I + ---help--- + See USB1_VBUS_PIN help text. + +config USB3_VBUS_PIN + string "Vbus enable pin for usb3 (ehci2)" + default "" + ---help--- + See USB1_VBUS_PIN help text. + +config I2C0_ENABLE + bool "Enable I2C/TWI controller 0" + default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 + default n if MACH_SUN6I || MACH_SUN8I + select CMD_I2C + ---help--- + This allows enabling I2C/TWI controller 0 by muxing its pins, enabling + its clock and setting up the bus. This is especially useful on devices + with slaves connected to the bus or with pins exposed through e.g. an + expansion port/header. + +config I2C1_ENABLE + bool "Enable I2C/TWI controller 1" + default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. + +config I2C2_ENABLE + bool "Enable I2C/TWI controller 2" + default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. + +if MACH_SUN6I || MACH_SUN7I +config I2C3_ENABLE + bool "Enable I2C/TWI controller 3" + default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. +endif + +if SUNXI_GEN_SUN6I +config R_I2C_ENABLE + bool "Enable the PRCM I2C/TWI controller" + # This is used for the pmic on H3 + default y if SY8106A_POWER + select CMD_I2C + ---help--- + Set this to y to enable the I2C controller which is part of the PRCM. +endif + +if MACH_SUN7I +config I2C4_ENABLE + bool "Enable I2C/TWI controller 4" + default n + select CMD_I2C + ---help--- + See I2C0_ENABLE help text. +endif + +config AXP_GPIO + bool "Enable support for gpio-s on axp PMICs" + default n + ---help--- + Say Y here to enable support for the gpio pins of the axp PMIC ICs. + +config VIDEO + bool "Enable graphical uboot console on HDMI, LCD or VGA" + depends on !MACH_SUN8I_A83T + depends on !MACH_SUNXI_H3_H5 + depends on !MACH_SUN8I_R40 + depends on !MACH_SUN8I_V3S + depends on !MACH_SUN9I + depends on !MACH_SUN50I + default y + ---help--- + Say Y here to add support for using a cfb console on the HDMI, LCD + or VGA output found on most sunxi devices. See doc/README.video for + info on how to select the video output and mode. + +config VIDEO_HDMI + bool "HDMI output support" + depends on VIDEO && !MACH_SUN8I + default y + ---help--- + Say Y here to add support for outputting video over HDMI. + +config VIDEO_VGA + bool "VGA output support" + depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) + default n + ---help--- + Say Y here to add support for outputting video over VGA. + +config VIDEO_VGA_VIA_LCD + bool "VGA via LCD controller support" + depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) + default n + ---help--- + Say Y here to add support for external DACs connected to the parallel + LCD interface driving a VGA connector, such as found on the + Olimex A13 boards. + +config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH + bool "Force sync active high for VGA via LCD controller support" + depends on VIDEO_VGA_VIA_LCD + default n + ---help--- + Say Y here if you've a board which uses opendrain drivers for the vga + hsync and vsync signals. Opendrain drivers cannot generate steep enough + positive edges for a stable video output, so on boards with opendrain + drivers the sync signals must always be active high. + +config VIDEO_VGA_EXTERNAL_DAC_EN + string "LCD panel power enable pin" + depends on VIDEO_VGA_VIA_LCD + default "" + ---help--- + Set the enable pin for the external VGA DAC. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_COMPOSITE + bool "Composite video output support" + depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) + default n + ---help--- + Say Y here to add support for outputting composite video. + +config VIDEO_LCD_MODE + string "LCD panel timing details" + depends on VIDEO + default "" + ---help--- + LCD panel timing details string, leave empty if there is no LCD panel. + This is in drivers/video/videomodes.c: video_get_params() format, e.g. + x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 + Also see: http://linux-sunxi.org/LCD + +config VIDEO_LCD_DCLK_PHASE + int "LCD panel display clock phase" + depends on VIDEO + default 1 + ---help--- + Select LCD panel display clock phase shift, range 0-3. + +config VIDEO_LCD_POWER + string "LCD panel power enable pin" + depends on VIDEO + default "" + ---help--- + Set the power enable pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_RESET + string "LCD panel reset pin" + depends on VIDEO + default "" + ---help--- + Set the reset pin for the LCD panel. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_BL_EN + string "LCD panel backlight enable pin" + depends on VIDEO + default "" + ---help--- + Set the backlight enable pin for the LCD panel. This takes a string in the + the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of + port H. + +config VIDEO_LCD_BL_PWM + string "LCD panel backlight pwm pin" + depends on VIDEO + default "" + ---help--- + Set the backlight pwm pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_BL_PWM_ACTIVE_LOW + bool "LCD panel backlight pwm is inverted" + depends on VIDEO + default y + ---help--- + Set this if the backlight pwm output is active low. + +config VIDEO_LCD_PANEL_I2C + bool "LCD panel needs to be configured via i2c" + depends on VIDEO + default n + select CMD_I2C + ---help--- + Say y here if the LCD panel needs to be configured via i2c. This + will add a bitbang i2c controller using gpios to talk to the LCD. + +config VIDEO_LCD_PANEL_I2C_SDA + string "LCD panel i2c interface SDA pin" + depends on VIDEO_LCD_PANEL_I2C + default "PG12" + ---help--- + Set the SDA pin for the LCD i2c interface. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_PANEL_I2C_SCL + string "LCD panel i2c interface SCL pin" + depends on VIDEO_LCD_PANEL_I2C + default "PG10" + ---help--- + Set the SCL pin for the LCD i2c interface. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + + +# Note only one of these may be selected at a time! But hidden choices are +# not supported by Kconfig +config VIDEO_LCD_IF_PARALLEL + bool + +config VIDEO_LCD_IF_LVDS + bool + +config SUNXI_DE2 + bool + default n + +config VIDEO_DE2 + bool "Display Engine 2 video driver" + depends on SUNXI_DE2 + select DM_VIDEO + select DISPLAY + default y + ---help--- + Say y here if you want to build DE2 video driver which is present on + newer SoCs. Currently only HDMI output is supported. + + +choice + prompt "LCD panel support" + depends on VIDEO + ---help--- + Select which type of LCD panel to support. + +config VIDEO_LCD_PANEL_PARALLEL + bool "Generic parallel interface LCD panel" + select VIDEO_LCD_IF_PARALLEL + +config VIDEO_LCD_PANEL_LVDS + bool "Generic lvds interface LCD panel" + select VIDEO_LCD_IF_LVDS + +config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 + bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" + select VIDEO_LCD_SSD2828 + select VIDEO_LCD_IF_PARALLEL + ---help--- + 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + +config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 + bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" + select VIDEO_LCD_ANX9804 + select VIDEO_LCD_IF_PARALLEL + select VIDEO_LCD_PANEL_I2C + ---help--- + Select this for eDP LCD panels with 4 lanes running at 1.62G, + connected via an ANX9804 bridge chip. + +config VIDEO_LCD_PANEL_HITACHI_TX18D42VM + bool "Hitachi tx18d42vm LCD panel" + select VIDEO_LCD_HITACHI_TX18D42VM + select VIDEO_LCD_IF_LVDS + ---help--- + 7.85" 1024x768 Hitachi tx18d42vm LCD panel support + +config VIDEO_LCD_TL059WV5C0 + bool "tl059wv5c0 LCD panel" + select VIDEO_LCD_PANEL_I2C + select VIDEO_LCD_IF_PARALLEL + ---help--- + 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and + Aigo M60/M608/M606 tablets. + +endchoice + +config SATAPWR + string "SATA power pin" + default "" + help + Set the pins used to power the SATA. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of + port H. + +config GMAC_TX_DELAY + int "GMAC Transmit Clock Delay Chain" + default 0 + ---help--- + Set the GMAC Transmit Clock Delay Chain value. + +config SPL_STACK_R_ADDR + default 0x4fe00000 if MACH_SUN4I + default 0x4fe00000 if MACH_SUN5I + default 0x4fe00000 if MACH_SUN6I + default 0x4fe00000 if MACH_SUN7I + default 0x4fe00000 if MACH_SUN8I + default 0x2fe00000 if MACH_SUN9I + default 0x4fe00000 if MACH_SUN50I + +endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 4507279..65b1ebd 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -204,7 +204,9 @@ void s_init(void) clock_init(); timer_init(); gpio_init(); +#ifndef CONFIG_DM_I2C i2c_init_board(); +#endif eth_init_board(); } diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 631bc6e..ec5b026 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -51,6 +51,13 @@ void clock_init_safe(void) writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); if (IS_ENABLED(CONFIG_MACH_SUN6I)) writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); + +#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI) + setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); + setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); + setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); +#endif } #endif |