diff options
Diffstat (limited to 'board/freescale/mpc8360emds/mpc8360emds.c')
| -rw-r--r-- | board/freescale/mpc8360emds/mpc8360emds.c | 69 |
1 files changed, 52 insertions, 17 deletions
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 51d8035..be76774 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006,2010 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -24,6 +24,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <asm/fsl_enet.h> +#include <asm/mmu.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -139,9 +140,20 @@ int board_early_init_f(void) int board_early_init_r(void) { + gd_t *gd; #ifdef CONFIG_PQ_MDS_PIB pib_init(); #endif + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + } + return 0; } @@ -216,19 +228,15 @@ phys_size_t initdram(int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; + u32 ddr_size_log2 = __ilog2(ddr_size); + u32 half_ddr_size = ddr_size >> 1; + + im->sysconf.ddrlaw[0].bar = + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif @@ -246,11 +254,25 @@ int fixed_sdram(void) im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else - im->ddr.csbnds[0].csbnds = 0x00000007; - im->ddr.csbnds[1].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; - im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.csbnds[1].csbnds = + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> + CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; + + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0; im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; @@ -292,6 +314,19 @@ static int sdram_init(unsigned int base) if (rem) base = base - rem + sdram_size; + /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, reuse BAT5 for PCI MEM space + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + /* Setup the BAT6 for SDRAM */ + write_bat(DBAT6, batu, batl); + write_bat(IBAT6, batu, batl); + } + sdram_addr = (uint *)base; /* * Setup SDRAM Base and Option Registers |