diff options
Diffstat (limited to 'board/scalys/simc-t10xx/ddr_QT1040-4GB.c')
| -rwxr-xr-x | board/scalys/simc-t10xx/ddr_QT1040-4GB.c | 187 |
1 files changed, 187 insertions, 0 deletions
diff --git a/board/scalys/simc-t10xx/ddr_QT1040-4GB.c b/board/scalys/simc-t10xx/ddr_QT1040-4GB.c new file mode 100755 index 0000000..27f2f46 --- /dev/null +++ b/board/scalys/simc-t10xx/ddr_QT1040-4GB.c @@ -0,0 +1,187 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_DDR4 +#error CONFIG_SYS_FSL_DDR4 not defined +#endif + +/* Values for QT1040 4GB DDR4 */ +/* ST9D4512M72SBG0 */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 0x100000000ULL, + .capacity = 0x100000000ULL, + .device_width = 64, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 16, + .n_col_addr = 10, + + .bank_addr_bits = 0, + .bank_group_bits = 1, + .edc_config = EDC_ECC, + .burst_lengths_bitmask = 0x0c, + /* 1600 MT/s*/ + .tckmin_x_ps = 1250, + .tckmax_ps = 1499, + .caslat_x = 0x1400, + .taa_ps = 15000, + .trcd_ps = 15000, + .trp_ps = 15000, + .tras_ps = 35000, + .trc_ps = 50000, + .trfc1_ps = 350000, + .trfc2_ps = 260000, + .trfc4_ps = 160000, + .trrds_ps = 6000, + .trrdl_ps = 7500, + .tccdl_ps = 6250, + .refresh_rate_ps = 3900000, + .tfaw_ps = 50000, + + /* DQ mapping for Qormino V2 S3/4 (rev-C/D) */ + .dq_mapping[ 0] = 0x15, + .dq_mapping[ 1] = 0x2B, + .dq_mapping[ 2] = 0x0C, + .dq_mapping[ 3] = 0x27, + .dq_mapping[ 4] = 0x0F, + .dq_mapping[ 5] = 0x37, + .dq_mapping[ 6] = 0x18, + .dq_mapping[ 7] = 0x25, + .dq_mapping[ 8] = 0x2A, + .dq_mapping[ 9] = 0x16, + .dq_mapping[10] = 0x2E, + .dq_mapping[11] = 0x06, + .dq_mapping[12] = 0x2A, + .dq_mapping[13] = 0x0D, + .dq_mapping[14] = 0x05, + .dq_mapping[15] = 0x27, + .dq_mapping[16] = 0x2B, + .dq_mapping[17] = 0x18, + .dq_mapping_ors = 0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + + if (ctrl_num != 0) { + printf("Only 1 memory controller supported, but %i requested\n", + ctrl_num); + return; + } + + if (pdimm == NULL ) { + printf("Error, no valid dimm parameter supplied\n"); + return; + } + + if (!pdimm->n_ranks) { + printf("No ranks in dimm parameters. Configuration error?\n"); + return; + } + + /* DDR speed is fixed in the RCW */ + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_wr_cfg = 4; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 4; + } + + /* half strength */ + popts->half_strength_driver_enable = 1; + + popts->wrlvl_override = 1; + popts->wrlvl_en = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 5; + popts->wrlvl_ctl_2 = 0x05050505; + popts->wrlvl_ctl_3 = 0x05050505; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_40ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_40ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ + + /* rtt and rtt_wr override */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* Clock is launched xxx applied cycle after address/command */ + popts->clk_adjust = 9; + + /* Optimized cpo */ + popts->cpo_sample = 0x3d; +} + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Soldered-down DDR4"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(pdimm->mpart) - 1); + } + + return 0; +} + +int dram_init(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + debug ("\n**** SPL_BUILD - DDR %i bits - %i MHz - (stack @ %p - fct @ %p) ****\n\n", + ddr_raw_timing.primary_sdram_width, (unsigned int) get_ddr_freq(0)/1000000u, &dram_size, (void*) dram_init); + + dram_size = fsl_ddr_sdram(); + debug("dram_size 0 = 0x%llx\n", dram_size); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + debug("dram_size 1 = 0x%llx\n", dram_size); + dram_size *= 0x100000; + debug("dram_size = 0x%llx (%llu MB)\n\nEnd of SPL DDR init...", dram_size, dram_size/(1024U*1024U)); + +#else + debug ("\n**** NOT SPL_BUILD - DDR %i bits - %i MHz - (stack @ %p - fct @ %p) ****\n\n", + ddr_raw_timing.primary_sdram_width, (unsigned int) get_ddr_freq(0)/1000000u, &dram_size, dram_init); + + /* DDR has been initialised by SPL loader */ + dram_size = fsl_ddr_sdram_size(); + debug("dram_size 0 = 0x%llx\n", dram_size); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + debug("dram_size 1 = 0x%llx\n", dram_size); + dram_size *= 0x100000; + +#endif + + gd->ram_size = dram_size; + + return 0; +} |