diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.h | 2 | ||||
-rw-r--r-- | drivers/mtd/nand/jz4740_nand.c | 1 | ||||
-rw-r--r-- | drivers/spi/davinci_spi.c | 2 | ||||
-rw-r--r-- | drivers/spi/ep93xx_spi.c | 2 | ||||
-rwxr-xr-x | drivers/video/anx9804.c | 2 |
5 files changed, 0 insertions, 9 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index e2ff040..cb3fb24 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -32,8 +32,6 @@ */ #define MV_DEBUG_INIT -#define BIT(x) (1 << (x)) - #ifdef MV_DEBUG_INIT #define DEBUG_INIT_S(s) puts(s) #define DEBUG_INIT_D(d, l) printf("%x", d) diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 7a62cc3..abcedc2 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -16,7 +16,6 @@ #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) -#define BIT(x) (1 << (x)) #define JZ_NAND_ECC_CTRL_ENCODING BIT(3) #define JZ_NAND_ECC_CTRL_RS BIT(2) #define JZ_NAND_ECC_CTRL_RESET BIT(1) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0a036cc..0bd4f88 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -15,8 +15,6 @@ #include <asm/io.h> #include <asm/arch/hardware.h> -#define BIT(x) (1 << (x)) - /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 #define SPIGCR0_SPIRST_MASK 0x0 diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c index 235557e..cb682dd 100644 --- a/drivers/spi/ep93xx_spi.c +++ b/drivers/spi/ep93xx_spi.c @@ -16,8 +16,6 @@ #include <asm/arch/ep93xx.h> - -#define BIT(x) (1<<(x)) #define SSPBASE SPI_BASE #define SSPCR0 0x0000 diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index 83d60d6..37ad69a 100755 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -14,8 +14,6 @@ #include <i2c.h> #include "anx9804.h" -#define BIT(x) (1 << (x)) - /* Registers at i2c address 0x38 */ #define ANX9804_HDCP_CONTROL_0_REG 0x01 |