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Diffstat (limited to 'include/configs/QT1040-4GB.h')
| -rwxr-xr-x | include/configs/QT1040-4GB.h | 944 |
1 files changed, 944 insertions, 0 deletions
diff --git a/include/configs/QT1040-4GB.h b/include/configs/QT1040-4GB.h new file mode 100755 index 0000000..054b992 --- /dev/null +++ b/include/configs/QT1040-4GB.h @@ -0,0 +1,944 @@ +/* + * Copyright 2017 Scalys B.V. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _QT1040_4GB_H +#define _QT1040_4GB_H + +#include "simc-t10x0.h" +#include <generated/autoconf.h> + + + +#define CONFIG_MTD_UBI_WL_THRESHOLD 4096 +#define CONFIG_MTD_UBI_BEB_LIMIT 20 + + +#define MPC85XX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) + +/* + * QorIq-v2 4GB board configuration file + */ + +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) /* MT29F8G08ABBCAH4*/ + +/* + * System and DDR clock + */ +#define CONFIG_SYS_CLK_FREQ 100000000 /* 100 MHz */ +#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ + +#define QORV2_DDR4_1600MTS +/* #define QORV2_DDR4_1333MTS */ +/* #define QORV2_DDR4_1066MTS */ + +#ifdef CONFIG_RAMBOOT_PBL +/* We have to specify all the PBL and RCW since they are used without being + * proccessed by the preprocessor */ +#if defined(CONFIG_NAND_FLASH_BOOT) +/* normal boot from NAND flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg + +#ifdef QORV2_DDR4_1600MTS +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr1600_cpu1400_nand_rcw.cfg +#else /* 1600 */ +#ifdef QORV2_DDR4_1333MTS +#warning ---- QORV2 1333MTS ----- +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr1333_cpu1200_nand_rcw.cfg +#else +#ifdef QORV2_DDR4_1066MTS +#warning ---- QORV2 1066MTS ----- +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr1066_cpu1200_nand_rcw.cfg +#else +#ifdef QORV2_DDR4_0800MTS +#warning ---- QORV2 0800MTS ----- +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr0800_cpu1200_nand_rcw.cfg +#else +#error NO DDR SPEED DEFINED +#endif /* else 0800 */ +#endif /* else 1066 */ +#endif /* else 1333 */ +#endif /* else 1600 */ + +#elif defined(CONFIG_NOR_FLASH_BOOT) +/* normal boot from NOR flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr1600_cpu1400_nor_rcw.cfg +#elif defined(CONFIG_SPI_FLASH_BOOT) +/* normal boot from SPI flash */ +/* Possible TODO, verify SPI boot source */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr1600_cpu1400_spi_rcw.cfg +#elif defined(CONFIG_SDHC_FLASH_BOOT) +/* normal boot from SDHC flash */ +/* Possible TODO, further implement and verify SD card boot source, + * e.g. env and firmware locations */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-4gb-ddr1600_cpu1400_sdhc_rcw.cfg +#else +/* unknown configuration, this should not happen */ +#error Invalid or unsupported Boot configuration +#endif + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT + +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif /* CONFIG_SPL_BUILD */ + +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#ifdef CONFIG_NAND_FLASH +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SYS_NAND_U_BOOT_SIZE ( (2048-256) *1024) +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) + + +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#ifndef CONFIG_SDHC_FLASH_BOOT +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif +#endif /* CONFIG_NAND */ + +#ifdef CONFIG_SDHC_FLASH_BOOT +#define CONFIG_SDCARD +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + +#endif /* CONFIG_RAMBOOT_PBL */ + +/* High Level Configuration Options */ +#include <asm/config_mpc85xx.h> +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + + +/* #define CONFIG_DEEP_SLEEP */ /* support deep sleep */ +#define CONFIG_SILENT_CONSOLE + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif /* CONFIG_RESET_VECTOR_ADDRESS */ + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + + +#define CONFIG_PCI_INDIRECT_BRIDGE + + +/* The number of available PCI controllers depends on the RCW */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + + + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x200000 /* Refer to mtdparts */ +/* + * CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE + */ + +#if 0 +#if defined(CONFIG_SDCARD) +/* TODO: move env to boot source */ +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 0x800) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x200000 /* Refer to mtdparts */ +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif /* CONFIG_SPIFLASH */ +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC + +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +/* #define CONFIG_MEM_INIT_VALUE 0x0BADC0DE */ +#define CONFIG_MEM_INIT_VALUE 0x12345678 +#endif /* CONFIG_DDR_ECC */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +/* #define CONFIG_SYS_DRAM_TEST */ /* Executes a memory test at U-Boot start */ +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00200000 +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST + +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +/* TODO CLEANUP #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) */ +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) + + +/* + * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address + * (CONFIG_SYS_INIT_L3_VADDR) will be different. + */ +#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) + + +#endif /* CONFIG_RAMBOOT_PBL */ +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_SDRAM_SIZE 4096 /* In MByte, for fixed parameter use */ + +/* + * IFC Definitions + */ +#ifdef CONFIG_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#endif + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) + +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC on encode */ \ + CSOR_NAND_ECC_DEC_EN | /* ECC on decode */ \ + CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ + CSOR_NAND_RAL_3 | /* RAL = 3Byes */ \ + CSOR_NAND_PGS_2K | /* Page Size = 2K */ \ + CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ + CSOR_NAND_PB(64) | /* Pages Per Block = 64 */ \ + CSOR_NAND_BCTLD) /* Buffer control disable */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) + +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) + +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) + +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0xa) + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +/*#define CONFIG_CMD_NAND*/ + + +/* NOR configuation */ +/*#define CONFIG_SYS_NO_FLASH*/ +#define CONFIG_MTD +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_PROTECTION +/*#define CONFIG_SYS_NOR_BASE (0xe8000000) +#define CONFIG_SYS_NOR_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NOR_BASE) +*/ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + + +#define CONFIG_SYS_NOR_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) + +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD Toggle Enable during Burst Program */ \ + CSOR_NOR_ADM_SHIFT(7) | /* Address Data Multiplexing Shift */ \ + CSOR_NOR_TRHZ_80) | /* Time for Read Enable High to Output High Impedance */ \ + CSOR_NAND_BCTLD /* Buffer control disable */ + + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +/*#define CONFIG_BOARD_EARLY_INIT_R*/ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +#define CONFIG_SPL_GPIO_SUPPORT + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) + +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif + +/* Use the HUSH parser */ +/*#define CONFIG_SYS_HUSH_PARSER*/ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ + + +/* new uImage format support */ +#if 0 +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ +#endif + + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_E1000 +#define CONFIG_E1000_SPI +#define CONFIG_CMD_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +/* #define CONFIG_DOS_PARTITION */ +#endif /* CONFIG_PCI */ + +/* + * SATA + */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 + +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +/* #define CONFIG_DOS_PARTITION */ +#endif + +#define CONFIG_SPI_FLASH_MTD + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_HAS_FSL_DR_USB +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) +#define CONFIG_EHCI_DESC_BIG_ENDIAN /* Endiannes fix for EHCI USB */ +#endif +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +/*#define CONFIG_CMD_MMC*/ +/* #define CONFIG_GENERIC_MMC */ +#define CONFIG_CMD_EXT2 +/*#define CONFIG_CMD_FAT*/ +/* #define CONFIG_DOS_PARTITION */ +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + + +#define CONFIG_QE +#define CONFIG_U_QE + +/* Default address of microcode for the Linux Fman driver */ +/* TODO: move FMAN/QE ucode to boot source */ + +#if defined(CONFIG_SDHC_FLASH_BOOT) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. + */ +/*#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)*/ +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (0x240000) /* Refer to mtdparts: fman_ucode */ +#define CONFIG_SYS_QE_FW_ADDR (0x280000) /* Refer to mtdparts: qe_ucode */ + +#elif defined(CONFIG_NAND_FLASH_BOOT) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (0x240000) /* Refer to mtdparts: fman_ucode */ +#define CONFIG_SYS_QE_FW_ADDR (0x280000) /* Refer to mtdparts: qe_ucode */ + +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xe8240000 /* Refer to mtdparts: fman_ucode */ +#define CONFIG_SYS_QE_FW_ADDR 0xe8280000 /* Refer to mtdparts: qe_ucode */ +/* __stringify(CONFIG_LOADADDR) */ +#endif + +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +/*#define CONFIG_PHY_MARVELL*/ +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x00 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x01 + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC4" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +/*#define CONFIG_CMD_ERRATA*/ +#define CONFIG_CMD_GREPENV +/*#define CONFIG_CMD_IRQ*/ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +/*#define CONFIG_CMD_REGINFO*/ + +#ifdef CONFIG_PCI +/*#define CONFIG_CMD_PCI*/ +#endif + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +/*#define CONFIG_CMD_HASH*/ +#define CONFIG_SHA_HW_ACCEL +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 1000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Dynamic MTD Partition support with mtdparts + */ +/*#define CONFIG_CMD_MTDPARTS*/ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_NOR_FLASH + +/*#define CONFIG_SYS_NO_FLASH*/ + + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB +#endif + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +/* #define CONFIG_UBI_SILENCE_MSG */ +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* + * eSPI - Enhanced SPI + */ +#if defined(CONFIG_SPI_FLASH) +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION + +/*#define CONFIG_CMD_SF*/ +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +#define MTDIDS_DEFAULT \ + "nand0=fff800000.flash," \ + "nor0=fe8000000.nor" + +#define MTDPART_DEFAULT_PARTITIONS \ + "2M@0x0(u-boot)," \ + "256k(env)," \ + "256k(fman_ucode)," \ + "256k(qe_ucode)," + + +#ifdef CONFIG_NAND_FLASH + +#endif +#ifdef CONFIG_NOR_FLASH + +#endif +#define MTDPARTS_DEFAULT \ + "mtdparts=fff800000.flash:" \ + MTDPART_DEFAULT_PARTITIONS \ + "0x3fc80000(ubipart_nand)," \ + "1M@0x3ff00000(bbt)ro;" \ + "fe8000000.nor:" \ + MTDPART_DEFAULT_PARTITIONS \ + "-(ubipart_nor)" + +#ifdef CONFIG_NOR_FLASH +#define NOR_ENV \ + "update-uboot-nor-nw=" \ + "dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8000000 0xe81fffff;" \ + "erase 0xe8000000 0xe81fffff;" \ + "cp.w ${loadaddr} 0xe8000000 ${filesize};" \ + "fi\0" \ + "update-uboot-nor-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nor;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8000000 0xe81fffff;" \ + "erase 0xe8000000 0xe81fffff;" \ + "cp.w ${loadaddr} 0xe8000000 ${filesize};" \ + "fi\0" \ + \ + "update-fman-ucode-nor-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8240000 0xe827ffff;" \ + "erase 0xe8240000 0xe827ffff;" \ + "cp.w ${loadaddr} 0xe8240000 ${filesize};" \ + "fi\0" \ + "update-qe-ucode-nor-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8280000 0xe82bffff;" \ + "erase 0xe8280000 0xe82bffff;" \ + "cp.w ${loadaddr} 0xe8280000 ${filesize};" \ + "fi\0" \ + "update-ubi-rootfs-nor="\ + "dhcp;" \ + "ubi part ubipart_nor;" \ + "if test $? = \"0\"; then " \ + "tftp ${TFTP_PATH}/ubi_rootfs_image.nor.ubifs;" \ + "if test $? = \"0\"; then " \ + "ubi write ${loadaddr} rootfs ${filesize};" \ + "fi;" \ + "fi;" \ + "\0" \ + \ + "ubiboot-nor=" \ + "ubi part ubipart_nor;" \ + "ubifsmount ubi0:rootfs;" \ + "ubifsload ${fitaddr} /boot/fitImage.itb;" \ + "run set_ubiboot_args_nor;" \ + "bootm ${fitaddr}#conf@1" \ + "\0" \ + \ + "set_ubiboot_args_nor=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nor ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" +#else +#define NOR_ENV +#endif + +#ifdef CONFIG_NAND_FLASH +#define NAND_ENV \ + "update-uboot-nand-nw=" \ + "dhcp;" \ + "tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nand;" \ + "if test $? = \"0\"; then " \ + "nand erase.part u-boot;" \ + "nand write ${loadaddr} 0 ${filesize}; "\ + "fi\0" \ + "update-uboot-nand-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nand;" \ + "nand erase.part u-boot;" \ + "nand write ${loadaddr} u-boot ${filesize};" \ + "\0" \ + \ + "update-fman-ucode-nand-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \ + "nand erase.part fman_ucode;" \ + "nand write ${loadaddr} fman_ucode ${filesize};" \ + "\0" \ + \ + "update-qe-ucode-nand-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \ + "nand erase.part qe_ucode;" \ + "nand write ${loadaddr} qe_ucode ${filesize};" \ + "\0" \ + "update-ubi-rootfs-nand="\ + "dhcp;" \ + "ubi part ubipart_nand;" \ + "if test $? = \"0\"; then " \ + "tftp ${TFTP_PATH}/ubi_rootfs_image.nand.ubifs;" \ + "if test $? = \"0\"; then " \ + "ubi write ${loadaddr} rootfs ${filesize};" \ + "fi;" \ + "fi;" \ + "\0" \ + \ + "ubiboot-nand=" \ + "ubi part ubipart_nand;" \ + "ubifsmount ubi0:rootfs;" \ + "ubifsload ${fitaddr} /boot/fitImage.itb;" \ + "run set_ubiboot_args_nand;" \ + "bootm ${fitaddr}#conf@1" \ + "\0" \ + \ + "set_ubiboot_args_nand=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nand ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" +#else +#define NAND_ENV +#endif + +#ifdef CONFIG_NAND_FLASH_BOOT +#define BOOTCMD "ubiboot-nand" +#elif defined(CONFIG_NOR_FLASH_BOOT) +#define BOOTCMD "ubiboot-nor" +#else +#define BOOTCMD "" +#endif + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 + + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" \ + "fsl_ddr:bank_intlv=null;"\ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + \ + "l2switchaddr=02:00:00:ba:be:00\0" \ + "ethaddr=02:00:00:ba:be:01\0" \ + "eth1addr=02:00:00:ba:be:02\0" \ + "eth2addr=02:00:00:ba:be:03\0" \ + "eth3addr=02:00:00:ba:be:04\0" \ + "eth4addr=02:00:00:ba:be:05\0" \ + \ + "autoload=no\0" \ + "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "TFTP_PATH=\0" \ + \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + \ + NOR_ENV \ + NAND_ENV \ + \ + "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ + "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \ + "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \ + "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\ + \ + "probe-spi-flash=sf probe 0; if test $? = \"0\"; then " \ + "setenv mtdids \"${mtdids}\",nor1=fe110000.spi;" \ + "setenv mtdparts \"${mtdparts};\"fe110000.spi:" MTDPART_DEFAULT_PARTITIONS "-(storage);"\ + ";fi\0" \ + \ + "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \ + \ + "bootcmd=run setfans; run "BOOTCMD"\0" \ + \ + "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \ + "bootargs=console=ttyS0,115200 rootwait panic=10\0" \ + +#endif /* _QT1040_4GB_H */ |