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-rw-r--r--include/configs/B4860QDS.h11
-rw-r--r--include/configs/BSC9131RDB.h7
-rw-r--r--include/configs/BSC9132QDS.h11
-rw-r--r--include/configs/C29XPCIE.h7
-rw-r--r--include/configs/P1010RDB.h13
-rw-r--r--include/configs/P2041RDB.h11
-rw-r--r--include/configs/T1040QDS.h8
-rw-r--r--include/configs/T104xRDB.h8
-rw-r--r--include/configs/T208xQDS.h8
-rw-r--r--include/configs/T208xRDB.h8
-rw-r--r--include/configs/T4240QDS.h11
-rw-r--r--include/configs/T4240RDB.h8
-rw-r--r--include/configs/corenet_ds.h11
-rw-r--r--include/configs/ls1021aqds.h11
-rw-r--r--include/configs/ls1021atwr.h12
-rw-r--r--include/fsl_sec.h181
16 files changed, 325 insertions, 1 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 9063c57..dc1a9bc 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -82,6 +82,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
@@ -759,6 +760,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_NET
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* USB
*/
@@ -913,4 +920,8 @@ unsigned long get_board_ddr_clk(void);
#include <asm/fsl_secure_boot.h>
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 56a3e94..bc5af52 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -55,6 +55,7 @@
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
@@ -382,6 +383,12 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index aeded6d..989363c 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -78,6 +78,7 @@
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_PCI /* Enable PCI/PCIE */
@@ -598,6 +599,12 @@ combinations. this should be removed later
#define CONFIG_DOS_PARTITION
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -704,4 +711,8 @@ combinations. this should be removed later
#include <asm/fsl_secure_boot.h>
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 715616d..5d11278 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -86,6 +86,7 @@
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_PCI /* Enable PCI/PCIE */
@@ -506,6 +507,12 @@
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index a373990..d378dbd 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -53,7 +53,7 @@
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
@@ -170,6 +170,7 @@
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_PCI /* Enable PCI/PCIE */
@@ -832,6 +833,12 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_DOS_PARTITION
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -956,4 +963,8 @@ extern unsigned long get_sdram_size(void);
#include <asm/fsl_secure_boot.h>
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 16f7525..2e11aaa 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -49,6 +49,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
@@ -647,6 +648,12 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_DOS_PARTITION
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -743,4 +750,8 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#include <asm/fsl_secure_boot.h>
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index a781ba3..1d0664d 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -58,6 +58,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controler 1 */
@@ -716,6 +717,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_NET
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -818,6 +825,7 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 5e2c100..2bb86e4 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -113,6 +113,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controler 1 */
@@ -731,6 +732,12 @@
#define CONFIG_CMD_NET
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -865,6 +872,7 @@
#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 395472b..2733358 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -44,6 +44,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
@@ -777,6 +778,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_NET
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -909,6 +916,7 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
#undef CONFIG_CMD_USB
#endif
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e5936c7..400d979 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -37,6 +37,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
@@ -736,6 +737,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMD_NET
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -868,6 +875,7 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SECURE_BOOT
#include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
#undef CONFIG_CMD_USB
#endif
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index ca97247..1e0f5ec 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -15,6 +15,7 @@
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
@@ -506,6 +507,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* USB
*/
@@ -625,4 +632,8 @@ unsigned long get_board_ddr_clk(void);
#include <asm/fsl_secure_boot.h>
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 183255d..13f4bd3 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -47,6 +47,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
@@ -668,6 +669,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DOS_PARTITION
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define __USB_PHY_TYPE utmi
@@ -751,6 +758,7 @@ unsigned long get_board_ddr_clk(void);
* which is anyways not used in Secure Environment.
*/
#undef CONFIG_CMD_USB
+#define CONFIG_CMD_BLOB
#endif
#endif /* __CONFIG_H */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 12b3296..72b7efa 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -57,6 +57,7 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
@@ -648,6 +649,12 @@
#define CONFIG_DOS_PARTITION
#endif
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -745,4 +752,8 @@
#include <asm/fsl_secure_boot.h>
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..4221426 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -69,6 +69,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_HAS_SERDES
+#define CONFIG_FSL_CAAM /* Enable CAAM */
/*
* IFC Definitions
*/
@@ -388,4 +389,14 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..5868287 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -48,6 +48,8 @@
#define CONFIG_SYS_HAS_SERDES
+#define CONFIG_FSL_CAAM /* Enable CAAM */
+
/*
* IFC Definitions
*/
@@ -288,4 +290,14 @@
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ
+#define CONFIG_MISC_INIT_R
+
+/* Hash command with SHA acceleration supported in hardware */
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CMD_BLOB
+#endif
+
#endif
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
new file mode 100644
index 0000000..aa850a3
--- /dev/null
+++ b/include/fsl_sec.h
@@ -0,0 +1,181 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __FSL_SEC_H
+#define __FSL_SEC_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define sec_in32(a) in_le32(a)
+#define sec_out32(a, v) out_le32(a, v)
+#define sec_in16(a) in_le16(a)
+#define sec_clrbits32 clrbits_le32
+#define sec_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define sec_in32(a) in_be32(a)
+#define sec_out32(a, v) out_be32(a, v)
+#define sec_in16(a) in_be16(a)
+#define sec_clrbits32 clrbits_be32
+#define sec_setbits32 setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+
+/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+/* RNG4 TRNG test registers */
+struct rng4tst {
+#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+ u32 rtmctl; /* misc. control register */
+ u32 rtscmisc; /* statistical check misc. register */
+ u32 rtpkrrng; /* poker range register */
+#define RTSDCTL_ENT_DLY_MIN 1200
+#define RTSDCTL_ENT_DLY_MAX 12800
+ union {
+ u32 rtpkrmax; /* PRGM=1: poker max. limit register */
+ u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
+ };
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+ u32 rtsdctl; /* seed control register */
+ union {
+ u32 rtsblim; /* PRGM=1: sparse bit limit register */
+ u32 rttotsam; /* PRGM=0: total samples register */
+ };
+ u32 rtfreqmin; /* frequency count min. limit register */
+ union {
+ u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
+ u32 rtfreqcnt; /* PRGM=0: freq. count register */
+ };
+ u32 rsvd1[40];
+#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
+ u32 rdsta; /*RNG DRNG Status Register*/
+ u32 rsvd2[15];
+};
+
+typedef struct ccsr_sec {
+ u32 res0;
+ u32 mcfgr; /* Master CFG Register */
+ u8 res1[0x4];
+ u32 scfgr;
+ struct {
+ u32 ms; /* Job Ring LIODN Register, MS */
+ u32 ls; /* Job Ring LIODN Register, LS */
+ } jrliodnr[4];
+ u8 res2[0x2c];
+ u32 jrstartr; /* Job Ring Start Register */
+ struct {
+ u32 ms; /* RTIC LIODN Register, MS */
+ u32 ls; /* RTIC LIODN Register, LS */
+ } rticliodnr[4];
+ u8 res3[0x1c];
+ u32 decorr; /* DECO Request Register */
+ struct {
+ u32 ms; /* DECO LIODN Register, MS */
+ u32 ls; /* DECO LIODN Register, LS */
+ } decoliodnr[8];
+ u8 res4[0x40];
+ u32 dar; /* DECO Avail Register */
+ u32 drr; /* DECO Reset Register */
+ u8 res5[0x4d8];
+ struct rng4tst rng; /* RNG Registers */
+ u8 res11[0x8a0];
+ u32 crnr_ms; /* CHA Revision Number Register, MS */
+ u32 crnr_ls; /* CHA Revision Number Register, LS */
+ u32 ctpr_ms; /* Compile Time Parameters Register, MS */
+ u32 ctpr_ls; /* Compile Time Parameters Register, LS */
+ u8 res6[0x10];
+ u32 far_ms; /* Fault Address Register, MS */
+ u32 far_ls; /* Fault Address Register, LS */
+ u32 falr; /* Fault Address LIODN Register */
+ u32 fadr; /* Fault Address Detail Register */
+ u8 res7[0x4];
+ u32 csta; /* CAAM Status Register */
+ u8 res8[0x8];
+ u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
+ u32 ccbvid; /* CHA Cluster Block Version ID Register */
+ u32 chavid_ms; /* CHA Version ID Register, MS */
+ u32 chavid_ls; /* CHA Version ID Register, LS */
+ u32 chanum_ms; /* CHA Number Register, MS */
+ u32 chanum_ls; /* CHA Number Register, LS */
+ u32 secvid_ms; /* SEC Version ID Register, MS */
+ u32 secvid_ls; /* SEC Version ID Register, LS */
+ u8 res9[0x6020];
+ u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
+ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+ u8 res10[0x8fd8];
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN 0x08000000
+#define SEC_CTPR_MS_QI 0x02000000
+#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
+#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
+#define SEC_RVID_MA 0x0f000000
+#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT 28
+#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
+#define SEC_CHANUM_MS_DECONUM_SHIFT 24
+#define SEC_SECVID_MS_IPID_MASK 0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT 16
+#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
+#define SEC_CCBVID_ERA_MASK 0xff000000
+#define SEC_CCBVID_ERA_SHIFT 24
+#define SEC_SCFGR_RDBENABLE 0x00000400
+#define SEC_SCFGR_VIRT_EN 0x00008000
+#define SEC_CHAVID_LS_RNG_SHIFT 16
+#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
+
+#define CONFIG_JRSTARTR_JR0 0x00000001
+
+struct jr_regs {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 irba_l;
+ u32 irba_h;
+#else
+ u32 irba_h;
+ u32 irba_l;
+#endif
+ u32 rsvd1;
+ u32 irs;
+ u32 rsvd2;
+ u32 irsa;
+ u32 rsvd3;
+ u32 irja;
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 orba_l;
+ u32 orba_h;
+#else
+ u32 orba_h;
+ u32 orba_l;
+#endif
+ u32 rsvd4;
+ u32 ors;
+ u32 rsvd5;
+ u32 orjr;
+ u32 rsvd6;
+ u32 orsf;
+ u32 rsvd7;
+ u32 jrsta;
+ u32 rsvd8;
+ u32 jrint;
+ u32 jrcfg0;
+ u32 jrcfg1;
+ u32 rsvd9;
+ u32 irri;
+ u32 rsvd10;
+ u32 orwi;
+ u32 rsvd11;
+ u32 jrcr;
+};
+
+int sec_init(void);
+#endif
+
+#endif /* __FSL_SEC_H */
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