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-rw-r--r--include/asm-arm/io.h2
-rw-r--r--include/configs/sbc8548.h6
2 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index c33b9e8..f4ae307 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -123,7 +123,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
+ * big endian mode connectivity is in place, as described by numerous
* ARM documents:
*
* PCI: D0-D7 D8-D15 D16-D23 D24-D31
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 49a7234..c84b70a 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -148,7 +148,7 @@
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
*
* OR6:
- * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
* XAM = OR6[17:18] = 11
* CSNT = OR6[20] = 1
* ACS = half cycle delay = OR6[21:22] = 11
@@ -157,7 +157,7 @@
* EAD = use external address latch delay = OR6[31] = 1
*
* 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6
+ * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6
*/
#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
@@ -167,7 +167,7 @@
#define CFG_BR6_PRELIM 0xfb801801
#define CFG_OR0_PRELIM 0xff806e65
-#define CFG_OR6_PRELIM 0xfc006e65
+#define CFG_OR6_PRELIM 0xf8006e65
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */