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This commit moves source files as follows:
arch/arm/cpu/arm920t/at91/* -> arch/arm/mach-at91/arm920t/*
arch/arm/cpu/arm926ejs/at91/* -> arch/arm/mach-at91/arm926ejs/*
arch/arm/cpu/armv7/at91/* -> arch/arm/mach-at91/armv7/*
arch/arm/cpu/at91-common/* -> arch/arm/mach-at91/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.co>
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The SAMAA5D4 SoC can access DDR in interleave mode.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
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- compile mpddrc ram init code also for AT91SAM9M10G45
based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
in the cr configuration
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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use the configure value for computing the ba_off value
not the value from the cr register. This leaded in a
wrong ram configuration on the upcoming corvus spl board
support.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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