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Please pull another update for Broadcom MIPS.
This contains new SoC's, new boards and new drivers and some bugfixes.
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Mostly including the Armada 37xx pinctrl / gpio driver.
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Currently these (board agnostic) commands cannot be selected using
menuconfig and friends. Fix this the obvious way. As part of this,
don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v'
and "we have a hashing command" as this makes the Kconfig logic odd.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
[trini: Re-apply, add imply for a few cases, run moveconfig.py, also
migrate CRC32_VERIFY]
Signed-off-by: Tom Rini <trini@konsulko.com>
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Instead of having a peripheral clock of 50 MHz like the BCM63xx family, it
has a 48 MHz clock.
This fixes uart baud rate calculation for BCM3380.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This driver allows rebooting the SoC by calling wdt_expire_now op.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This driver controls the watchdog present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The dram_init and dram_init_banksize functions were using a board
specific implementation for decoding the memory banks from the fdt.
This change makes the dram_init* functions use a generic implementation
of decoding and populating memory bank and size data.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nathan Rossi <nathan@nathanrossi.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting
the correct PHY type (KR / SFI) for the COMPHY driver and enabling the
ethernet0 device node in the dts.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
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Start to populate the device tree of the Armada 37xx with the pincontrol
configuration used on the board providing a dts.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
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Add the nodes for the two pin controller present in the Armada 37xx SoCs.
Initially the node was named gpio1 using the same name that for the
register range in the datasheet. However renaming it pinctr_nb (nb for
North Bridge) makes more sens.
Minor changes for U-Boot because of the slightly different dts version
done by Stefan Roese.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
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Move FTMAC100 to where it should be, alphabetically in
drivers/net/Kconfig
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
drivers/net/Kconfig
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This patch adjusts memory map for images on LS2080ARDB and
LS2080AQDS NOR flash as below
Image Flash Offset
RCW+PBI 0x00000000
Boot firmware (U-Boot) 0x00100000
Boot firmware Environment 0x00300000
PPA firmware 0x00400000
PHY firmware 0x00980000
DPAA2 MC 0x00A00000
DPAA2 DPL 0x00D00000
DPAA2 DPC 0x00E00000
Kernel.itb 0x01000000
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Support Andestech eth ftmac100 device tree flow on AG101P/AE3XX platform.
Verification:
Boot linux kernel via dhcp and bootm ok.
NDS32 # setenv bootm_size 0x2000000;setenv fdt_high 0x1f00000;
NDS32 # dhcp 0x600000 10.0.4.97:boomimage-310y-ae300-spi.bin
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
DHCP client bound to address 10.0.4.178 (4899 ms)
Using mac@e0100000 device
TFTP from server 10.0.4.97; our IP address is 10.0.4.178
Filename 'boomimage-310y-ae300-spi.bin'.
Load address: 0x600000
Loading: #################################################################
#################################################################
#################################################################
...
...
###################################
233.4 KiB/s
done
Bytes transferred = 13872076 (d3abcc hex)
NDS32 # dhcp 0x2000000 10.0.4.97:ae300.dtb
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
DHCP client bound to address 10.0.4.178 (4592 ms)
Using mac@e0100000 device
TFTP from server 10.0.4.97; our IP address is 10.0.4.178
Filename 'ae300.dtb'.
Load address: 0x2000000
Loading: #
82 KiB/s
done
Bytes transferred = 2378 (94a hex)
NDS32 # bootm 0x600000 - 0x2000000
Image Name:
Created: 2017-03-22 6:52:03 UTC
Image Type: NDS32 Linux Kernel Image (uncompressed)
Data Size: 13872012 Bytes = 13.2 MiB
Load Address: 0000c000
Entry Point: 0000c000
Verifying Checksum ... OK
Booting using the fdt blob at 0x2000000
Loading Kernel Image ... OK
Loading Device Tree to 01efc000, end 01eff949 ... OK
Linux version 3.10.102-20375-gb0034c1-dirty (rick@app09)
(gcc version 4.9.3 (2016-07-06_nds32le-linux-glibc-v3_experimental) )
#293 PREEMPT Wed Mar 22 14:49:28 CST 2017
CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d11103f(id 13, rev 17, cfg 4159)
...
...
Signed-off-by: rick <rick@andestech.com>
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trini: Make Kconfig SPL_xxx entires only show if SPL, so that we don't
get Kconfig errors on platforms without SPL, ie sandbox (without SPL).
Signed-off-by: Tom Rini <trini@konsulko.com>
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Enable this option by default on sandbox to increase build coverage.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_LZMADEC
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_LZMA
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_IRQ
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_CMD_IOTRACE
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_IO
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_IMMAP
Also move this command out of the cmd/ directory since it is
PowerPC-specific.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate
CONFIG_IDE option so that IDE support can be enabled without requiring
the 'ide' command.
Update existing users and move the ide driver into drivers/block since
it should not be in common/.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_HDMIDETECT
Note that we cannot do 'default y if VIDEO' because this option is only
enabled for a small subset of mx6 boards. Also this command is is not a
great implementation (it doesn't use driver model).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_CMD_HASH
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Rework slightly, enable on some boards again]
Signed-off-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_CMD_GETTIME
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_CMD_FUSE
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_FPGA_LOADBP
CONFIG_CMD_FPGA_LOADFS
CONFIG_CMD_FPGA_LOADMK
CONFIG_CMD_FPGA_LOADP
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_ESBC_VALIDATE
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_CMD_ERRATA
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_CMD_ENTERRCM
Signed-off-by: Simon Glass <sjg@chromium.org>
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This converts the following to Kconfig:
CONFIG_CMD_EEPROM
CONFIG_CMD_EEPROM_LAYOUT
CONFIG_EEPROM_LAYOUT_HELP_STRING
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Rework Kconfig logic slightly, define EEPROM location on TI eval
platforms]
Signed-off-by: Tom Rini <trini@konsulko.com>
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