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2015-01-21fpga: xilinx: spartan3: Setup NULL fpga_op without driverMichal Simek
Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: xilinx: Simplify load/dump/info function handlingMichal Simek
Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: xilinx: Fix the rest of CamelCasesMichal Simek
No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: xilinx: Avoid CamelCase for in Xilinx_descMichal Simek
No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13fpga: spartan3: Avoid CamelCaseMichal Simek
No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2012-01-05fpga: add definition for Xilinx Spartan-6 XC6SLX4Stefano Babic
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-08-01fpga: constify to fix build warningWolfgang Denk
Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
2010-11-30add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fnsWolfgang Wegner
Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
2010-03-24add block write function to spartan3 slave serial loadWolfgang Wegner
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2009-10-03fpga: Remove relocation fixupsPeter Tyser
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-09-22Fix Spartan-3 definitions.Laurent Pinchart
A few Spartan-3 definitions erroneously use Spartan-3E size constants. This patch fixes them. Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
2008-09-22Remove duplicate Spartan-3E definition.Laurent Pinchart
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-20Big white-space cleanup.Wolfgang Denk
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-09Add new Xilinx Spartan FPGA typesMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-01-09Add pre and post configuration callbacks for Spartan FPGAsMatthias Fuchs
This patch adds a post configuration callback for Spartan2/3 FPGAs. pre and post configuration callback are now optional and not called when the function pointer is set to NULL. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-08-10add image size and descriptors for Spartan 3E FPGA chipsBruce Adler
Spartan 3E image sizes taken from Table 1-4 in Xilinx UG332 (v1.1) Signed-off by: Bruce Adler <bruce.adler@ccpu.com>
2005-09-25Add Xilinx Spartan3 family FPGA supportWolfgang Denk
Patch by Kurt Stremerch, 14 February 2005