blob: 39726355e67c9341853626cf865f0dbb22c41a92 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
/*
* ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
#define __ASM_ARCH_RCAR_GEN3_BASE_H
/*
* R-Car (R8A7750) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xEE220200
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
/* SCIF */
#define SCIF0_BASE 0xE6E60000
#define SCIF1_BASE 0xE6E68000
#define SCIF2_BASE 0xE6E88000
#define SCIF3_BASE 0xE6C50000
#define SCIF4_BASE 0xE6C40000
#define SCIF5_BASE 0xE6F30000
/* Module stop status register */
#define MSTPSR0 0xE6150030
#define MSTPSR1 0xE6150038
#define MSTPSR2 0xE6150040
#define MSTPSR3 0xE6150048
#define MSTPSR4 0xE615004C
#define MSTPSR5 0xE615003C
#define MSTPSR6 0xE61501C0
#define MSTPSR7 0xE61501C4
#define MSTPSR8 0xE61509A0
#define MSTPSR9 0xE61509A4
#define MSTPSR10 0xE61509A8
#define MSTPSR11 0xE61509AC
/* Realtime module stop control register */
#define RMSTPCR0 0xE6150110
#define RMSTPCR1 0xE6150114
#define RMSTPCR2 0xE6150118
#define RMSTPCR3 0xE615011C
#define RMSTPCR4 0xE6150120
#define RMSTPCR5 0xE6150124
#define RMSTPCR6 0xE6150128
#define RMSTPCR7 0xE615012C
#define RMSTPCR8 0xE6150980
#define RMSTPCR9 0xE6150984
#define RMSTPCR10 0xE6150988
#define RMSTPCR11 0xE615098C
/* System module stop control register */
#define SMSTPCR0 0xE6150130
#define SMSTPCR1 0xE6150134
#define SMSTPCR2 0xE6150138
#define SMSTPCR3 0xE615013C
#define SMSTPCR4 0xE6150140
#define SMSTPCR5 0xE6150144
#define SMSTPCR6 0xE6150148
#define SMSTPCR7 0xE615014C
#define SMSTPCR8 0xE6150990
#define SMSTPCR9 0xE6150994
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
/* SDHI */
#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
/* PFC */
#define PFC_PUEN5 0xE6060414
#define PUEN_SSI_SDATA4 BIT(17)
#define PFC_PUEN6 0xE6060418
#define PUEN_USB1_OVC (1 << 2)
#define PUEN_USB1_PWEN (1 << 1)
/* IICDVFS (I2C) */
#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct rcar_rwdt {
u32 rwtcnt;
u32 rwtcsra;
u32 rwtcsrb;
};
/* SWDT */
struct rcar_swdt {
u32 swtcnt;
u32 swtcsra;
u32 swtcsrb;
};
#endif
#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */
|
