summaryrefslogtreecommitdiff
path: root/arch/arm/mach-uniphier/spl_board_init.c
blob: da749a3d6d4e43cc66f70353545b74cb23180fe3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
/*
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <debug_uart.h>
#include <spl.h>

#include "init.h"
#include "micro-support-card.h"
#include "soc-info.h"

struct uniphier_spl_initdata {
	unsigned int soc_id;
	void (*bcu_init)(const struct uniphier_board_data *bd);
	void (*early_clk_init)(void);
	int (*dpll_init)(const struct uniphier_board_data *bd);
	int (*memconf_init)(const struct uniphier_board_data *bd);
	void (*dram_clk_init)(void);
	int (*umc_init)(const struct uniphier_board_data *bd);
};

static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
	{
		.soc_id = UNIPHIER_SLD3_ID,
		.bcu_init = uniphier_sld3_bcu_init,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_sld3_dpll_init,
		.memconf_init = uniphier_memconf_3ch_no_disbit_init,
		.dram_clk_init = uniphier_sld3_dram_clk_init,
		.umc_init = uniphier_sld3_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
	{
		.soc_id = UNIPHIER_LD4_ID,
		.bcu_init = uniphier_ld4_bcu_init,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_ld4_dpll_init,
		.memconf_init = uniphier_memconf_2ch_init,
		.dram_clk_init = uniphier_sld3_dram_clk_init,
		.umc_init = uniphier_ld4_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
	{
		.soc_id = UNIPHIER_PRO4_ID,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_pro4_dpll_init,
		.memconf_init = uniphier_memconf_2ch_init,
		.dram_clk_init = uniphier_sld3_dram_clk_init,
		.umc_init = uniphier_pro4_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
	{
		.soc_id = UNIPHIER_SLD8_ID,
		.bcu_init = uniphier_ld4_bcu_init,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_sld8_dpll_init,
		.memconf_init = uniphier_memconf_2ch_init,
		.dram_clk_init = uniphier_sld3_dram_clk_init,
		.umc_init = uniphier_sld8_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
	{
		.soc_id = UNIPHIER_PRO5_ID,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_pro5_dpll_init,
		.memconf_init = uniphier_memconf_2ch_init,
		.dram_clk_init = uniphier_pro5_dram_clk_init,
		.umc_init = uniphier_pro5_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
	{
		.soc_id = UNIPHIER_PXS2_ID,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_pxs2_dpll_init,
		.memconf_init = uniphier_memconf_3ch_init,
		.dram_clk_init = uniphier_pxs2_dram_clk_init,
		.umc_init = uniphier_pxs2_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
	{
		.soc_id = UNIPHIER_LD6B_ID,
		.early_clk_init = uniphier_sld3_early_clk_init,
		.dpll_init = uniphier_pxs2_dpll_init,
		.memconf_init = uniphier_memconf_3ch_init,
		.dram_clk_init = uniphier_pxs2_dram_clk_init,
		.umc_init = uniphier_pxs2_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	{
		.soc_id = UNIPHIER_LD11_ID,
		.early_clk_init = uniphier_ld11_early_clk_init,
		.dpll_init = uniphier_ld11_dpll_init,
		.memconf_init = uniphier_memconf_2ch_init,
		.dram_clk_init = uniphier_ld11_dram_clk_init,
		.umc_init = uniphier_ld11_umc_init,
	},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
	{
		.soc_id = UNIPHIER_LD20_ID,
		.early_clk_init = uniphier_ld11_early_clk_init,
		.dpll_init = uniphier_ld20_dpll_init,
		.memconf_init = uniphier_memconf_3ch_init,
		.dram_clk_init = uniphier_ld20_dram_clk_init,
		.umc_init = uniphier_ld20_umc_init,
	},
#endif
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)

void spl_board_init(void)
{
	const struct uniphier_board_data *bd;
	const struct uniphier_spl_initdata *initdata;
	int ret;

#ifdef CONFIG_DEBUG_UART
	debug_uart_init();
#endif

	bd = uniphier_get_board_param();
	if (!bd)
		hang();

	initdata = uniphier_get_spl_initdata();
	if (!initdata)
		hang();

	if (initdata->bcu_init)
		initdata->bcu_init(bd);


	initdata->early_clk_init();


#ifdef CONFIG_SPL_SERIAL_SUPPORT
	preloader_console_init();
#endif

	ret = initdata->dpll_init(bd);
	if (ret) {
		pr_err("failed to init DPLL\n");
		hang();
	}

	ret = initdata->memconf_init(bd);
	if (ret) {
		pr_err("failed to init MEMCONF\n");
		hang();
	}

	initdata->dram_clk_init();

	ret = initdata->umc_init(bd);
	if (ret) {
		pr_err("failed to init DRAM\n");
		hang();
	}
}