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authorStefan Sicleru <stefan.sicleru@freescale.com>2014-04-15 08:30:02 (GMT)
committerJose Rivera <German.Rivera@freescale.com>2014-04-15 14:23:43 (GMT)
commit59283bc18e045b47ae8141d3e3de5754f073f8e2 (patch)
treef81f51c90095f461b978e1a846c44b3ef6852293
parent857692491a0beed72330e5c13935675c0449b963 (diff)
downloadlinux-fsl-qoriq-59283bc18e045b47ae8141d3e3de5754f073f8e2.tar.xz
T1040RDB: Fix: Add L2 switch support and device tree bindings
Added port indexes and compatible strings for each port and for the L2 switch node itself. Added L2 switch device tree binding. Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Change-Id: I0d1383fbde82698bf6bdbbf275dadd7768bf0f8d Reviewed-on: http://git.am.freescale.net:8181/10978 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Razvan Stefanescu <razvan.stefanescu@freescale.com> Reviewed-by: Codrin Constantin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/l2-switch.txt99
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-l2switch-0.dtsi93
-rw-r--r--arch/powerpc/boot/dts/fsl/t1040si-post.dtsi1
3 files changed, 193 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2-switch.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2-switch.txt
new file mode 100644
index 0000000..c192f74
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/l2-switch.txt
@@ -0,0 +1,99 @@
+T1040 L2switch Device Tree Binding
+Copyright (C) 2013 Freescale Semiconductor Inc.
+
+CONTENTS
+ - Overview
+ - L2switch Node
+ - Port Node
+
+=====================================================================
+Overview
+
+DESCRIPTION
+
+ T1040 integrates a Gigabit Ethernet switch core with eight 10/100/1000 Mbps
+ Ethernet ports and two 10/100/1000/2500 Mbps ports.
+
+=====================================================================
+L2switch Node
+
+Description
+
+ This node specifies the address range of l2switch configuration registers
+ and interrupts. It also contains a set of child nodes defining the
+ Ethernet ports.
+
+PROPERTIES
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: Must include "vitesse-9953"
+
+ - reg
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Standard property which specifies the physical address and
+ length of the l2switch configuration registers.
+
+ - interrupts
+ Usage: required
+ Value type: <prop_encoded-array>
+ Definition: Standard property, specifies the interrupts generated by
+ this device.
+ The value of the interrupts property consists of one interrupt
+ specifier. The format of the specifier is defined by the binding
+ document describing the node's interrupt parent.
+
+=====================================================================
+Port Node
+
+Description
+
+ This node specifies the status and connection type of each of the Ethernet
+ ports.
+
+PROPERTIES
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: Must include "vitesse-9953-port"
+
+ - port-index
+ Usage: required
+ Value type: <u32>
+ Definition: Specifies the port index. Values 0, 1 are used by the two
+ internal 10/100/1000/2500 Mbps ports, values 2-9 are used by the
+ eight external 10/100/1000 Mbps ports.
+
+ - phy-connection-type
+ Usage: required
+ Value type: <string>
+ Definition: Specifies the controller/PHY interface type.
+
+ - status
+ Usage: optional
+ Value type: <string>
+ Definition: Standard property.
+ Indicates the operational status of the port. "disabled" is used
+ to indicate that the port is not usable (for example because the
+ QSGMII link to the PHYs is not available with current RCW).
+
+ - fixed-link
+ Usage: optional
+ Value type: <prop_encoded-array>
+ Definition: Specifies link parameters in the absence of a PHY.
+ <a b c d e> where a is emulated phy id - must be unique to among
+ all specified fixed-links, b is duplex - 0 half, 1 full, c is
+ link speed - 10/100/1000/2500, d is pause - 0 no pause, 1 pause,
+ e is asym_pause - 0 no asym_pause, 1 asym_pause.
+
+ - phy-handle
+ Usage: optional
+ Value type: <phandle>
+ Definition: The phandle for the PHY connected to this l2switch port.
+
+
+ Note: All other standard properties (see the ePAPR) are allowed but are
+ optional.
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-l2switch-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-l2switch-0.dtsi
new file mode 100644
index 0000000..e15ac3c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-l2switch-0.dtsi
@@ -0,0 +1,93 @@
+/*
+ * T1040 Silicon/SoC L2switch device tree stub [ controller @ offset 0x800000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+l2switch: l2switch@800000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "vitesse-9953";
+ clock-frequency = <0>;
+
+ reg = <0x800000 0x290000>;
+
+ port@100000 {
+ compatible = "vitesse-9953-port";
+ port-index = <0>;
+ };
+
+ port@110000 {
+ compatible = "vitesse-9953-port";
+ port-index = <1>;
+ };
+
+ port@120000 {
+ compatible = "vitesse-9953-port";
+ port-index = <2>;
+ };
+
+ port@130000 {
+ compatible = "vitesse-9953-port";
+ port-index = <3>;
+ };
+
+ port@140000 {
+ compatible = "vitesse-9953-port";
+ port-index = <4>;
+ };
+
+ port@150000 {
+ compatible = "vitesse-9953-port";
+ port-index = <5>;
+ };
+
+ port@160000 {
+ compatible = "vitesse-9953-port";
+ port-index = <6>;
+ };
+
+ port@170000 {
+ compatible = "vitesse-9953-port";
+ port-index = <7>;
+ };
+
+ port@180000 {
+ compatible = "vitesse-9953-port";
+ port-index = <8>;
+ };
+
+ port@190000 {
+ compatible = "vitesse-9953-port";
+ port-index = <9>;
+ };
+ };
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 23d0ae5..f48d5c2 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -638,6 +638,7 @@ sata@221000 {
status = "disabled";
};
};
+/include/ "qoriq-l2switch-0.dtsi"
l2switch@800000 {
interrupts = <26 2 0 0>;