diff options
| author | Scott Wood <scottwood@freescale.com> | 2014-04-07 23:49:35 (GMT) |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-04-07 23:49:35 (GMT) |
| commit | 62b8c978ee6b8d135d9e7953221de58000dba986 (patch) | |
| tree | 683b04b2e627f6710c22c151b23c8cc9a165315e /arch/arm | |
| parent | 78fd82238d0e5716578c326404184a27ba67fd6e (diff) | |
| download | linux-fsl-qoriq-62b8c978ee6b8d135d9e7953221de58000dba986.tar.xz | |
Rewind v3.13-rc3+ (78fd82238d0e5716) to v3.12
Diffstat (limited to 'arch/arm')
894 files changed, 18752 insertions, 36806 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1f1a7e..1ad6fb6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -5,8 +5,6 @@ config ARM select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAVE_CUSTOM_GPIO_H - select ARCH_MIGHT_HAVE_PC_PARPORT - select ARCH_USE_CMPXCHG_LOCKREF select ARCH_WANT_IPC_PARSE_VERSION select BUILDTIME_EXTABLE_SORT if MMU select CLONE_BACKWARDS @@ -25,7 +23,7 @@ config ARM select HARDIRQS_SW_RESEND select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB - select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT select HAVE_CONTEXT_TRACKING @@ -53,12 +51,9 @@ config ARM select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND select HAVE_OPROFILE if (HAVE_PERF_EVENTS) select HAVE_PERF_EVENTS - select HAVE_PERF_REGS - select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 - select HAVE_VIRT_CPU_ACCOUNTING_GEN select IRQ_FORCED_THREADING select KTIME_SCALAR select MODULES_USE_ELF_REL @@ -322,7 +317,6 @@ config ARCH_INTEGRATOR select NEED_MACH_MEMORY_H select PLAT_VERSATILE select SPARSE_IRQ - select USE_OF select VERSATILE_FPGA_IRQ help Support for ARM's Integrator platform. @@ -364,6 +358,7 @@ config ARCH_AT91 bool "Atmel AT91" select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select HAVE_CLK select IRQ_DOMAIN select NEED_MACH_GPIO_H select NEED_MACH_IO_H if PCCARD @@ -377,6 +372,7 @@ config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB select AUTO_ZRELADDR + select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK select CPU_ARM720T @@ -390,9 +386,9 @@ config ARCH_CLPS711X config ARCH_GEMINI bool "Cortina Systems Gemini" select ARCH_REQUIRE_GPIOLIB - select CLKSRC_MMIO + select ARCH_USES_GETTIMEOFFSET select CPU_FA526 - select GENERIC_CLOCKEVENTS + select NEED_MACH_GPIO_H help Support for the Cortina Systems Gemini family SoCs @@ -461,7 +457,7 @@ config ARCH_IOP32X depends on MMU select ARCH_REQUIRE_GPIOLIB select CPU_XSCALE - select GPIO_IOP + select NEED_MACH_GPIO_H select NEED_RET_TO_USER select PCI select PLAT_IOP @@ -474,7 +470,7 @@ config ARCH_IOP33X depends on MMU select ARCH_REQUIRE_GPIOLIB select CPU_XSCALE - select GPIO_IOP + select NEED_MACH_GPIO_H select NEED_RET_TO_USER select PCI select PLAT_IOP @@ -485,7 +481,6 @@ config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU select ARCH_HAS_DMA_SET_COHERENT_MASK - select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_REQUIRE_GPIOLIB select CLKSRC_MMIO select CPU_XSCALE @@ -564,6 +559,7 @@ config ARCH_MMP select GPIO_PXA select IRQ_DOMAIN select MULTI_IRQ_HANDLER + select NEED_MACH_GPIO_H select PINCTRL select PLAT_PXA select SPARSE_IRQ @@ -626,6 +622,7 @@ config ARCH_PXA select GPIO_PXA select HAVE_IDE select MULTI_IRQ_HANDLER + select NEED_MACH_GPIO_H select PLAT_PXA select SPARSE_IRQ help @@ -634,6 +631,7 @@ config ARCH_PXA config ARCH_MSM bool "Qualcomm MSM" select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP select CLKSRC_OF if OF select COMMON_CLK select GENERIC_CLOCKEVENTS @@ -651,6 +649,7 @@ config ARCH_SHMOBILE select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select HAVE_CLK select HAVE_MACH_CLKDEV select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 @@ -693,6 +692,7 @@ config ARCH_SA1100 select GENERIC_CLOCKEVENTS select HAVE_IDE select ISA + select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ help @@ -706,6 +706,7 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -726,22 +727,21 @@ config ARCH_S3C64XX select ARM_VIC select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM - select COMMON_CLK select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_TCM select NEED_MACH_GPIO_H select NO_IOPORT select PLAT_SAMSUNG - select PM_GENERIC_DOMAINS select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS + select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT - select SAMSUNG_WAKEMASK select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI help @@ -754,6 +754,7 @@ config ARCH_S5P64X0 select CPU_V6 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -772,6 +773,7 @@ config ARCH_S5PC100 select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -791,6 +793,7 @@ config ARCH_S5PV210 select CPU_V7 select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -807,9 +810,11 @@ config ARCH_EXYNOS select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE select ARM_GIC + select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS + select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS @@ -819,6 +824,20 @@ config ARCH_EXYNOS help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) +config ARCH_SHARK + bool "Shark" + select ARCH_USES_GETTIMEOFFSET + select CPU_SA110 + select ISA + select ISA_DMA + select NEED_MACH_MEMORY_H + select PCI + select VIRT_TO_BUS + select ZONE_DMA + help + Support for the StrongARM based Digital DNARD machine, also known + as "Shark" (<http://www.shark-linux.de/shark.html>). + config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL @@ -828,6 +847,7 @@ config ARCH_DAVINCI select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select HAVE_IDE + select NEED_MACH_GPIO_H select TI_PRIV_EDMA select USE_OF select ZONE_DMA @@ -845,6 +865,7 @@ config ARCH_OMAP1 select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP + select HAVE_CLK select HAVE_IDE select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD @@ -988,7 +1009,9 @@ source "arch/arm/mach-sti/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" +if ARCH_S3C64XX source "arch/arm/mach-s3c64xx/Kconfig" +endif source "arch/arm/mach-s5p64x0/Kconfig" @@ -1068,6 +1091,11 @@ config IWMMXT Enable support for iWMMXt context switching at run time if running on a CPU that supports it. +config XSCALE_PMU + bool + depends on CPU_XSCALE + default y + config MULTI_IRQ_HANDLER bool help @@ -1403,6 +1431,12 @@ config PCI_NANOENGINE config PCI_SYSCALL def_bool PCI +# Select the host bridge type +config PCI_HOST_VIA82C505 + bool + depends on PCI && ARCH_SHARK + default y + config PCI_HOST_ITE8152 bool depends on PCI && MACH_ARMCORE @@ -1433,6 +1467,7 @@ config SMP depends on GENERIC_CLOCKEVENTS depends on HAVE_SMP depends on MMU || ARM_MPU + select USE_GENERIC_SMP_HELPERS help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -1496,7 +1531,6 @@ config HAVE_ARM_ARCH_TIMER bool "Architected timer support" depends on CPU_V7 select ARM_ARCH_TIMER - select GENERIC_CLOCKEVENTS help This option enables support for the ARM architected timer @@ -1515,32 +1549,6 @@ config MCPM for (multi-)cluster based systems, such as big.LITTLE based systems. -config BIG_LITTLE - bool "big.LITTLE support (Experimental)" - depends on CPU_V7 && SMP - select MCPM - help - This option enables support selections for the big.LITTLE - system architecture. - -config BL_SWITCHER - bool "big.LITTLE switcher support" - depends on BIG_LITTLE && MCPM && HOTPLUG_CPU - select CPU_PM - select ARM_CPU_SUSPEND - help - The big.LITTLE "switcher" provides the core functionality to - transparently handle transition between a cluster of A15's - and a cluster of A7's in a big.LITTLE system. - -config BL_SWITCHER_DUMMY_IF - tristate "Simple big.LITTLE switcher user interface" - depends on BL_SWITCHER && DEBUG_KERNEL - help - This is a simple and dummy char dev interface to control - the big.LITTLE switcher core code. It is meant for - debugging purposes only. - choice prompt "Memory split" default VMSPLIT_3G @@ -1720,6 +1728,7 @@ config AEABI config OABI_COMPAT bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" depends on AEABI && !THUMB2_KERNEL + default y help This option preserves the old syscall interface along with the new (ARM EABI) one. It also provides a compatibility layer to @@ -1727,16 +1736,11 @@ config OABI_COMPAT in memory differs between the legacy ABI and the new ARM EABI (only for non "thumb" binaries). This option adds a tiny overhead to all syscalls and produces a slightly larger kernel. - - The seccomp filter system will not be available when this is - selected, since there is no way yet to sensibly distinguish - between calling conventions during filtering. - If you know you'll be using only pure EABI user space then you can say N here. If this option is not selected and you attempt to execute a legacy ABI binary then the result will be UNPREDICTABLE (in fact it can be predicted that it won't work - at all). If in doubt say N. + at all). If in doubt say Y. config ARCH_HAS_HOLES_MEMORYMODEL bool @@ -1868,12 +1872,6 @@ config CC_STACKPROTECTOR neutralized via a kernel panic. This feature requires gcc version 4.2 or above. -config SWIOTLB - def_bool y - -config IOMMU_HELPER - def_bool SWIOTLB - config XEN_DOM0 def_bool y depends on XEN @@ -1884,7 +1882,6 @@ config XEN depends on CPU_V7 && !CPU_V6 depends on !GENERIC_ATOMIC64 select ARM_PSCI - select SWIOTLB_XEN help Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5765abf..9762c84 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -318,7 +318,6 @@ choice config DEBUG_MSM_UART1 bool "Kernel low-level debugging messages via MSM UART1" depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 - select DEBUG_MSM_UART help Say Y here if you want the debug print routines to direct their output to the first serial port on MSM devices. @@ -326,7 +325,6 @@ choice config DEBUG_MSM_UART2 bool "Kernel low-level debugging messages via MSM UART2" depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 - select DEBUG_MSM_UART help Say Y here if you want the debug print routines to direct their output to the second serial port on MSM devices. @@ -334,7 +332,6 @@ choice config DEBUG_MSM_UART3 bool "Kernel low-level debugging messages via MSM UART3" depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 - select DEBUG_MSM_UART help Say Y here if you want the debug print routines to direct their output to the third serial port on MSM devices. @@ -343,7 +340,6 @@ choice bool "Kernel low-level debugging messages via MSM 8660 UART" depends on ARCH_MSM8X60 select MSM_HAS_DEBUG_UART_HS - select DEBUG_MSM_UART help Say Y here if you want the debug print routines to direct their output to the serial port on MSM 8660 devices. @@ -352,20 +348,10 @@ choice bool "Kernel low-level debugging messages via MSM 8960 UART" depends on ARCH_MSM8960 select MSM_HAS_DEBUG_UART_HS - select DEBUG_MSM_UART help Say Y here if you want the debug print routines to direct their output to the serial port on MSM 8960 devices. - config DEBUG_MSM8974_UART - bool "Kernel low-level debugging messages via MSM 8974 UART" - depends on ARCH_MSM8974 - select MSM_HAS_DEBUG_UART_HS - select DEBUG_MSM_UART - help - Say Y here if you want the debug print routines to direct - their output to the serial port on MSM 8974 devices. - config DEBUG_MVEBU_UART bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)" depends on ARCH_MVEBU @@ -400,13 +386,6 @@ choice when u-boot hands over to the kernel, the system silently crashes, with no serial output at all. - config DEBUG_VF_UART - bool "Vybrid UART" - depends on SOC_VF610 - help - Say Y here if you want kernel low-level debugging support - on Vybrid based platforms. - config DEBUG_NOMADIK_UART bool "Kernel low-level debugging messages via NOMADIK UART" depends on ARCH_NOMADIK @@ -855,20 +834,6 @@ choice options; the platform specific options are deprecated and will be soon removed. - config DEBUG_LL_UART_EFM32 - bool "Kernel low-level debugging via efm32 UART" - depends on ARCH_EFM32 - help - Say Y here if you want the debug print routines to direct - their output to an UART or USART port on efm32 based - machines. Use the following addresses for DEBUG_UART_PHYS: - - 0x4000c000 | USART0 - 0x4000c400 | USART1 - 0x4000c800 | USART2 - 0x4000e000 | UART0 - 0x4000e400 | UART1 - config DEBUG_LL_UART_PL01X bool "Kernel low-level debugging via ARM Ltd PL01x Primecell UART" help @@ -915,16 +880,11 @@ config DEBUG_STI_UART bool depends on ARCH_STI -config DEBUG_MSM_UART - bool - depends on ARCH_MSM - config DEBUG_LL_INCLUDE string default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X default "debug/exynos.S" if DEBUG_EXYNOS_UART - default "debug/efm32.S" if DEBUG_LL_UART_EFM32 default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ @@ -935,14 +895,17 @@ config DEBUG_LL_INCLUDE DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART - default "debug/msm.S" if DEBUG_MSM_UART + default "debug/msm.S" if DEBUG_MSM_UART1 || \ + DEBUG_MSM_UART2 || \ + DEBUG_MSM_UART3 || \ + DEBUG_MSM8660_UART || \ + DEBUG_MSM8960_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/sti.S" if DEBUG_STI_UART default "debug/tegra.S" if DEBUG_TEGRA_UART default "debug/ux500.S" if DEBUG_UX500_UART default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT - default "debug/vf.S" if DEBUG_VF_UART default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "mach/debug-macro.S" @@ -988,7 +951,6 @@ config DEBUG_UART_PHYS default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 default 0x20201000 if DEBUG_BCM2835 - default 0x4000e400 if DEBUG_LL_UART_EFM32 default 0x40090000 if ARCH_LPC32XX default 0x40100000 if DEBUG_PXA_UART1 default 0x42000000 if ARCH_GEMINI @@ -1019,7 +981,6 @@ config DEBUG_UART_PHYS default 0xfff36000 if DEBUG_HIGHBANK_UART default 0xfffff700 if ARCH_IOP33X depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ - DEBUG_LL_UART_EFM32 || \ DEBUG_UART_8250 || DEBUG_UART_PL01X config DEBUG_UART_VIRT diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c99b108..db50b62 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -16,7 +16,6 @@ LDFLAGS := LDFLAGS_vmlinux :=-p --no-undefined -X ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 -LDFLAGS_MODULE += --be8 endif OBJCOPYFLAGS :=-O binary -R .comment -S @@ -189,6 +188,7 @@ machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0 machine-$(CONFIG_ARCH_S5PC100) += s5pc100 machine-$(CONFIG_ARCH_S5PV210) += s5pv210 machine-$(CONFIG_ARCH_SA1100) += sa1100 +machine-$(CONFIG_ARCH_SHARK) += shark machine-$(CONFIG_ARCH_SHMOBILE) += shmobile machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile machine-$(CONFIG_ARCH_SIRF) += prima2 diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e7190bb..7ac1610 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -44,6 +44,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y) OBJS += ll_char_wr.o font.o endif +ifeq ($(CONFIG_ARCH_SHARK),y) +OBJS += head-shark.o ofw-shark.o +endif + ifeq ($(CONFIG_ARCH_SA1100),y) OBJS += head-sa1100.o endif diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S new file mode 100644 index 0000000..92b5689 --- /dev/null +++ b/arch/arm/boot/compressed/head-shark.S @@ -0,0 +1,140 @@ +/* The head-file for the Shark + * by Alexander Schulz + * + * Does the following: + * - get the memory layout from firmware. This can only be done as long as the mmu + * is still on. + * - switch the mmu off, so we have physical addresses + * - copy the kernel to 0x08508000. This is done to have a fixed address where the + * C-parts (misc.c) are executed. This address must be known at compile-time, + * but the load-address of the kernel depends on how much memory is installed. + * - Jump to this location. + * - Set r8 with 0, r7 with the architecture ID for head.S + */ + +#include <linux/linkage.h> + +#include <asm/assembler.h> + + .section ".start", "ax" + + .arch armv4 + b __beginning + +__ofw_data: .long 0 @ the number of memory blocks + .space 128 @ (startaddr,size) ... + .space 128 @ bootargs + .align + +__beginning: mov r4, r0 @ save the entry to the firmware + + mov r0, #0xC0 @ disable irq and fiq + mov r1, r0 + mrs r3, cpsr + bic r2, r3, r0 + eor r2, r2, r1 + msr cpsr_c, r2 + + mov r0, r4 @ get the Memory layout from firmware + adr r1, __ofw_data + add r2, r1, #4 + mov lr, pc + b ofw_init + mov r1, #0 + + adr r2, __mmu_off @ calculate physical address + sub r2, r2, #0xf0000000 @ openprom maps us at f000 virt, 0e50 phys + adr r0, __ofw_data + ldr r0, [r0, #4] + add r2, r2, r0 + add r2, r2, #0x00500000 + + mrc p15, 0, r3, c1, c0 + bic r3, r3, #0xC @ Write Buffer and DCache + bic r3, r3, #0x1000 @ ICache + mcr p15, 0, r3, c1, c0 @ disabled + + mov r0, #0 + mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 + mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4 + + bic r3, r3, #0x1 @ MMU + mcr p15, 0, r3, c1, c0 @ disabled + + mov pc, r2 + +__copy_target: .long 0x08507FFC +__copy_end: .long 0x08607FFC + + .word _start + .word __bss_start + + .align +__temp_stack: .space 128 + +__mmu_off: + adr r0, __ofw_data @ read the 1. entry of the memory map + ldr r0, [r0, #4] + orr r0, r0, #0x00600000 + sub r0, r0, #4 + + ldr r1, __copy_end + ldr r3, __copy_target + +/* r0 = 0x0e600000 (current end of kernelcode) + * r3 = 0x08508000 (where it should begin) + * r1 = 0x08608000 (end of copying area, 1MB) + * The kernel is compressed, so 1 MB should be enough. + * copy the kernel to the beginning of physical memory + * We start from the highest address, so we can copy + * from 0x08500000 to 0x08508000 if we have only 8MB + */ + +/* As we get more 2.6-kernels it gets more and more + * uncomfortable to be bound to kernel images of 1MB only. + * So we add a loop here, to be able to copy some more. + * Alexander Schulz 2005-07-17 + */ + + mov r4, #3 @ How many megabytes to copy + + +__MoveCode: sub r4, r4, #1 + +__Copy: ldr r2, [r0], #-4 + str r2, [r1], #-4 + teq r1, r3 + bne __Copy + + /* The firmware maps us in blocks of 1 MB, the next block is + _below_ the last one. So our decrementing source pointer + ist right here, but the destination pointer must be increased + by 2 MB */ + add r1, r1, #0x00200000 + add r3, r3, #0x00100000 + + teq r4, #0 + bne __MoveCode + + + /* and jump to it */ + adr r2, __go_on @ where we want to jump + adr r0, __ofw_data @ read the 1. entry of the memory map + ldr r0, [r0, #4] + sub r2, r2, r0 @ we are mapped add 0e50 now, sub that (-0e00) + sub r2, r2, #0x00500000 @ -0050 + ldr r0, __copy_target @ and add 0850 8000 instead + add r0, r0, #4 + add r2, r2, r0 + mov pc, r2 @ and jump there + +__go_on: + adr sp, __temp_stack + add sp, sp, #128 + adr r0, __ofw_data + mov lr, pc + b create_params + + mov r8, #0 + mov r7, #15 diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 066b034..75189f1 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -135,7 +135,6 @@ start: .word _edata @ zImage end address THUMB( .thumb ) 1: - ARM_BE8( setend be ) @ go BE8 if compiled for BE8 mrs r9, cpsr #ifdef CONFIG_ARM_VIRT_EXT bl __hyp_stub_install @ get into SVC mode, reversibly @@ -700,7 +699,9 @@ __armv4_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x0030 - ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r0, r0, #1 << 25 @ big-endian page tables +#endif bl __common_mmu_cache_on mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs @@ -727,7 +728,9 @@ __armv7_mmu_cache_on: orr r0, r0, #1 << 22 @ U (v6 unaligned access model) @ (needed for ARM1176) #ifdef CONFIG_MMU - ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r0, r0, #1 << 25 @ big-endian page tables +#endif mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client diff --git a/arch/arm/boot/compressed/ofw-shark.c b/arch/arm/boot/compressed/ofw-shark.c new file mode 100644 index 0000000..465c54b --- /dev/null +++ b/arch/arm/boot/compressed/ofw-shark.c @@ -0,0 +1,260 @@ +/* + * linux/arch/arm/boot/compressed/ofw-shark.c + * + * by Alexander Schulz + * + * This file is used to get some basic information + * about the memory layout of the shark we are running + * on. Memory is usually divided in blocks a 8 MB. + * And bootargs are copied from OpenFirmware. + */ + + +#include <linux/kernel.h> +#include <linux/types.h> +#include <asm/setup.h> +#include <asm/page.h> + + +asmlinkage void +create_params (unsigned long *buffer) +{ + /* Is there a better address? Also change in mach-shark/core.c */ + struct tag *tag = (struct tag *) 0x08003000; + int j,i,m,k,nr_banks,size; + unsigned char *c; + + k = 0; + + /* Head of the taglist */ + tag->hdr.tag = ATAG_CORE; + tag->hdr.size = tag_size(tag_core); + tag->u.core.flags = 1; + tag->u.core.pagesize = PAGE_SIZE; + tag->u.core.rootdev = 0; + + /* Build up one tagged block for each memory region */ + size=0; + nr_banks=(unsigned int) buffer[0]; + for (j=0;j<nr_banks;j++){ + /* search the lowest address and put it into the next entry */ + /* not a fast sort algorithm, but there are at most 8 entries */ + /* and this is used only once anyway */ + m=0xffffffff; + for (i=0;i<(unsigned int) buffer[0];i++){ + if (buffer[2*i+1]<m) { + m=buffer[2*i+1]; + k=i; + } + } + + tag = tag_next(tag); + tag->hdr.tag = ATAG_MEM; + tag->hdr.size = tag_size(tag_mem32); + tag->u.mem.size = buffer[2*k+2]; + tag->u.mem.start = buffer[2*k+1]; + + size += buffer[2*k+2]; + + buffer[2*k+1]=0xffffffff; /* mark as copied */ + } + + /* The command line */ + tag = tag_next(tag); + tag->hdr.tag = ATAG_CMDLINE; + + c=(unsigned char *)(&buffer[34]); + j=0; + while (*c) tag->u.cmdline.cmdline[j++]=*c++; + + tag->u.cmdline.cmdline[j]=0; + tag->hdr.size = (j + 7 + sizeof(struct tag_header)) >> 2; + + /* Hardware revision */ + tag = tag_next(tag); + tag->hdr.tag = ATAG_REVISION; + tag->hdr.size = tag_size(tag_revision); + tag->u.revision.rev = ((unsigned char) buffer[33])-'0'; + + /* End of the taglist */ + tag = tag_next(tag); + tag->hdr.tag = 0; + tag->hdr.size = 0; +} + + +typedef int (*ofw_handle_t)(void *); + +/* Everything below is called with a wrong MMU setting. + * This means: no string constants, no initialization of + * arrays, no global variables! This is ugly but I didn't + * want to write this in assembler :-) + */ + +int +of_decode_int(const unsigned char *p) +{ + unsigned int i = *p++ << 8; + i = (i + *p++) << 8; + i = (i + *p++) << 8; + return (i + *p); +} + +int +OF_finddevice(ofw_handle_t openfirmware, char *name) +{ + unsigned int args[8]; + char service[12]; + + service[0]='f'; + service[1]='i'; + service[2]='n'; + service[3]='d'; + service[4]='d'; + service[5]='e'; + service[6]='v'; + service[7]='i'; + service[8]='c'; + service[9]='e'; + service[10]='\0'; + + args[0]=(unsigned int)service; + args[1]=1; + args[2]=1; + args[3]=(unsigned int)name; + + if (openfirmware(args) == -1) + return -1; + return args[4]; +} + +int +OF_getproplen(ofw_handle_t openfirmware, int handle, char *prop) +{ + unsigned int args[8]; + char service[12]; + + service[0]='g'; + service[1]='e'; + service[2]='t'; + service[3]='p'; + service[4]='r'; + service[5]='o'; + service[6]='p'; + service[7]='l'; + service[8]='e'; + service[9]='n'; + service[10]='\0'; + + args[0] = (unsigned int)service; + args[1] = 2; + args[2] = 1; + args[3] = (unsigned int)handle; + args[4] = (unsigned int)prop; + + if (openfirmware(args) == -1) + return -1; + return args[5]; +} + +int +OF_getprop(ofw_handle_t openfirmware, int handle, char *prop, void *buf, unsigned int buflen) +{ + unsigned int args[8]; + char service[8]; + + service[0]='g'; + service[1]='e'; + service[2]='t'; + service[3]='p'; + service[4]='r'; + service[5]='o'; + service[6]='p'; + service[7]='\0'; + + args[0] = (unsigned int)service; + args[1] = 4; + args[2] = 1; + args[3] = (unsigned int)handle; + args[4] = (unsigned int)prop; + args[5] = (unsigned int)buf; + args[6] = buflen; + + if (openfirmware(args) == -1) + return -1; + return args[7]; +} + +asmlinkage void ofw_init(ofw_handle_t o, int *nomr, int *pointer) +{ + int phandle,i,mem_len,buffer[32]; + char temp[15]; + + temp[0]='/'; + temp[1]='m'; + temp[2]='e'; + temp[3]='m'; + temp[4]='o'; + temp[5]='r'; + temp[6]='y'; + temp[7]='\0'; + + phandle=OF_finddevice(o,temp); + + temp[0]='r'; + temp[1]='e'; + temp[2]='g'; + temp[3]='\0'; + + mem_len = OF_getproplen(o,phandle, temp); + OF_getprop(o,phandle, temp, buffer, mem_len); + *nomr=mem_len >> 3; + + for (i=0; i<=mem_len/4; i++) pointer[i]=of_decode_int((const unsigned char *)&buffer[i]); + + temp[0]='/'; + temp[1]='c'; + temp[2]='h'; + temp[3]='o'; + temp[4]='s'; + temp[5]='e'; + temp[6]='n'; + temp[7]='\0'; + + phandle=OF_finddevice(o,temp); + + temp[0]='b'; + temp[1]='o'; + temp[2]='o'; + temp[3]='t'; + temp[4]='a'; + temp[5]='r'; + temp[6]='g'; + temp[7]='s'; + temp[8]='\0'; + + mem_len = OF_getproplen(o,phandle, temp); + OF_getprop(o,phandle, temp, buffer, mem_len); + if (mem_len > 128) mem_len=128; + for (i=0; i<=mem_len/4; i++) pointer[i+33]=buffer[i]; + pointer[i+33]=0; + + temp[0]='/'; + temp[1]='\0'; + phandle=OF_finddevice(o,temp); + temp[0]='b'; + temp[1]='a'; + temp[2]='n'; + temp[3]='n'; + temp[4]='e'; + temp[5]='r'; + temp[6]='-'; + temp[7]='n'; + temp[8]='a'; + temp[9]='m'; + temp[10]='e'; + temp[11]='\0'; + mem_len = OF_getproplen(o,phandle, temp); + OF_getprop(o,phandle, temp, buffer, mem_len); + * ((unsigned char *) &pointer[32]) = ((unsigned char *) buffer)[mem_len-2]; +} diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..802720e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -40,17 +40,17 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb + dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb -dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ +dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \ bcm28155-ap.dtb -dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ dove-d2plug.dtb \ - dove-d3plug.dtb \ dove-dove-db.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ @@ -96,25 +96,22 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ kirkwood-nsa310a.dtb \ - kirkwood-openblocks_a6.dtb \ - kirkwood-openblocks_a7.dtb \ kirkwood-sheevaplug.dtb \ kirkwood-sheevaplug-esata.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ - kirkwood-ts219-6282.dtb + kirkwood-ts219-6282.dtb \ + kirkwood-openblocks_a6.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb -dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb +dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ + msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-370-mirabox.dtb \ armada-370-netgear-rn102.dtb \ - armada-370-netgear-rn104.dtb \ armada-370-rd.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ - armada-xp-matrix.dtb \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += \ imx25-karo-tx25.dtb \ @@ -145,10 +142,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-sbc6x.dtb \ - imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6sl-evk.dtb \ - vf610-cosmic.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ @@ -164,7 +159,6 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-cfa10057.dtb \ imx28-cfa10058.dtb \ imx28-evk.dtb \ - imx28-m28cu3.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb @@ -178,15 +172,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap3-devkit8000.dtb \ omap3-beagle-xm.dtb \ omap3-evm.dtb \ - omap3-evm-37xx.dtb \ - omap3-n900.dtb \ - omap3-n9.dtb \ - omap3-n950.dtb \ omap3-tobi.dtb \ - omap3-gta04.dtb \ omap3-igep0020.dtb \ omap3-igep0030.dtb \ - omap3-zoom3.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ @@ -198,33 +186,25 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am335x-evmsk.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ - am335x-nano.dtb \ - am335x-base0033.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ - am43x-epos-evm.dtb \ - dra7-evm.dtb + am43x-epos-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ - ste-hrefprev60-stuib.dtb \ - ste-hrefprev60-tvk.dtb \ - ste-hrefv60plus-stuib.dtb \ - ste-hrefv60plus-tvk.dtb \ + ste-hrefprev60.dtb \ + ste-hrefv60plus.dtb \ ste-ccu8540.dtb \ ste-ccu9540.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb -dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ - s3c6410-smdk6410.dtb dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ - r7s72100-genmai.dtb \ + emev2-kzm9d-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ r8a7740-armadillo800eva-reference.dtb \ r8a7779-marzen.dtb \ r8a7779-marzen-reference.dtb \ - r8a7791-koelsch.dtb \ r8a7790-lager.dtb \ r8a7790-lager-reference.dtb \ sh73a0-kzm9g.dtb \ @@ -232,10 +212,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a73a4-ape6evm.dtb \ r8a73a4-ape6evm-reference.dtb \ sh7372-mackerel.dtb -dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb -dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ - socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_sockit.dtb \ +dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb @@ -257,7 +235,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a13-olinuxino.dtb \ sun6i-a31-colombus.dtb \ sun7i-a20-cubieboard2.dtb \ - sun7i-a20-cubietruck.dtb \ sun7i-a20-olinuxino-micro.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ @@ -272,8 +249,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ - tegra114-dalmore.dtb \ - tegra124-venice2.dtb + tegra114-dalmore.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts deleted file mode 100644 index 72a9b3f..0000000 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "am335x-igep0033.dtsi" - -/ { - model = "IGEP COM AM335x on AQUILA Expansion"; - compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_pins>; - pinctrl-1 = <&nxp_hdmi_off_pins>; - status = "okay"; - }; - - leds_base { - pinctrl-names = "default"; - pinctrl-0 = <&leds_base_pins>; - - compatible = "gpio-leds"; - - led@0 { - label = "base:red:user"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ - default-state = "off"; - }; - - led@1 { - label = "base:green:user"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - nxp_hdmi_pins: pinmux_nxp_hdmi_pins { - pinctrl-single,pins = < - 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ - 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */ - 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */ - 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */ - 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */ - 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */ - 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */ - 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */ - 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */ - 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */ - 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */ - 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */ - 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */ - 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */ - 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */ - 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */ - 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */ - 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */ - 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */ - 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */ - 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */ - >; - }; - nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { - pinctrl-single,pins = < - 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ - >; - }; - - leds_base_pins: pinmux_leds_base_pins { - pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index e3f27ec..2f66ded 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -21,205 +21,177 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - leds { + am33xx_pinmux: pinmux@44e10800 { pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; - led@2 { - label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; }; - led@3 { - label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; }; - led@4 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; }; - led@5 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; }; - }; - vmmcsd_fixed: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ - >; - }; + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; }; - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; + ocp { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; + status = "okay"; + }; - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ - >; - }; + musb: usb@47400000 { + status = "okay"; - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; + control@44e10000 { + status = "okay"; + }; - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; + usb-phy@47401300 { + status = "okay"; + }; - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; + usb-phy@47401b00 { + status = "okay"; + }; - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ - >; - }; + usb@47401000 { + status = "okay"; + }; - emmc_pins: pinmux_emmc_pins { - pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -}; + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; + dma-controller@07402000 { + status = "okay"; + }; + }; - status = "okay"; -}; + i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; -&usb { - status = "okay"; + status = "okay"; + clock-frequency = <400000>; - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; + tps: tps@24 { + reg = <0x24>; + }; - usb-phy@47401b00 { - status = "okay"; + }; }; - usb@47401000 { - status = "okay"; - }; + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; + compatible = "gpio-leds"; - dma-controller@07402000 { - status = "okay"; - }; -}; + led@2 { + label = "beaglebone:green:heartbeat"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; + led@3 { + label = "beaglebone:green:mmc0"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; - status = "okay"; - clock-frequency = <400000>; + led@4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; - tps: tps@24 { - reg = <0x24>; + led@5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; }; - }; /include/ "tps65217.dtsi" @@ -288,12 +260,3 @@ pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; }; - -&mmc1 { - status = "okay"; - bus-width = <0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - cd-inverted; -}; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 94ee427..7993c48 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -9,21 +9,3 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&ldo3_reg>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 6b71ad9..197cadf 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -15,64 +15,3 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; - -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins>; - bus-width = <8>; - status = "okay"; - ti,vcc-aux-disable-is-sleep; -}; - -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { - pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ - 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - >; - }; - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { - pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -/ { - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 7e6c64e..e8ec875 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -24,6 +24,324 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; + + matrix_keypad_s0: matrix_keypad_s0 { + pinctrl-single,pins = < + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + >; + }; + + volume_keys_s0: volume_keys_s0 { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ + 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + }; + + ocp { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; + }; + + i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + }; + + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; + }; + + i2c1: i2c@4802a000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <100000>; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + + tsl2550: tsl2550@39 { + compatible = "taos,tsl2550"; + reg = <0x39>; + }; + + tmp275: tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + }; + + elm: elm@48080000 { + status = "okay"; + }; + + epwmss0: epwmss@48300000 { + status = "okay"; + + ecap0: ecap@48300100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; + }; + }; + + gpmc: gpmc@50000000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + /* MTD partition table */ + partition@0 { + label = "SPL1"; + reg = <0x00000000 0x000020000>; + }; + + partition@1 { + label = "SPL2"; + reg = <0x00020000 0x00020000>; + }; + + partition@2 { + label = "SPL3"; + reg = <0x00040000 0x00020000>; + }; + + partition@3 { + label = "SPL4"; + reg = <0x00060000 0x00020000>; + }; + + partition@4 { + label = "U-boot"; + reg = <0x00080000 0x001e0000>; + }; + + partition@5 { + label = "environment"; + reg = <0x00260000 0x00020000>; + }; + + partition@6 { + label = "Kernel"; + reg = <0x00280000 0x00500000>; + }; + + partition@7 { + label = "File-System"; + reg = <0x00780000 0x0F880000>; + }; + }; + }; + }; + vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -85,447 +403,10 @@ brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; - - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - 800x480p62 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - - sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-EVM"; - ti,audio-codec = <&tlv320aic3106>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - - matrix_keypad_s0: matrix_keypad_s0 { - pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - volume_keys_s0: volume_keys_s0 { - pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - lcd_pins_s0: lcd_pins_s0 { - pinctrl-single,pins = < - 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ - 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ - 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ - 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ - 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ - 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ - 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ - 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ - 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ - 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ - 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ - 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ - 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ - 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ - 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ - 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ - 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ - 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ - 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ - 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ - 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ - 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ - 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ - 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ - 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ - 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ - 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ - 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ - >; - }; - - am335x_evm_audio_pins: am335x_evm_audio_pins { - pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */ - 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&usb { - status = "okay"; - - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; - - usb-phy@47401b00 { - status = "okay"; - }; - - usb@47401000 { - status = "okay"; - }; - - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; - - dma-controller@07402000 { - status = "okay"; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tsl2550: tsl2550@39 { - compatible = "taos,tsl2550"; - reg = <0x39>; - }; - - tmp275: tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tlv320aic3106: tlv320aic3106@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vaux2_reg>; - IOVDD-supply = <&vaux2_reg>; - DRVDD-supply = <&vaux2_reg>; - DVDD-supply = <&vbat>; - }; -}; - -&lcdc { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: ecap@48300100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - elm_id = <&elm>; - - /* MTD partition table */ - partition@0 { - label = "SPL1"; - reg = <0x00000000 0x000020000>; - }; - - partition@1 { - label = "SPL2"; - reg = <0x00020000 0x00020000>; - }; - - partition@2 { - label = "SPL3"; - reg = <0x00040000 0x00020000>; - }; - - partition@3 { - label = "SPL4"; - reg = <0x00060000 0x00020000>; - }; - - partition@4 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; - - partition@5 { - label = "environment"; - reg = <0x00260000 0x00020000>; - }; - - partition@6 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; - - partition@7 { - label = "File-System"; - reg = <0x00780000 0x0F880000>; - }; - }; }; #include "tps65910.dtsi" -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&am335x_evm_audio_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; @@ -596,8 +477,6 @@ }; vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; regulator-always-on; }; }; @@ -630,7 +509,7 @@ tsc { ti,wires = <4>; ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; + ti,coordiante-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; }; @@ -638,17 +517,3 @@ ti,adc-channels = <4 5 6 7>; }; }; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 4718ec4..4f339fa 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -31,6 +31,210 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; + am33xx_pinmux: pinmux@44e10800 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + >; + }; + + gpio_keys_s0: gpio_keys_s0 { + pinctrl-single,pins = < + 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + ecap2_pins: backlight_pins { + pinctrl-single,pins = < + 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + }; + + ocp { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; + }; + + i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + }; + + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + }; + }; + + epwmss2: epwmss@48304000 { + status = "okay"; + + ecap2: ecap@48304100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + }; + }; + }; + vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -115,240 +319,6 @@ brightness-levels = <0 58 61 66 75 90 125 170 255>; default-brightness-level = <8>; }; - - sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-EVMSK"; - ti,audio-codec = <&tlv320aic3106>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <24576000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - >; - }; - - gpio_keys_s0: gpio_keys_s0 { - pinctrl-single,pins = < - 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - ecap2_pins: backlight_pins { - pinctrl-single,pins = < - 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - - /* Slave 2 */ - 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value*/ - 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tlv320aic3106: tlv320aic3106@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vaux2_reg>; - IOVDD-supply = <&vaux2_reg>; - DRVDD-supply = <&vaux2_reg>; - DVDD-supply = <&vbat>; - }; -}; - -&usb { - status = "okay"; - - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; - - usb@47401000 { - status = "okay"; - }; -}; - -&epwmss2 { - status = "okay"; - - ecap2: ecap@48304100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - }; }; #include "tps65910.dtsi" @@ -423,8 +393,6 @@ }; vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; regulator-always-on; }; }; @@ -451,47 +419,3 @@ phy_id = <&davinci_mdio>, <1>; phy-mode = "rgmii-txid"; }; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp1_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <1>; - rx-num-evt = <1>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; -}; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi deleted file mode 100644 index 7063311..0000000 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ /dev/null @@ -1,307 +0,0 @@ -/* - * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x - * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - compatible = "gpio-leds"; - - led@0 { - label = "com:green:user"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - vbat: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vmmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - nandflash_pins: pinmux_nandflash_pins { - pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - >; - }; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins>; - - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - - nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - elm_id = <&elm>; - - /* MTD partition table */ - partition@0 { - label = "SPL"; - reg = <0x00000000 0x000080000>; - }; - - partition@1 { - label = "U-boot"; - reg = <0x00080000 0x001e0000>; - }; - - partition@2 { - label = "U-Boot Env"; - reg = <0x00260000 0x00020000>; - }; - - partition@3 { - label = "Kernel"; - reg = <0x00280000 0x00500000>; - }; - - partition@4 { - label = "File System"; - reg = <0x00780000 0x007880000>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc>; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&usb { - status = "okay"; - - control@44e10000 { - status = "okay"; - }; - - usb-phy@47401300 { - status = "okay"; - }; - - usb-phy@47401b00 { - status = "okay"; - }; - - usb@47401000 { - status = "okay"; - }; - - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; - - dma-controller@07402000 { - status = "okay"; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-always-on; - }; - }; -}; - diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts deleted file mode 100644 index 9907b49..0000000 --- a/arch/arm/boot/dts/am335x-nano.dts +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "Newflow AM335x NanoBone"; - compatible = "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&dcdc2_reg>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - led@0 { - label = "nanobone:green:usr1"; - gpios = <&gpio1 5 0>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&misc_pins>; - - misc_pins: misc_pins { - pinctrl-single,pins = < - 0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */ - >; - }; - - gpmc_pins: gpmc_pins { - pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ - 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ - 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ - 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ - 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ - 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ - 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ - 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ - - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */ - 0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */ - 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */ - - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */ - - 0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */ - 0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */ - 0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */ - 0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */ - 0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */ - 0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */ - 0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */ - - 0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */ - 0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */ - 0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */ - >; - }; - - i2c0_pins: i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - uart0_pins: uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - uart1_pins: uart1_pins { - pinctrl-single,pins = < - 0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ - 0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ - 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - 0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ - >; - }; - - uart2_pins: uart2_pins { - pinctrl-single,pins = < - 0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */ - 0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */ - 0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ - 0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; - - uart3_pins: uart3_pins { - pinctrl-single,pins = < - 0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */ - 0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */ - 0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */ - 0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ - >; - }; - - uart4_pins: uart4_pins { - pinctrl-single,pins = < - 0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */ - 0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */ - 0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */ - 0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */ - >; - }; - - uart5_pins: uart5_pins { - pinctrl-single,pins = < - 0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */ - 0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */ - >; - }; - - mmc1_pins: mmc1_pins { - pinctrl-single,pins = < - 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ - 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rx-during-tx; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; - rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; - rs485-rts-delay = <1 1>; - linux,rs485-enabled-at-boot-time; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - gpio@20 { - compatible = "mcp,mcp23017"; - reg = <0x20>; - }; - - tps: tps@24 { - reg = <0x24>; - }; - - eeprom@53 { - compatible = "mcp,24c02"; - reg = <0x53>; - pagesize = <8>; - }; - - rtc@68 { - compatible = "dallas,ds1307"; - reg = <0x68>; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - status = "okay"; - gpmc,num-waitpins = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmc_pins>; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */ - - nor@0,0 { - reg = <0 0x00000000 0x08000000>; - compatible = "cfi-flash"; - linux,mtd-name = "spansion,s29gl010p11t"; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <10>; - gpmc,adv-rd-off-ns = <30>; - gpmc,adv-wr-off-ns = <30>; - gpmc,oe-on-ns = <40>; - gpmc,oe-off-ns = <160>; - gpmc,we-on-ns = <40>; - gpmc,we-off-ns = <160>; - gpmc,rd-cycle-ns = <160>; - gpmc,wr-cycle-ns = <160>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-delay-ns = <20>; - gpmc,wr-data-mux-bus-ns = <70>; - gpmc,wr-access-ns = <80>; - - #address-cells = <1>; - #size-cells = <1>; - - /* - MTD partition table - =================== - +------------+-->0x00000000-> U-Boot start - | | - | |-->0x000BFFFF-> U-Boot end - | |-->0x000C0000-> ENV1 start - | | - | |-->0x000DFFFF-> ENV1 end - | |-->0x000E0000-> ENV2 start - | | - | |-->0x000FFFFF-> ENV2 end - | |-->0x00100000-> Kernel start - | | - | |-->0x004FFFFF-> Kernel end - | |-->0x00500000-> File system start - | | - | |-->0x014FFFFF-> File system end - | |-->0x01500000-> User data start - | | - | |-->0x03FFFFFF-> User data end - | |-->0x04000000-> Data storage start - | | - +------------+-->0x08000000-> NOR end (Free end) - */ - partition@0 { - label = "boot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@1 { - label = "env1"; - reg = <0x000c0000 0x00020000>; /* 128KB */ - }; - - partition@2 { - label = "env2"; - reg = <0x000e0000 0x00020000>; /* 128KB */ - }; - - partition@3 { - label = "kernel"; - reg = <0x00100000 0x00400000>; /* 4MB */ - }; - - partition@4 { - label = "rootfs"; - reg = <0x00500000 0x01000000>; /* 16MB */ - }; - - partition@5 { - label = "user"; - reg = <0x01500000 0x02b00000>; /* 43MB */ - }; - - partition@6 { - label = "data"; - reg = <0x04000000 0x04000000>; /* 64MB */ - }; - }; -}; - -&mac { - dual_emac = <1>; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&ldo4_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - bus-width = <4>; - cd-gpios = <&gpio3 8 0>; - wp-gpios = <&gpio3 18 0>; -}; - -#include "tps65217.dtsi" - -&tps { - regulators { - dcdc1_reg: regulator@0 { - /* +1.5V voltage with ±4% tolerance */ - regulator-min-microvolt = <1450000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: regulator@1 { - /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: regulator@2 { - /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <915000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: regulator@3 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: regulator@4 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: regulator@5 { - /* +1.8V voltage with ±4% tolerance */ - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1870000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: regulator@6 { - /* +3.3V voltage with ±4% tolerance */ - regulator-min-microvolt = <3175000>; - regulator-max-microvolt = <3430000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6d8ffe..f9c5da9 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -18,9 +18,6 @@ interrupt-parent = <&intc>; aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -33,8 +30,6 @@ usb1 = &usb1; phy0 = &usb0_phy; phy1 = &usb1_phy; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; }; cpus { @@ -62,11 +57,6 @@ }; }; - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -110,25 +100,13 @@ reg = <0x48200000 0x1000>; }; - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x10>; - interrupts = <12 13 14>; - #dma-cells = <1>; - dma-channels = <64>; - ti,edma-regions = <4>; - ti,edma-slots = <256>; - }; - gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; reg = <0x44e07000 0x1000>; interrupts = <96>; }; @@ -139,7 +117,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; reg = <0x4804c000 0x1000>; interrupts = <98>; }; @@ -150,7 +128,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; reg = <0x481ac000 0x1000>; interrupts = <32>; }; @@ -161,7 +139,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; reg = <0x481ae000 0x1000>; interrupts = <62>; }; @@ -250,50 +228,6 @@ status = "disabled"; }; - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - ti,needs-special-hs-handling; - dmas = <&edma 24 - &edma 25>; - dma-names = "tx", "rx"; - interrupts = <64>; - interrupt-parent = <&intc>; - reg = <0x48060000 0x1000>; - status = "disabled"; - }; - - mmc2: mmc@481d8000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; - dma-names = "tx", "rx"; - interrupts = <28>; - interrupt-parent = <&intc>; - reg = <0x481d8000 0x1000>; - status = "disabled"; - }; - - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - interrupts = <29>; - interrupt-parent = <&intc>; - reg = <0x47810000 0x1000>; - status = "disabled"; - }; - - hwspinlock: spinlock@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x1000>; - ti,hwmods = "spinlock"; - }; - wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; @@ -389,11 +323,6 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; - dmas = <&edma 16 - &edma 17 - &edma 18 - &edma 19>; - dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -405,11 +334,6 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; - dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -422,7 +346,7 @@ ti,hwmods = "usb_otg_hs"; status = "disabled"; - usb_ctrl_mod: control@44e10000 { + ctrl_mod: control@44e10000 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; @@ -435,7 +359,7 @@ reg = <0x47401300 0x100>; reg-names = "phy"; status = "disabled"; - ti,ctrl_mod = <&usb_ctrl_mod>; + ti,ctrl_mod = <&ctrl_mod>; }; usb0: usb@47401000 { @@ -483,7 +407,7 @@ reg = <0x47401b00 0x100>; reg-names = "phy"; status = "disabled"; - ti,ctrl_mod = <&usb_ctrl_mod>; + ti,ctrl_mod = <&ctrl_mod>; }; usb1: usb@47401800 { @@ -670,12 +594,6 @@ /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - }; }; ocmcram: ocmcram@40300000 { @@ -689,7 +607,6 @@ reg = <0x44d00000 0x4000 /* M3 UMEM */ 0x44d80000 0x2000>; /* M3 DMEM */ ti,hwmods = "wkup_m3"; - ti,no-reset-on-init; }; elm: elm@48080000 { @@ -700,15 +617,6 @@ status = "disabled"; }; - lcdc: lcdc@4830e000 { - compatible = "ti,am33xx-tilcdc"; - reg = <0x4830e000 0x1000>; - interrupt-parent = <&intc>; - interrupts = <36>; - ti,hwmods = "lcdc"; - status = "disabled"; - }; - tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; reg = <0x44e0d000 0x1000>; @@ -729,7 +637,6 @@ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; - ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; gpmc,num-cs = <7>; @@ -738,59 +645,5 @@ #size-cells = <1>; status = "disabled"; }; - - sham: sham@53100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - dmas = <&edma 36>; - dma-names = "rx"; - }; - - aes: aes@53500000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53500000 0xa0>; - interrupts = <103>; - dmas = <&edma 6>, - <&edma 5>; - dma-names = "tx", "rx"; - }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupts-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803C000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupts-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; - dma-names = "tx", "rx"; - }; - - rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = <111>; - }; }; }; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 974d103..ddc1df7 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -18,21 +18,12 @@ aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; serial0 = &uart0; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; }; cpus { - #address-cells = <1>; - #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; }; }; @@ -44,100 +35,16 @@ <0x48240100 0x0100>; }; - l2-cache-controller@48242000 { - compatible = "arm,pl310-cache"; - reg = <0x48242000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - am43xx_pinmux: pinmux@44e10800 { - compatible = "pinctrl-single"; - reg = <0x44e10800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - ti,hwmods = "l3_main"; - - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x10>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <64>; - ti,edma-regions = <4>; - ti,edma-slots = <256>; - }; uart0: serial@44e09000 { compatible = "ti,am4372-uart","ti,omap2-uart"; reg = <0x44e09000 0x2000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - }; - - uart1: serial@48022000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x48022000 0x2000>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart2"; - status = "disabled"; - }; - - uart2: serial@48024000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x48024000 0x2000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart3"; - status = "disabled"; - }; - - uart3: serial@481a6000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481a6000 0x2000>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart4"; - status = "disabled"; - }; - - uart4: serial@481a8000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481a8000 0x2000>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart5"; - status = "disabled"; - }; - - uart5: serial@481aa000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481aa000 0x2000>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart6"; - status = "disabled"; - }; - - mailbox: mailbox@480C8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mailbox"; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - ti,mbox-names = "wkup_m3"; - ti,mbox-data = <0 0 0 0>; - status = "disabled"; }; timer1: timer@44e31000 { @@ -145,523 +52,17 @@ reg = <0x44e31000 0x400>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,timer-alwon; - ti,hwmods = "timer1"; }; timer2: timer@48040000 { compatible = "ti,am4372-timer","ti,am335x-timer"; reg = <0x48040000 0x400>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48042000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48042000 0x400>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer3"; - status = "disabled"; - }; - - timer4: timer@48044000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48044000 0x400>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - ti,hwmods = "timer4"; - status = "disabled"; - }; - - timer5: timer@48046000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48046000 0x400>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - ti,hwmods = "timer5"; - status = "disabled"; - }; - - timer6: timer@48048000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48048000 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - ti,hwmods = "timer6"; - status = "disabled"; - }; - - timer7: timer@4804a000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4804a000 0x400>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - ti,hwmods = "timer7"; - status = "disabled"; - }; - - timer8: timer@481c1000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x481c1000 0x400>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer8"; - status = "disabled"; - }; - - timer9: timer@4833d000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4833d000 0x400>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer9"; - status = "disabled"; - }; - - timer10: timer@4833f000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4833f000 0x400>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer10"; - status = "disabled"; - }; - - timer11: timer@48341000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48341000 0x400>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer11"; - status = "disabled"; }; counter32k: counter@44e86000 { compatible = "ti,am4372-counter32k","ti,omap-counter32k"; reg = <0x44e86000 0x40>; - ti,hwmods = "counter_32k"; - }; - - rtc@44e3e000 { - compatible = "ti,am4372-rtc","ti,da830-rtc"; - reg = <0x44e3e000 0x1000>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "rtc"; - status = "disabled"; - }; - - wdt@44e35000 { - compatible = "ti,am4372-wdt","ti,omap3-wdt"; - reg = <0x44e35000 0x1000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "wd_timer2"; - }; - - gpio0: gpio@44e07000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x44e07000 0x1000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio1"; - status = "disabled"; - }; - - gpio1: gpio@4804c000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x4804c000 0x1000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio2"; - status = "disabled"; - }; - - gpio2: gpio@481ac000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x481ac000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio3"; - status = "disabled"; - }; - - gpio3: gpio@481ae000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x481ae000 0x1000>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio4"; - status = "disabled"; - }; - - gpio4: gpio@48320000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x48320000 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio5"; - status = "disabled"; - }; - - gpio5: gpio@48322000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x48322000 0x1000>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio6"; - status = "disabled"; - }; - - i2c0: i2c@44e0b000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x44e0b000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "i2c1"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@4802a000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x4802a000 0x1000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "i2c2"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@4819c000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x4819c000 0x1000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "i2c3"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@48030000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x48030000 0x400>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "spi0"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x1000>; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&edma 24 - &edma 25>; - dma-names = "tx", "rx"; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - mmc2: mmc@481d8000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x481d8000 0x1000>; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; - dma-names = "tx", "rx"; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - mmc3: mmc@47810000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x47810000 0x1000>; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - spi1: spi@481a0000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a0000 0x400>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "spi1"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@481a2000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a2000 0x400>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "spi2"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@481a4000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a4000 0x400>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "spi3"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@48345000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x48345000 0x400>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "spi4"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac: ethernet@4a100000 { - compatible = "ti,am4372-cpsw","ti,cpsw"; - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "cpgmac0"; - status = "disabled"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - no_bd_ram = <0>; - rx_descs = <64>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - ranges; - - davinci_mdio: mdio@4a101000 { - compatible = "ti,am4372-mdio","ti,davinci_mdio"; - reg = <0x4a101000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - epwmss0: epwmss@48300000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss0"; - status = "disabled"; - - ecap0: ecap@48300100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; - reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; - status = "disabled"; - }; - - ehrpwm0: ehrpwm@48300200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; - reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48302000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48302000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss1"; - status = "disabled"; - - ecap1: ecap@48302100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; - reg = <0x48302100 0x80>; - ti,hwmods = "ecap1"; - status = "disabled"; - }; - - ehrpwm1: ehrpwm@48302200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; - reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48304000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48304000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss2"; - status = "disabled"; - - ecap2: ecap@48304100 { - compatible = "ti,am4372-ecap","ti,am33xx-ecap"; - reg = <0x48304100 0x80>; - ti,hwmods = "ecap2"; - status = "disabled"; - }; - - ehrpwm2: ehrpwm@48304200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; - reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; - status = "disabled"; - }; - }; - - epwmss3: epwmss@48306000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48306000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss3"; - status = "disabled"; - - ehrpwm3: ehrpwm@48306200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; - reg = <0x48306200 0x80>; - ti,hwmods = "ehrpwm3"; - status = "disabled"; - }; - }; - - epwmss4: epwmss@48308000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48308000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss4"; - status = "disabled"; - - ehrpwm4: ehrpwm@48308200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; - reg = <0x48308200 0x80>; - ti,hwmods = "ehrpwm4"; - status = "disabled"; - }; - }; - - epwmss5: epwmss@4830a000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x4830a000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss5"; - status = "disabled"; - - ehrpwm5: ehrpwm@4830a200 { - compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; - reg = <0x4830a200 0x80>; - ti,hwmods = "ehrpwm5"; - status = "disabled"; - }; - }; - - sham: sham@53100000 { - compatible = "ti,omap5-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x300>; - dmas = <&edma 36>; - dma-names = "rx"; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - }; - - aes: aes@53501000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x53501000 0xa0>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&edma 6 - &edma 5>; - dma-names = "tx", "rx"; - }; - - des: des@53701000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x53701000 0xa0>; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&edma 34 - &edma 33>; - dma-names = "tx", "rx"; - }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupts-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803C000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupts-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; - dma-names = "tx", "rx"; }; }; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index fbf9c4c..74174d4 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -11,176 +11,8 @@ /dts-v1/; #include "am4372.dtsi" -#include <dt-bindings/pinctrl/am43xx.h> -#include <dt-bindings/gpio/gpio.h> / { model = "TI AM43x EPOS EVM"; compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; - - vmmcsd_fixed: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - }; - - am43xx_pinmux: pinmux@44e10800 { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - }; - - matrix_keypad: matrix_keypad@0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ - &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ - &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ - &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ - - col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ - &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ - &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ - &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x01000204 /* P4 */ - 0x02000207 /* P7 */ - 0x0300020a /* NUMERIC_STAR */ - 0x00010202 /* P2 */ - 0x01010205 /* P5 */ - 0x02010208 /* P8 */ - 0x03010200 /* P0 */ - 0x00020203 /* P3 */ - 0x01020206 /* P6 */ - 0x02020209 /* P9 */ - 0x0302020b /* NUMERIC_POUND */ - 0x00030067 /* UP */ - 0x0103006a /* RIGHT */ - 0x0203006c /* DOWN */ - 0x03030069>; /* LEFT */ - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <16>; - phy-mode = "rmii"; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rmii"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - at24@50 { - compatible = "at24,24c256"; - pagesize = <64>; - reg = <0x50>; - }; - - pixcir_ts@5c { - compatible = "pixcir,pixcir_ts"; - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <17 0>; - - attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; - - x-size = <1024>; - y-size = <768>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 08a56bc..90ce29d 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -99,22 +99,22 @@ spi-max-frequency = <50000000>; }; }; - }; - pcie-controller { - status = "okay"; - /* - * The two PCIe units are accessible through - * both standard PCIe slots and mini-PCIe - * slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@2,0 { - /* Port 1, Lane 0 */ + pcie-controller { status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts deleted file mode 100644 index b0b32f5..0000000 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Device Tree file for NETGEAR ReadyNAS 104 - * - * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "armada-370.dtsi" - -/ { - model = "NETGEAR ReadyNAS 104"; - compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ - }; - - soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 - MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; - - pcie-controller { - status = "okay"; - - /* Connected to FL1009 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected to Marvell 88SE9215 SATA controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - - internal-regs { - serial@12000 { - clock-frequency = <200000000>; - status = "okay"; - }; - - pinctrl { - poweroff: poweroff { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - backup_key_pin: backup-key-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - power_key_pin: power-key-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpo"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - reset_key_pin: reset-key-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - }; - - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; - }; - - usb@50000 { - status = "okay"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - clock-frequency = <100000>; - status = "okay"; - - g762: g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; /* input clock */ - fan_gear_mode = <0>; - fan_startv = <1>; - pwm_polarity = <0>; - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&backup_led_pin &power_led_pin>; - pinctrl-names = "default"; - - blue_backup_led { - label = "rn104:blue:backup"; - gpios = <&gpio1 31 0>; /* GPIO 63 Active High */ - default-state = "off"; - }; - - blue_power_led { - label = "rn104:blue:pwr"; - gpios = <&gpio2 0 1>; /* GPIO 64 Active Low */ - linux,default-trigger = "keep"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&backup_key_pin - &power_key_pin - &reset_key_pin>; - pinctrl-names = "default"; - - button@1 { - label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 20 1>; - }; - - button@2 { - label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 30 0>; - }; - - button@3 { - label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio2 1 1>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&poweroff>; - pinctrl-names = "default"; - gpios = <&gpio1 28 1>; - }; -}; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 7f10f62..1de2dae 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -113,12 +113,11 @@ #interrupt-cells = <1>; #size-cells = <1>; interrupt-controller; - msi-controller; }; coherency-fabric@20200 { compatible = "marvell,coherency-fabric"; - reg = <0x20200 0xb0>, <0x21010 0x1c>; + reg = <0x20200 0xb0>, <0x21810 0x1c>; }; serial@12000 { @@ -138,14 +137,6 @@ status = "disabled"; }; - coredivclk: corediv-clock@18740 { - compatible = "marvell,armada-370-corediv-clock"; - reg = <0x18740 0xc>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; - }; - timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; @@ -185,6 +176,7 @@ i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <31>; @@ -195,6 +187,7 @@ i2c1: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = <32>; @@ -259,13 +252,4 @@ }; }; - - clocks { - /* 2 GHz fixed main PLL */ - mainpll: mainpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - }; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 7a4b82e..e134d7a 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -44,7 +44,6 @@ #address-cells = <3>; #size-cells = <2>; - msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = @@ -219,14 +218,6 @@ }; }; - i2c0: i2c@11000 { - reg = <0x11000 0x20>; - }; - - i2c1: i2c@11100 { - reg = <0x11100 0x20>; - }; - usb@50000 { clocks = <&coreclk 0>; }; diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts deleted file mode 100644 index e47c49e..0000000 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Device Tree file for Marvell Armada XP Matrix board - * - * Copyright (C) 2013 Marvell - * - * Lior Amsalem <alior@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; -#include "armada-xp-mv78460.dtsi" - -/ { - model = "Marvell Armada XP Matrix Board"; - compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; - - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; - - internal-regs { - serial@12000 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@12100 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@12200 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@12300 { - clock-frequency = <250000000>; - status = "okay"; - }; - - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - - ethernet@30000 { - status = "okay"; - phy-mode = "sgmii"; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - - usb@50000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 98335fb..0358a33 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -47,7 +47,7 @@ /* * MV78230 has 2 PCIe units Gen2.0: One unit can be * configured as x4 or quad x1 lanes. One unit is - * x1 only. + * x4/x1. */ pcie-controller { compatible = "marvell,armada-xp-pcie"; @@ -57,15 +57,14 @@ #address-cells = <3>; #size-cells = <2>; - msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ @@ -74,8 +73,8 @@ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; pcie@1,0 { device_type = "pci"; @@ -145,20 +144,20 @@ status = "disabled"; }; - pcie@5,0 { + pcie@9,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; + clocks = <&gateclk 26>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 6660968..0e82c50 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -48,7 +48,7 @@ /* * MV78260 has 3 PCIe units Gen2.0: Two units can be * configured as x4 or quad x1 lanes. One unit is - * x4 only. + * x4/x1. */ pcie-controller { compatible = "marvell,armada-xp-pcie"; @@ -58,7 +58,6 @@ #address-cells = <3>; #size-cells = <2>; - msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = @@ -68,9 +67,7 @@ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ - 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ - 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ - 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ @@ -79,18 +76,10 @@ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ - - 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ - 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ - 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ - 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ - 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ - 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ - 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ - - 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ - 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; + 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ + 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ + 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; pcie@1,0 { device_type = "pci"; @@ -116,8 +105,8 @@ #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &mpic 59>; marvell,pcie-port = <0>; @@ -160,88 +149,37 @@ status = "disabled"; }; - pcie@5,0 { + pcie@9,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x2800 0 0 0 0>; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 - 0x81000000 0 0 0x81000000 0x5 0 1 0>; + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 + 0x81000000 0 0 0x81000000 0x9 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; - marvell,pcie-port = <1>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; marvell,pcie-lane = <0>; - clocks = <&gateclk 9>; - status = "disabled"; - }; - - pcie@6,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; - reg = <0x3000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 - 0x81000000 0 0 0x81000000 0x6 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <1>; - clocks = <&gateclk 10>; - status = "disabled"; - }; - - pcie@7,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; - reg = <0x3800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 - 0x81000000 0 0 0x81000000 0x7 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <2>; - clocks = <&gateclk 11>; - status = "disabled"; - }; - - pcie@8,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; - reg = <0x4000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 - 0x81000000 0 0 0x81000000 0x8 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <3>; - clocks = <&gateclk 12>; + clocks = <&gateclk 26>; status = "disabled"; }; - pcie@9,0 { + pcie@10,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; - reg = <0x4800 0 0 0 0>; + assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; + reg = <0x5000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 - 0x81000000 0 0 0x81000000 0x9 0 1 0>; + ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 + 0x81000000 0 0 0x81000000 0xa 0 1 0>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; - marvell,pcie-port = <2>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; marvell,pcie-lane = <0>; - clocks = <&gateclk 26>; + clocks = <&gateclk 27>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 31ba6d8..e82c1b8 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -74,7 +74,6 @@ #address-cells = <3>; #size-cells = <2>; - msi-parent = <&mpic>; bus-range = <0x00 0xff>; ranges = diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 281c644..3058522 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -147,16 +147,6 @@ }; }; - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - usb@50000 { clocks = <&gateclk 18>; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index cb2c010..1373546 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -96,6 +96,7 @@ }; spi0: spi@fffc8000 { + status = "okay"; cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; mtd_dataflash@0 { compatible = "atmel,at45", "atmel,dataflash"; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 17b8799..b4ec6fe 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -7,8 +7,6 @@ */ #include "at91sam9x5.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" / { model = "Atmel AT91SAM9G25 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index e35c2fc..bebf9f5 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -7,7 +7,6 @@ */ #include "at91sam9x5.dtsi" -#include "at91sam9x5_macb0.dtsi" / { model = "Atmel AT91SAM9G35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 6224f9f..9fb7ffd 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -437,9 +437,6 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0010000 0x4000>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; - dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>, - <&dma 0 AT91_DMA_CFG_PER_ID(22)>; - dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index e9487f6..27a9352 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -38,18 +38,9 @@ status = "okay"; }; - ssc0: ssc@f0010000 { - status = "okay"; - }; - i2c0: i2c@f8010000 { status = "okay"; - wm8904: codec@1a { - compatible = "wm8904"; - reg = <0x1a>; - }; - qt1070: keyboard@1b { compatible = "qt1070"; reg = <0x1b>; @@ -91,13 +82,6 @@ <AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; }; }; - - sound { - pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { - atmel,pins = - <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; - }; - }; }; spi0: spi@f0000000 { @@ -158,22 +142,4 @@ gpio-key,wakeup; }; }; - - sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12"; - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; - }; }; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index c255421..49e94ab 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -7,9 +7,6 @@ */ #include "at91sam9x5.dtsi" -#include "at91sam9x5_usart3.dtsi" -#include "at91sam9x5_macb0.dtsi" -#include "at91sam9x5_macb1.dtsi" / { model = "Atmel AT91SAM9X25 SoC"; @@ -25,6 +22,27 @@ 0x80000000 0xfffd0000 0xb83fffff /* pioC */ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; + + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ + AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ + AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ + AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ + AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ + AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ + AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ + }; + }; + }; + + macb1: ethernet@f8030000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 8eac66c..1a3d525 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -7,7 +7,6 @@ */ #include "at91sam9x5.dtsi" -#include "at91sam9x5_macb0.dtsi" / { model = "Atmel AT91SAM9X35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 40267a1..e74dc15 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -206,6 +206,29 @@ }; }; + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ + }; + }; + uart0 { pinctrl_uart0: uart0-0 { atmel,pins = @@ -254,6 +277,34 @@ }; }; + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + + pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ + }; + }; + mmc0 { pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { atmel,pins = @@ -559,6 +610,22 @@ status = "disabled"; }; + macb0: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + status = "disabled"; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; + status = "disabled"; + }; + i2c0: i2c@f8010000 { compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi deleted file mode 100644 index 55731ff..0000000 --- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -/* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 - * Ethernet interface. - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ - }; - - pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { - atmel,pins = - <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ - AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ - AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ - AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ - }; - }; - }; - - macb0: ethernet@f802c000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi deleted file mode 100644 index 77425a6..0000000 --- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -/* - * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 - * Ethernet interfaces. - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff400 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ - AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ - AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ - AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ - AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ - AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ - AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ - AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ - AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ - AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ - }; - }; - }; - - macb1: ethernet@f8030000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf8030000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi deleted file mode 100644 index 6801106..0000000 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -/* - * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * 4 USART. - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - aliases { - serial4 = &usart3; - }; - - ahb { - apb { - pinctrl@fffff400 { - usart3 { - pinctrl_usart3: usart3-0 { - atmel,pins = - <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ - AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ - }; - - pinctrl_usart3_rts: usart3_rts-0 { - atmel,pins = - <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ - }; - - pinctrl_usart3_cts: usart3_cts-0 { - atmel,pins = - <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ - }; - - pinctrl_usart3_sck: usart3_sck-0 { - atmel,pins = - <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ - }; - }; - }; - - usart3: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usart3>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 978bab4..6db4f81 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -65,11 +65,6 @@ compatible = "sirf,prima2-rsc"; reg = <0x88020000 0x1000>; }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - }; }; mem-iobg { @@ -80,17 +75,10 @@ memory-controller@90000000 { compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; + reg = <0x90000000 0x10000>; interrupts = <27>; clocks = <&clks 5>; }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; }; disp-iobg { @@ -132,20 +120,6 @@ }; }; - graphics2d-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - ble@a0000000 { - compatible = "sirf,atlas6-ble"; - reg = <0xa0000000 0x2000>; - interrupts = <5>; - clocks = <&clks 33>; - }; - }; - dsp-iobg { compatible = "simple-bus"; #address-cells = <1>; @@ -297,11 +271,6 @@ compatible = "sirf,prima2-spi"; reg = <0xb0170000 0x10000>; interrupts = <16>; - sirf,spi-num-chipselects = <1>; - sirf,spi-dma-rx-channel = <12>; - sirf,spi-dma-tx-channel = <13>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clks 20>; status = "disabled"; }; @@ -558,18 +527,6 @@ sirf,function = "usb1_utmi_drvbus"; }; }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; warm_rst_pins_a: warm_rst@0 { warm_rst { sirf,pins = "warm_rstgrp"; diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts index 23cd16d..9d36eb4 100644 --- a/arch/arm/boot/dts/bcm11351-brt.dts +++ b/arch/arm/boot/dts/bcm11351-brt.dts @@ -40,7 +40,6 @@ sdio4: sdio@3f1b0000 { max-frequency = <48000000>; - cd-gpios = <&gpio 14 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index b0c0610..05a5aab 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -49,36 +49,6 @@ reg-io-width = <4>; }; - uart@3e001000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e001000 0x1000>; - clock-frequency = <13000000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e002000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e002000 0x1000>; - clock-frequency = <13000000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart@3e003000 { - compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; - reg = <0x3e003000 0x1000>; - clock-frequency = <13000000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; - L2: l2-cache { compatible = "brcm,bcm11351-a2-pl310-cache"; reg = <0x3ff20000 0x1000>; @@ -98,47 +68,31 @@ clock-frequency = <32768>; }; - gpio: gpio@35003000 { - compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; - reg = <0x35003000 0x800>; - interrupts = - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - #interrupt-cells = <2>; - gpio-controller; - interrupt-controller; - }; - sdio1: sdio@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0x0 77 0x4>; status = "disabled"; }; sdio2: sdio@3f190000 { compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x10000>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0x0 76 0x4>; status = "disabled"; }; sdio3: sdio@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0x0 74 0x4>; status = "disabled"; }; sdio4: sdio@3f1b0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x10000>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0x0 73 0x4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index 08e47c2..96ae67a 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -40,7 +40,6 @@ sdio4: sdio@3f1b0000 { max-frequency = <48000000>; - cd-gpios = <&gpio 14 0>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index aa537ed..1e12aef 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -85,8 +85,6 @@ reg = <0x7e205000 0x1000>; interrupts = <2 21>; clocks = <&clk_i2c>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -95,8 +93,6 @@ reg = <0x7e804000 0x1000>; interrupts = <2 21>; clocks = <&clk_i2c>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index 9b186ac..dc259e8b 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -27,13 +27,6 @@ i2c2_bus: i2c2-bus { samsung,pin-pud = <0>; }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; }; i2c@12C60000 { @@ -42,11 +35,6 @@ max77686@09 { compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; reg = <0x09>; voltage-regulators { diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts index 50c0d69..61a8062 100644 --- a/arch/arm/boot/dts/dove-cm-a510.dts +++ b/arch/arm/boot/dts/dove-cm-a510.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "dove.dtsi" +/include/ "dove.dtsi" / { model = "Compulab CM-A510"; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 8349a24..022646e 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "dove.dtsi" +/include/ "dove.dtsi" / { model = "SolidRun CuBox"; @@ -99,13 +99,19 @@ silabs,pll-master; }; - clkout2 { - reg = <2>; + clkout1 { + reg = <1>; silabs,drive-strength = <8>; silabs,multisynth-source = <1>; silabs,clock-source = <0>; silabs,pll-master; }; + + clkout2 { + reg = <2>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + }; }; }; @@ -126,11 +132,3 @@ reg = <0>; }; }; - -&audio1 { - status = "okay"; - clocks = <&gate_clk 13>, <&si5351 2>; - clock-names = "internal", "extclk"; - pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts index c11d363..e2222ce 100644 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "dove.dtsi" +/include/ "dove.dtsi" / { model = "Globalscale D2Plug"; diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts deleted file mode 100644 index f5f59bb..0000000 --- a/arch/arm/boot/dts/dove-d3plug.dts +++ /dev/null @@ -1,103 +0,0 @@ -/dts-v1/; - -#include "dove.dtsi" - -/ { - model = "Globalscale D3Plug"; - compatible = "globalscale,d3plug", "marvell,dove"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; - pinctrl-names = "default"; - - wlan-act { - label = "wlan-act"; - gpios = <&gpio0 0 1>; - }; - - wlan-ap { - label = "wlan-ap"; - gpios = <&gpio0 1 1>; - }; - - status { - label = "status"; - gpios = <&gpio0 2 1>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 0>; - pinctrl-0 = <&pmx_gpio_8>; - pinctrl-names = "default"; - }; - }; -}; - -&uart0 { status = "okay"; }; -&sata0 { status = "okay"; }; -&i2c0 { status = "okay"; }; - -/* Samsung M8G2F eMMC */ -&sdio0 { - status = "okay"; - non-removable; - bus-width = <4>; -}; - -/* Marvell SD8787 WLAN/BT */ -&sdio1 { - status = "okay"; - non-removable; -}; - -&spi0 { - status = "okay"; - - /* spi0.0: 2M Flash Macronix MX25L1605D */ - spi-flash@0 { - compatible = "st,m25l1605d"; - spi-max-frequency = <86000000>; - reg = <0>; - }; -}; - -&pcie { - status = "okay"; - /* Fresco Logic USB3.0 xHCI controller */ - pcie-port@0 { - status = "okay"; - reset-gpios = <&gpio0 26 1>; - reset-delay-us = <20000>; - pinctrl-0 = <&pmx_camera_gpio>; - pinctrl-names = "default"; - }; - /* Mini-PCIe slot */ - pcie-port@1 { - status = "okay"; - reset-gpios = <&gpio0 25 1>; - }; -}; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts index bb725dc..e5a920b 100644 --- a/arch/arm/boot/dts/dove-dove-db.dts +++ b/arch/arm/boot/dts/dove-dove-db.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "dove.dtsi" +/include/ "dove.dtsi" / { model = "Marvell DB-MV88AP510-BP Development Board"; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 113a8bc..cc27916 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -1,11 +1,8 @@ /include/ "skeleton.dtsi" -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - / { compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; - interrupt-parent = <&intc>; aliases { gpio0 = &gpio0; @@ -30,576 +27,482 @@ marvell,tauros2-cache-features = <0>; }; - mbus { - compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; - #address-cells = <2>; + soc@f1000000 { + compatible = "simple-bus"; + #address-cells = <1>; #size-cells = <1>; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ - pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ - - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ - MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ - MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ - MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ - MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ - - pcie: pcie-controller { - compatible = "marvell,dove-pcie"; + interrupt-parent = <&intc>; + + ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ + 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ + 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ + 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ + 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ + 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ + 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ + 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <5>; + }; + + core_clk: core-clocks@d0214 { + compatible = "marvell,dove-core-clock"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; + }; + + gate_clk: clock-gating-ctrl@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + thermal: thermal-diode@d001c { + compatible = "marvell,dove-thermal"; + reg = <0xd001c 0x0c>, <0xd005c 0x08>; + }; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <7>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&core_clk 0>; status = "disabled"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&intc>; - bus-range = <0x00 0xff>; - - ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 - 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 - 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ - 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ - 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ - 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ - - pcie-port@0 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - clocks = <&gate_clk 4>; - marvell,pcie-port = <0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 16>; - }; - - pcie-port@1 { - device_type = "pci"; - status = "disabled"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - clocks = <&gate_clk 5>; - marvell,pcie-port = <1>; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 18>; + }; + + uart3: serial@12300 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + gpio0: gpio-ctrl@d0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio-ctrl@d0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <61>; + }; + + gpio2: gpio-ctrl@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpios = <8>; + }; + + pinctrl: pin-ctrl@d0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0xd0200 0x10>; + clocks = <&gate_clk 22>; + + pmx_gpio_0: pmx-gpio-0 { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_gpio_1: pmx-gpio-1 { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_gpio_2: pmx-gpio-2 { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_gpio_3: pmx-gpio-3 { + marvell,pins = "mpp3"; + marvell,function = "gpio"; }; + + pmx_gpio_4: pmx-gpio-4 { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; + + pmx_gpio_5: pmx-gpio-5 { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + pmx_gpio_6: pmx-gpio-6 { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + pmx_gpio_7: pmx-gpio-7 { + marvell,pins = "mpp7"; + marvell,function = "gpio"; + }; + + pmx_gpio_8: pmx-gpio-8 { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + pmx_gpio_9: pmx-gpio-9 { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + + pmx_gpio_10: pmx-gpio-10 { + marvell,pins = "mpp10"; + marvell,function = "gpio"; + }; + + pmx_gpio_11: pmx-gpio-11 { + marvell,pins = "mpp11"; + marvell,function = "gpio"; + }; + + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_gpio_13: pmx-gpio-13 { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_gpio_14: pmx-gpio-14 { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_gpio_15: pmx-gpio-15 { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_gpio_16: pmx-gpio-16 { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_gpio_17: pmx-gpio-17 { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_gpio_18: pmx-gpio-18 { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_gpio_19: pmx-gpio-19 { + marvell,pins = "mpp19"; + marvell,function = "gpio"; + }; + + pmx_gpio_20: pmx-gpio-20 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_gpio_21: pmx-gpio-21 { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_camera: pmx-camera { + marvell,pins = "mpp_camera"; + marvell,function = "camera"; + }; + + pmx_camera_gpio: pmx-camera-gpio { + marvell,pins = "mpp_camera"; + marvell,function = "gpio"; + }; + + pmx_sdio0: pmx-sdio0 { + marvell,pins = "mpp_sdio0"; + marvell,function = "sdio0"; + }; + + pmx_sdio0_gpio: pmx-sdio0-gpio { + marvell,pins = "mpp_sdio0"; + marvell,function = "gpio"; + }; + + pmx_sdio1: pmx-sdio1 { + marvell,pins = "mpp_sdio1"; + marvell,function = "sdio1"; + }; + + pmx_sdio1_gpio: pmx-sdio1-gpio { + marvell,pins = "mpp_sdio1"; + marvell,function = "gpio"; + }; + + pmx_audio1_gpio: pmx-audio1-gpio { + marvell,pins = "mpp_audio1"; + marvell,function = "gpio"; + }; + + pmx_spi0: pmx-spi0 { + marvell,pins = "mpp_spi0"; + marvell,function = "spi0"; + }; + + pmx_spi0_gpio: pmx-spi0-gpio { + marvell,pins = "mpp_spi0"; + marvell,function = "gpio"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; + + pmx_uart1_gpio: pmx-uart1-gpio { + marvell,pins = "mpp_uart1"; + marvell,function = "gpio"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp_nand"; + marvell,function = "nand"; + }; + + pmx_nand_gpo: pmx-nand-gpo { + marvell,pins = "mpp_nand"; + marvell,function = "gpo"; + }; + }; + + spi0: spi-ctrl@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; + clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_spi0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi1: spi-ctrl@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + i2c0: i2c-ctrl@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + timeout-ms = <1000>; + clocks = <&core_clk 0>; + status = "disabled"; }; - internal-regs { - compatible = "simple-bus"; + ehci0: usb-host@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <24>; + clocks = <&gate_clk 0>; + status = "okay"; + }; + + ehci1: usb-host@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x1000>; + interrupts = <25>; + clocks = <&gate_clk 1>; + status = "okay"; + }; + + sdio0: sdio-host@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + clocks = <&gate_clk 8>; + pinctrl-0 = <&pmx_sdio0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sdio1: sdio-host@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + clocks = <&gate_clk 9>; + pinctrl-0 = <&pmx_sdio1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata0: sata-host@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + clocks = <&gate_clk 3>; + nr-ports = <1>; + status = "disabled"; + }; + + rtc: real-time-clock@d8500 { + compatible = "marvell,orion-rtc"; + reg = <0xd8500 0x20>; + }; + + crypto: crypto-engine@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xc8000000 0x800>; + reg-names = "regs", "sram"; + interrupts = <31>; + clocks = <&gate_clk 15>; + status = "okay"; + }; + + xor0: dma-engine@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gate_clk 23>; + status = "okay"; + + channel0 { + interrupts = <39>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <40>; + dmacap,memset; + dmacap,memcpy; + dmacap,xor; + }; + }; + + xor1: dma-engine@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gate_clk 24>; + status = "okay"; + + channel0 { + interrupts = <42>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <43>; + dmacap,memset; + dmacap,memcpy; + dmacap,xor; + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ - 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ - 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ - 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ - - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - core_clk: core-clocks@d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; - }; - - gate_clk: clock-gating-ctrl@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - thermal: thermal-diode@d001c { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <7>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <8>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@12200 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - uart3: serial@12300 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - gpio0: gpio-ctrl@d0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0400 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12>, <13>, <14>, <60>; - }; - - gpio1: gpio-ctrl@d0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0420 0x20>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61>; - }; - - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; - }; - - pinctrl: pin-ctrl@d0200 { - compatible = "marvell,dove-pinctrl"; - reg = <0xd0200 0x10>; - clocks = <&gate_clk 22>; - - pmx_gpio_0: pmx-gpio-0 { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - - pmx_gpio_1: pmx-gpio-1 { - marvell,pins = "mpp1"; - marvell,function = "gpio"; - }; - - pmx_gpio_2: pmx-gpio-2 { - marvell,pins = "mpp2"; - marvell,function = "gpio"; - }; - - pmx_gpio_3: pmx-gpio-3 { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - - pmx_gpio_4: pmx-gpio-4 { - marvell,pins = "mpp4"; - marvell,function = "gpio"; - }; - - pmx_gpio_5: pmx-gpio-5 { - marvell,pins = "mpp5"; - marvell,function = "gpio"; - }; - - pmx_gpio_6: pmx-gpio-6 { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - pmx_gpio_7: pmx-gpio-7 { - marvell,pins = "mpp7"; - marvell,function = "gpio"; - }; - - pmx_gpio_8: pmx-gpio-8 { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - - pmx_gpio_9: pmx-gpio-9 { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - - pmx_gpio_10: pmx-gpio-10 { - marvell,pins = "mpp10"; - marvell,function = "gpio"; - }; - - pmx_gpio_11: pmx-gpio-11 { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - - pmx_gpio_12: pmx-gpio-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_gpio_13: pmx-gpio-13 { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_audio1_extclk: pmx-audio1-extclk { - marvell,pins = "mpp13"; - marvell,function = "audio1"; - }; - - pmx_gpio_14: pmx-gpio-14 { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_gpio_15: pmx-gpio-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_gpio_16: pmx-gpio-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_gpio_17: pmx-gpio-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_gpio_18: pmx-gpio-18 { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - pmx_gpio_19: pmx-gpio-19 { - marvell,pins = "mpp19"; - marvell,function = "gpio"; - }; - - pmx_gpio_20: pmx-gpio-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_gpio_21: pmx-gpio-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_camera: pmx-camera { - marvell,pins = "mpp_camera"; - marvell,function = "camera"; - }; - - pmx_camera_gpio: pmx-camera-gpio { - marvell,pins = "mpp_camera"; - marvell,function = "gpio"; - }; - - pmx_sdio0: pmx-sdio0 { - marvell,pins = "mpp_sdio0"; - marvell,function = "sdio0"; - }; - - pmx_sdio0_gpio: pmx-sdio0-gpio { - marvell,pins = "mpp_sdio0"; - marvell,function = "gpio"; - }; - - pmx_sdio1: pmx-sdio1 { - marvell,pins = "mpp_sdio1"; - marvell,function = "sdio1"; - }; - - pmx_sdio1_gpio: pmx-sdio1-gpio { - marvell,pins = "mpp_sdio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_gpio: pmx-audio1-gpio { - marvell,pins = "mpp_audio1"; - marvell,function = "gpio"; - }; - - pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { - marvell,pins = "mpp_audio1"; - marvell,function = "i2s1/spdifo"; - }; - - pmx_spi0: pmx-spi0 { - marvell,pins = "mpp_spi0"; - marvell,function = "spi0"; - }; - - pmx_spi0_gpio: pmx-spi0-gpio { - marvell,pins = "mpp_spi0"; - marvell,function = "gpio"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp_uart1"; - marvell,function = "uart1"; - }; - - pmx_uart1_gpio: pmx-uart1-gpio { - marvell,pins = "mpp_uart1"; - marvell,function = "gpio"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp_nand"; - marvell,function = "nand"; - }; - - pmx_nand_gpo: pmx-nand-gpo { - marvell,pins = "mpp_nand"; - marvell,function = "gpo"; - }; - }; - - spi0: spi-ctrl@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - spi1: spi-ctrl@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - i2c0: i2c-ctrl@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - timeout-ms = <1000>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - nr-ports = <1>; - status = "disabled"; - }; - - rtc: real-time-clock@d8500 { - compatible = "marvell,orion-rtc"; - reg = <0xd8500 0x20>; - }; - - crypto: crypto-engine@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0xffffe000 0x800>; - reg-names = "regs", "sram"; - interrupts = <31>; - clocks = <&gate_clk 15>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - - ethphy: ethernet-phy { - device-type = "ethernet-phy"; - /* set phy address in board file */ - }; - }; - - eth: ethernet-ctrl@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - device_type = "network"; - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; - }; - }; - - audio0: audio-controller@b0000 { - compatible = "marvell,dove-audio"; - reg = <0xb0000 0x2210>; - interrupts = <19>, <20>; - clocks = <&gate_clk 12>; - clock-names = "internal"; - status = "disabled"; - }; - - audio1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; - status = "disabled"; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <30>; + clocks = <&gate_clk 2>; + status = "disabled"; + + ethphy: ethernet-phy { + device-type = "ethernet-phy"; + /* set phy address in board file */ + }; + }; + + eth: ethernet-controller@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 2>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + device_type = "network"; + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <29>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðphy>; }; }; }; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts deleted file mode 100644 index 5babba0..0000000 --- a/arch/arm/boot/dts/dra7-evm.dts +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "dra7.dtsi" - -/ { - model = "TI DRA7"; - compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x60000000>; /* 1536 MB */ - }; - - mmc2_3v3: fixedregulator-mmc2 { - compatible = "regulator-fixed"; - regulator-name = "mmc2_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */ - 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */ - 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */ - 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ - 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */ - 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */ - 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ - 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ - 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ - 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ - 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ - 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ - 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ - 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps123_reg: smps123 { - /* VDD_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_GPU - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <12500000>; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* CORE_VDD */ - regulator-name = "smps7"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1030000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_IVAHD */ - regulator-name = "smps8"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDS1V8 */ - regulator-name = "smps9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* VDD_RTCIO */ - /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <3400000>; -}; - -&mcspi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -&mcspi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&mmc2_3v3>; - bus-width = <8>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi deleted file mode 100644 index d0df4c4..0000000 --- a/arch/arm/boot/dts/dra7.dtsi +++ /dev/null @@ -1,586 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * Based on "omap4.dtsi" - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/dra.h> - -#include "skeleton.dtsi" - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "ti,dra7xx"; - interrupt-parent = <&gic>; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48211000 0x1000>, - <0x48212000 0x1000>, - <0x48214000 0x2000>, - <0x48216000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - /* - * The soc node represents the soc top level view. It is uses for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap5-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the SOC interconnect. - * The real OMAP interconnect network is quite complex. - * Since that will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - - counter32k: counter@4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; - }; - - dra7_pmx_core: pinmux@4a003400 { - compatible = "pinctrl-single"; - reg = <0x4a003400 0x0464>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <127>; - }; - - gpio1: gpio@4ae10000 { - compatible = "ti,omap4-gpio"; - reg = <0x4ae10000 0x200>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio7: gpio@48051000 { - compatible = "ti,omap4-gpio"; - reg = <0x48051000 0x200>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio7"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio8: gpio@48053000 { - compatible = "ti,omap4-gpio"; - reg = <0x48053000 0x200>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "gpio8"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart3: serial@48020000 { - compatible = "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart5: serial@48066000 { - compatible = "ti,omap4-uart"; - reg = <0x48066000 0x100>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart6: serial@48068000 { - compatible = "ti,omap4-uart"; - reg = <0x48068000 0x100>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart7: serial@48420000 { - compatible = "ti,omap4-uart"; - reg = <0x48420000 0x100>; - ti,hwmods = "uart7"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart8: serial@48422000 { - compatible = "ti,omap4-uart"; - reg = <0x48422000 0x100>; - ti,hwmods = "uart8"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart9: serial@48424000 { - compatible = "ti,omap4-uart"; - reg = <0x48424000 0x100>; - ti,hwmods = "uart9"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart10: serial@4ae2b000 { - compatible = "ti,omap4-uart"; - reg = <0x4ae2b000 0x100>; - ti,hwmods = "uart10"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae18000 0x80>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48032000 { - compatible = "ti,omap5430-timer"; - reg = <0x48032000 0x80>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap5430-timer"; - reg = <0x48034000 0x80>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap5430-timer"; - reg = <0x48036000 0x80>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer4"; - }; - - timer5: timer@48820000 { - compatible = "ti,omap5430-timer"; - reg = <0x48820000 0x80>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer5"; - ti,timer-dsp; - }; - - timer6: timer@48822000 { - compatible = "ti,omap5430-timer"; - reg = <0x48822000 0x80>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer6"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer7: timer@48824000 { - compatible = "ti,omap5430-timer"; - reg = <0x48824000 0x80>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer7"; - ti,timer-dsp; - }; - - timer8: timer@48826000 { - compatible = "ti,omap5430-timer"; - reg = <0x48826000 0x80>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer8"; - ti,timer-dsp; - ti,timer-pwm; - }; - - timer9: timer@4803e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4803e000 0x80>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer9"; - }; - - timer10: timer@48086000 { - compatible = "ti,omap5430-timer"; - reg = <0x48086000 0x80>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer10"; - }; - - timer11: timer@48088000 { - compatible = "ti,omap5430-timer"; - reg = <0x48088000 0x80>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - timer13: timer@48828000 { - compatible = "ti,omap5430-timer"; - reg = <0x48828000 0x80>; - ti,hwmods = "timer13"; - status = "disabled"; - }; - - timer14: timer@4882a000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882a000 0x80>; - ti,hwmods = "timer14"; - status = "disabled"; - }; - - timer15: timer@4882c000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882c000 0x80>; - ti,hwmods = "timer15"; - status = "disabled"; - }; - - timer16: timer@4882e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882e000 0x80>; - ti,hwmods = "timer16"; - status = "disabled"; - }; - - wdt2: wdt@4ae14000 { - compatible = "ti,omap4-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "wd_timer2"; - }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - status = "disabled"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - status = "disabled"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - status = "disabled"; - }; - - i2c4: i2c@4807a000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807a000 0x100>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - status = "disabled"; - }; - - i2c5: i2c@4807c000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807c000 0x100>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c5"; - status = "disabled"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - status = "disabled"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts index 2ccbb57f..139b40c 100644 --- a/arch/arm/boot/dts/ecx-2000.dts +++ b/arch/arm/boot/dts/ecx-2000.dts @@ -85,12 +85,6 @@ <1 10 0xf08>; }; - memory-controller@fff00000 { - compatible = "calxeda,ecx-2000-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index b90045a..e8559b7 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -19,14 +19,6 @@ bootargs = "console=ttyAMA0"; }; - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -53,6 +45,12 @@ status = "disabled"; }; + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; + ipc@fff20000 { compatible = "arm,pl320", "arm,primecell"; reg = <0xfff20000 0x1000>; diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts new file mode 100644 index 0000000..cceefda --- /dev/null +++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts @@ -0,0 +1,57 @@ +/* + * Device Tree Source for the KZM9D board + * + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +/dts-v1/; + +/include/ "emev2.dtsi" + +/ { + model = "EMEV2 KZM9D Board"; + compatible = "renesas,kzm9d-reference", "renesas,emev2"; + + memory { + device_type = "memory"; + reg = <0x40000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; + }; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + lan9220@20000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x20000000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gpio0>; + interrupts = <1 1>; /* active high */ + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; +}; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 861aa7d..f92e812 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -1,7 +1,7 @@ /* * Device Tree Source for the KZM9D board * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2012 Renesas Solutions Corp. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -23,35 +23,4 @@ chosen { bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; }; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - lan9220@20000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x20000000 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpio0>; - interrupts = <1 1>; /* active high */ - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index a73eeb5..caadc02 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -49,12 +49,6 @@ reg = <0x10000000 0x100>; }; - mipi_phy: video-phy@10020710 { - compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10020710 8>; - #phy-cells = <1>; - }; - pd_mfc: mfc-power-domain@10023C40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; @@ -167,8 +161,6 @@ clock-names = "csis", "sclk_csis"; bus-width = <4>; samsung,power-domain = <&pd_cam>; - phys = <&mipi_phy 0>; - phy-names = "csis"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -182,8 +174,6 @@ clock-names = "csis", "sclk_csis"; bus-width = <2>; samsung,power-domain = <&pd_cam>; - phys = <&mipi_phy 2>; - phy-names = "csis"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 1a12fb2..382d8c7 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,20 +32,13 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 0>; - enable-active-high; - }; + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 0>; + enable-active-high; }; tmu@100C0000 { @@ -199,12 +192,7 @@ }; buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM_1.2V"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1350000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63cc571..1c164f2 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -290,12 +290,7 @@ }; varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d2e3f5f..889cdad 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -350,7 +350,3 @@ status = "okay"; }; }; - -&mdma1 { - reg = <0x12840000 0x1000>; -}; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index d65984c..8768b03 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -32,20 +32,13 @@ reg = <0x0203F000 0x1000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 0>; - enable-active-high; - }; + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 0>; + enable-active-high; }; pinctrl@11000000 { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 6845270..cee55fa 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -324,14 +324,7 @@ }; i2c@12C80000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; + status = "disabled"; }; i2c@12C90000 { @@ -369,17 +362,6 @@ status = "disabled"; }; - i2c@12CE0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x38>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - i2c@121D0000 { status = "disabled"; }; @@ -430,10 +412,6 @@ status = "disabled"; }; - i2s0: i2s@03830000 { - status = "okay"; - }; - spi_0: spi@12d20000 { status = "disabled"; }; @@ -504,15 +482,13 @@ #address-cells = <1>; #size-cells = <0>; - main_dc_reg: regulator@0 { + main_dc_reg: fixedregulator@1 { compatible = "regulator-fixed"; - reg = <0>; regulator-name = "MAIN_DC"; }; - mmc_reg: regulator@1 { + mmc_reg: voltage-regulator { compatible = "regulator-fixed"; - reg = <1>; regulator-name = "VDD_33ON_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -520,9 +496,8 @@ enable-active-high; }; - reg_hdmi_en: regulator@2 { + reg_hdmi_en: fixedregulator@0 { compatible = "regulator-fixed"; - reg = <2>; regulator-name = "hdmi-en"; }; }; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 9a49e68..724a22f 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -210,21 +210,21 @@ samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; i2c2_hs_bus: i2c2-hs-bus { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <4>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; uart2_data: uart2-data { @@ -238,21 +238,21 @@ samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; i2c3_hs_bus: i2c3-hs-bus { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <4>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; uart3_data: uart3-data { @@ -273,14 +273,14 @@ samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; spi1_bus: spi1-bus { @@ -376,14 +376,14 @@ samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <4>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; i2c1_hs_bus: i2c1-hs-bus { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <4>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; sd0_clk: sd0-clk { @@ -551,14 +551,14 @@ samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; dp_hpd: dp_hpd { samsung,pins = "gpx0-7"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; }; @@ -649,42 +649,42 @@ "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_i2c2_bus: cam-i2c2-bus { samsung,pins = "gpe0-6", "gpe1-0"; samsung,pin-function = <4>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; samsung,pin-function = <4>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_bayrgb_bus: cam-bayrgb-bus { @@ -695,7 +695,7 @@ "gpg2-0", "gpg2-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; cam_port_a: cam-port-a { @@ -704,7 +704,7 @@ "gph1-4", "gph1-5", "gph1-6", "gph1-7"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; }; @@ -756,7 +756,7 @@ "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; c2c_txd: c2c-txd { @@ -766,7 +766,7 @@ "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samaung,pin-drv = <0>; }; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index f86d567..2538b32 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -231,6 +231,14 @@ status = "okay"; }; + i2s1: i2s@12D60000 { + status = "disabled"; + }; + + i2s2: i2s@12D70000 { + status = "disabled"; + }; + sound { compatible = "samsung,smdk-wm8994"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9db5047..bbac42a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -422,7 +422,6 @@ i2s0: i2s@03830000 { compatible = "samsung,s5pv210-i2s"; - status = "disabled"; reg = <0x03830000 0x100>; dmas = <&pdma0 10 &pdma0 9 @@ -439,7 +438,6 @@ i2s1: i2s@12D60000 { compatible = "samsung,s3c6410-i2s"; - status = "disabled"; reg = <0x12D60000 0x100>; dmas = <&pdma1 12 &pdma1 11>; @@ -452,7 +450,6 @@ i2s2: i2s@12D70000 { compatible = "samsung,s3c6410-i2s"; - status = "disabled"; reg = <0x12D70000 0x100>; dmas = <&pdma0 12 &pdma0 11>; @@ -618,18 +615,16 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; - clocks = <&clock 344>, <&clock 136>, <&clock 137>, - <&clock 159>, <&clock 1024>; + clocks = <&clock 333>, <&clock 136>, <&clock 137>, + <&clock 333>, <&clock 333>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; + "sclk_hdmiphy", "hdmiphy"; }; mixer { compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; - clocks = <&clock 343>, <&clock 136>; - clock-names = "mixer", "sclk_hdmi"; }; dp_phy: video-phy@10040720 { diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 79524c7..bafba25 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -61,30 +61,4 @@ }; }; - pinctrl@13400000 { - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; - }; - - hdmi@14530000 { - status = "okay"; - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - }; - - i2c_2: i2c@12C80000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 09aa06c..d537cd7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -27,10 +27,6 @@ pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; pinctrl4 = &pinctrl_4; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; }; cpus { @@ -239,75 +235,4 @@ io-channel-ranges; status = "disabled"; }; - - i2c_0: i2c@12C60000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; - interrupts = <0 56 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock 261>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "disabled"; - }; - - i2c_1: i2c@12C70000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; - interrupts = <0 57 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock 262>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; - status = "disabled"; - }; - - i2c_2: i2c@12C80000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; - interrupts = <0 58 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock 263>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; - status = "disabled"; - }; - - i2c_3: i2c@12C90000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; - interrupts = <0 59 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock 264>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; - status = "disabled"; - }; - - hdmi@14530000 { - compatible = "samsung,exynos4212-hdmi"; - reg = <0x14530000 0x70000>; - interrupts = <0 95 0>; - clocks = <&clock 413>, <&clock 143>, <&clock 768>, - <&clock 158>, <&clock 640>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "mout_hdmi"; - status = "disabled"; - }; - - mixer@14450000 { - compatible = "samsung,exynos5420-mixer"; - reg = <0x14450000 0x10000>; - interrupts = <0 94 0>; - clocks = <&clock 431>, <&clock 143>; - clock-names = "mixer", "sclk_hdmi"; - }; }; diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index 777fb1c..5b22508 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts @@ -17,7 +17,7 @@ compatible = "samsung,sd5v1", "samsung,exynos5440"; chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; + bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; fixed-rate-clocks { diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index d58cb78..ede7727 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -17,7 +17,7 @@ compatible = "samsung,ssdk5440", "samsung,exynos5440"; chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; + bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; spi_0: spi@D0000 { @@ -68,11 +68,9 @@ pcie@290000 { reset-gpio = <&pin_ctrl 5 0>; - status = "okay"; }; pcie@2a0000 { reset-gpio = <&pin_ctrl 22 0>; - status = "okay"; }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 8da1070..5d6cf49 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -276,7 +276,6 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 53>; num-lanes = <4>; - status = "disabled"; }; pcie@2a0000 { @@ -297,6 +296,5 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 56>; num-lanes = <4>; - status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index ed14aea..6aad34a 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -86,12 +86,6 @@ soc { ranges = <0x00000000 0x00000000 0xffffffff>; - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; - timer@fff10600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfff10600 0x20>; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 1f026ad..185c7c0 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx23.dtsi" +/include/ "imx23.dtsi" / { model = "Freescale i.MX23 Evaluation Kit"; @@ -45,14 +45,14 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_LCD_RESET__GPIO_1_18 - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 - MX23_PAD_SSP1_DETECT__SSP1_DETECT + 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 526bfdb..fc766ae 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -#include "imx23.dtsi" +/include/ "imx23.dtsi" / { model = "i.MX23 Olinuxino Low Cost Board"; @@ -40,21 +40,21 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_GPMI_ALE__GPIO_0_17 + 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; led_pin_gpio2_1: led_gpio2_1@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__GPIO_2_1 + 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h deleted file mode 100644 index 5c0f32ca..0000000 --- a/arch/arm/boot/dts/imx23-pinfunc.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Header providing constants for i.MX23 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ -#define __DT_BINDINGS_MX23_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -#define MX23_PAD_LCD_D00__LCD_D00 0x1000 -#define MX23_PAD_LCD_D01__LCD_D01 0x1010 -#define MX23_PAD_LCD_D02__LCD_D02 0x1020 -#define MX23_PAD_LCD_D03__LCD_D03 0x1030 -#define MX23_PAD_LCD_D04__LCD_D04 0x1040 -#define MX23_PAD_LCD_D05__LCD_D05 0x1050 -#define MX23_PAD_LCD_D06__LCD_D06 0x1060 -#define MX23_PAD_LCD_D07__LCD_D07 0x1070 -#define MX23_PAD_LCD_D08__LCD_D08 0x1080 -#define MX23_PAD_LCD_D09__LCD_D09 0x1090 -#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX23_PAD_LCD_D16__LCD_D16 0x1100 -#define MX23_PAD_LCD_D17__LCD_D17 0x1110 -#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -#define MX23_PAD_LCD_RS__LCD_RS 0x1130 -#define MX23_PAD_LCD_WR__LCD_WR 0x1140 -#define MX23_PAD_LCD_CS__LCD_CS 0x1150 -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -#define MX23_PAD_PWM0__PWM0 0x11a0 -#define MX23_PAD_PWM1__PWM1 0x11b0 -#define MX23_PAD_PWM2__PWM2 0x11c0 -#define MX23_PAD_PWM3__PWM3 0x11d0 -#define MX23_PAD_PWM4__PWM4 0x11e0 -#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -#define MX23_PAD_ROTARYA__ROTARYA 0x2070 -#define MX23_PAD_ROTARYB__ROTARYB 0x2080 -#define MX23_PAD_EMI_A00__EMI_A00 0x2090 -#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 -#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 -#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 -#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 -#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 -#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 -#define MX23_PAD_EMI_A07__EMI_A07 0x2100 -#define MX23_PAD_EMI_A08__EMI_A08 0x2110 -#define MX23_PAD_EMI_A09__EMI_A09 0x2120 -#define MX23_PAD_EMI_A10__EMI_A10 0x2130 -#define MX23_PAD_EMI_A11__EMI_A11 0x2140 -#define MX23_PAD_EMI_A12__EMI_A12 0x2150 -#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -#define MX23_PAD_EMI_D00__EMI_D00 0x3000 -#define MX23_PAD_EMI_D01__EMI_D01 0x3010 -#define MX23_PAD_EMI_D02__EMI_D02 0x3020 -#define MX23_PAD_EMI_D03__EMI_D03 0x3030 -#define MX23_PAD_EMI_D04__EMI_D04 0x3040 -#define MX23_PAD_EMI_D05__EMI_D05 0x3050 -#define MX23_PAD_EMI_D06__EMI_D06 0x3060 -#define MX23_PAD_EMI_D07__EMI_D07 0x3070 -#define MX23_PAD_EMI_D08__EMI_D08 0x3080 -#define MX23_PAD_EMI_D09__EMI_D09 0x3090 -#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 -#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 -#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 -#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 -#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 -#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 -#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 -#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 -#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 -#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 -#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 -#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 -#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 -#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 -#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 -#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 -#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 -#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 -#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 -#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 -#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 -#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 -#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 -#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 -#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 -#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 -#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 -#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 -#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -#define MX23_PAD_PWM0__ROTARYA 0x11a1 -#define MX23_PAD_PWM1__ROTARYB 0x11b1 -#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 -#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -#define MX23_PAD_PWM0__DUART_RX 0x11a2 -#define MX23_PAD_PWM1__DUART_TX 0x11b2 -#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 -#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 -#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -#define MX23_PAD_ROTARYA__SPDIF 0x2072 -#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 -#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 -#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 -#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 -#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 -#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 - -#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index cb64e2b..85c3864 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx23.dtsi" +/include/ "imx23.dtsi" / { model = "Freescale STMP378x Development Board"; @@ -39,12 +39,12 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_PWM3__GPIO_1_29 - MX23_PAD_PWM4__GPIO_1_30 + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index c96ceae..28b5ce2 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -9,8 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" -#include "imx23-pinfunc.h" +/include/ "skeleton.dtsi" / { interrupt-parent = <&icoll>; @@ -138,174 +137,174 @@ duart_pins_a: duart@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_PWM0__DUART_RX - MX23_PAD_PWM1__DUART_TX + 0x11a2 /* MX23_PAD_PWM0__DUART_RX */ + 0x11b2 /* MX23_PAD_PWM1__DUART_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart0_pins_a: auart0@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_AUART1_RX__AUART1_RX - MX23_PAD_AUART1_TX__AUART1_TX - MX23_PAD_AUART1_CTS__AUART1_CTS - MX23_PAD_AUART1_RTS__AUART1_RTS + 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */ + 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */ + 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */ + 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart0_2pins_a: auart0-2pins@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_I2C_SCL__AUART1_TX - MX23_PAD_I2C_SDA__AUART1_RX + 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ + 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_GPMI_D00__GPMI_D00 - MX23_PAD_GPMI_D01__GPMI_D01 - MX23_PAD_GPMI_D02__GPMI_D02 - MX23_PAD_GPMI_D03__GPMI_D03 - MX23_PAD_GPMI_D04__GPMI_D04 - MX23_PAD_GPMI_D05__GPMI_D05 - MX23_PAD_GPMI_D06__GPMI_D06 - MX23_PAD_GPMI_D07__GPMI_D07 - MX23_PAD_GPMI_CLE__GPMI_CLE - MX23_PAD_GPMI_ALE__GPMI_ALE - MX23_PAD_GPMI_RDY0__GPMI_RDY0 - MX23_PAD_GPMI_RDY1__GPMI_RDY1 - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN - MX23_PAD_GPMI_CE1N__GPMI_CE1N - MX23_PAD_GPMI_CE0N__GPMI_CE0N + 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */ + 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */ + 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */ + 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */ + 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */ + 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */ + 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */ + 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */ + 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */ + 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */ + 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */ + 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */ + 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ + 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ + 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ + 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; gpmi_pins_fixup: gpmi-pins-fixup { fsl,pinmux-ids = < - MX23_PAD_GPMI_WPN__GPMI_WPN - MX23_PAD_GPMI_WRN__GPMI_WRN - MX23_PAD_GPMI_RDN__GPMI_RDN + 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ + 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ + 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,drive-strength = <2>; }; mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_SCK__SSP1_SCK + 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ + 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ + 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ + 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ + 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_SSP1_DATA0__SSP1_DATA0 - MX23_PAD_SSP1_DATA1__SSP1_DATA1 - MX23_PAD_SSP1_DATA2__SSP1_DATA2 - MX23_PAD_SSP1_DATA3__SSP1_DATA3 - MX23_PAD_GPMI_D08__SSP1_DATA4 - MX23_PAD_GPMI_D09__SSP1_DATA5 - MX23_PAD_GPMI_D10__SSP1_DATA6 - MX23_PAD_GPMI_D11__SSP1_DATA7 - MX23_PAD_SSP1_CMD__SSP1_CMD - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK + 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ + 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ + 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ + 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ + 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */ + 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */ + 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */ + 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */ + 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mmc0_pins_fixup: mmc0-pins-fixup { fsl,pinmux-ids = < - MX23_PAD_SSP1_DETECT__SSP1_DETECT - MX23_PAD_SSP1_SCK__SSP1_SCK + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ >; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,pull-up = <0>; }; pwm2_pins_a: pwm2@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_PWM2__PWM2 + 0x11c0 /* MX23_PAD_PWM2__PWM2 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_LCD_D00__LCD_D00 - MX23_PAD_LCD_D01__LCD_D01 - MX23_PAD_LCD_D02__LCD_D02 - MX23_PAD_LCD_D03__LCD_D03 - MX23_PAD_LCD_D04__LCD_D04 - MX23_PAD_LCD_D05__LCD_D05 - MX23_PAD_LCD_D06__LCD_D06 - MX23_PAD_LCD_D07__LCD_D07 - MX23_PAD_LCD_D08__LCD_D08 - MX23_PAD_LCD_D09__LCD_D09 - MX23_PAD_LCD_D10__LCD_D10 - MX23_PAD_LCD_D11__LCD_D11 - MX23_PAD_LCD_D12__LCD_D12 - MX23_PAD_LCD_D13__LCD_D13 - MX23_PAD_LCD_D14__LCD_D14 - MX23_PAD_LCD_D15__LCD_D15 - MX23_PAD_LCD_D16__LCD_D16 - MX23_PAD_LCD_D17__LCD_D17 - MX23_PAD_GPMI_D08__LCD_D18 - MX23_PAD_GPMI_D09__LCD_D19 - MX23_PAD_GPMI_D10__LCD_D20 - MX23_PAD_GPMI_D11__LCD_D21 - MX23_PAD_GPMI_D12__LCD_D22 - MX23_PAD_GPMI_D13__LCD_D23 - MX23_PAD_LCD_DOTCK__LCD_DOTCK - MX23_PAD_LCD_ENABLE__LCD_ENABLE - MX23_PAD_LCD_HSYNC__LCD_HSYNC - MX23_PAD_LCD_VSYNC__LCD_VSYNC + 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */ + 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */ + 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */ + 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */ + 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */ + 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */ + 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */ + 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */ + 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */ + 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */ + 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; spi2_pins_a: spi2@0 { reg = <0>; fsl,pinmux-ids = < - MX23_PAD_GPMI_WRN__SSP2_SCK - MX23_PAD_GPMI_RDY1__SSP2_CMD - MX23_PAD_GPMI_D00__SSP2_DATA0 - MX23_PAD_GPMI_D03__SSP2_DATA3 + 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */ + 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */ + 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */ + 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; }; @@ -431,7 +430,6 @@ reg = <0x80050000 0x2000>; interrupts = <36 37 38 39 40 41 42 43 44>; status = "disabled"; - clocks = <&clks 26>; }; spdif@80054000 { diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 47c8c26..2a377ca 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -16,26 +16,6 @@ model = "Armadeus Systems APF27Dev docking/development board"; compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; - display: display { - model = "Chimei-LW700AT9003"; - native-mode = <&timing0>; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xfae80083>; /* non-standard but required */ - display-timings { - timing0: 640x480 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <640>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -70,12 +50,6 @@ status = "okay"; }; -&fb { - display = <&display>; - fsl,dmacr = <0x00020010>; - status = "okay"; -}; - &i2c1 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 826231e..b7a1c6d 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -123,7 +123,6 @@ }; pwm: pwm@10006000 { - #pwm-cells = <2>; compatible = "fsl,imx27-pwm"; reg = <0x10006000 0x1000>; interrupts = <23>; diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index 7198fe3..7eb0758 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx28.dtsi" +/include/ "imx28.dtsi" / { model = "Armadeus Systems APF28 module"; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index e2efd8d..b602494 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -10,7 +10,7 @@ */ /* APF28Dev is a docking board for the APF28 SOM */ -#include "imx28-apf28.dts" +/include/ "imx28-apf28.dts" / { model = "Armadeus Systems APF28Dev docking/development board"; @@ -41,30 +41,30 @@ hog_pins_apf28dev: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D16__GPIO_1_16 - MX28_PAD_LCD_D17__GPIO_1_17 - MX28_PAD_LCD_D18__GPIO_1_18 - MX28_PAD_LCD_D19__GPIO_1_19 - MX28_PAD_LCD_D20__GPIO_1_20 - MX28_PAD_LCD_D21__GPIO_1_21 - MX28_PAD_LCD_D22__GPIO_1_22 + 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */ + 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */ + 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */ + 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */ + 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */ + 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ + 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_apf28dev: lcdif-apf28dev@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index 6f254ca..0e7fed4 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -1,5 +1,5 @@ /dts-v1/; -#include "imx28.dtsi" +/include/ "imx28.dtsi" / { model = "Bluegiga APX4 Development Kit"; @@ -40,53 +40,53 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_RDY1__GPIO_0_21 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_JTAG_RTCK__GPIO_4_20 + 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ + 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ + 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ + 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_apx4: lcdif-apx4@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_SSP0_DATA7__SSP2_SCK - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 + 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ + 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ + 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ + 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <2>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index cabb617..1ec8c94 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx28.dtsi" +/include/ "imx28.dtsi" / { model = "Crystalfontz CFA-10036 Board"; @@ -26,31 +26,31 @@ ssd1306_cfa10036: ssd1306-10036@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 + 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; led_pins_cfa10036: leds-10036@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 + 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; usb0_otg_cfa10036: otg-10036@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__USB0_ID + 0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts index f93e9a7..182b99f 100644 --- a/arch/arm/boot/dts/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/imx28-cfa10037.dts @@ -13,7 +13,7 @@ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -#include "imx28-cfa10036.dts" +/include/ "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10037 Board"; @@ -25,21 +25,21 @@ usb_pins_cfa10037: usb-10037@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; mac0_pins_cfa10037: mac0-10037@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 + 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 7087b4b..06e4cfa 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -13,7 +13,7 @@ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -#include "imx28-cfa10036.dts" +/include/ "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10049 Board"; @@ -25,150 +25,150 @@ usb_pins_cfa10049: usb-10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; i2cmux_pins_cfa10049: i2cmux-10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_LCD_D23__GPIO_1_23 + 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ + 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; mac0_pins_cfa10049: mac0-10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 + 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; pca_pins_cfa10049: pca-10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 + 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; rotary_pins_cfa10049: rotary-10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 + 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ + 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; rotary_btn_pins_cfa10049: rotary-btn-10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__GPIO_3_26 + 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; spi2_pins_cfa10049: spi2-cfa10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 + 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ + 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ + 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; spi3_pins_cfa10049: spi3-cfa10049@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPIO_0_24 - MX28_PAD_GPMI_RESETN__GPIO_0_28 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_ALE__GPIO_0_26 - MX28_PAD_GPMI_CLE__GPIO_0_27 + 0x0183 /* MX28_PAD_GPMI_RDN__GPIO_0_24 */ + 0x01c3 /* MX28_PAD_GPMI_RESETN__GPIO_0_28 */ + 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ + 0x01a3 /* MX28_PAD_GPMI_ALE__GPIO_0_26 */ + 0x01b3 /* MX28_PAD_GPMI_CLE__GPIO_0_27 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10049: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; w1_gpio_pins: w1-gpio@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 + 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; /* 0 will enable the keeper */ + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <0>; /* 0 will enable the keeper */ }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index c3900e7..171bcbe 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -14,7 +14,7 @@ * The CFA-10055 is an expansion board for the CFA-10036 module and * CFA-10037, thus we need to include the CFA-10037 DTS. */ -#include "imx28-cfa10037.dts" +/include/ "imx28-cfa10037.dts" / { model = "Crystalfontz CFA-10055 Board"; @@ -26,64 +26,64 @@ spi2_pins_cfa10055: spi2-cfa10055@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 + 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ + 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ + 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10055: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index cef959a..b45dd0e 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -13,7 +13,7 @@ * The CFA-10055 is an expansion board for the CFA-10036 module and * CFA-10037, thus we need to include the CFA-10037 DTS. */ -#include "imx28-cfa10037.dts" +/include/ "imx28-cfa10037.dts" / { model = "Crystalfontz CFA-10056 Board"; @@ -25,37 +25,37 @@ spi2_pins_cfa10056: spi2-cfa10056@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 + 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ + 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ + 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; lcdif_pins_cfa10056: lcdif-10056@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 3c13128..0333c05 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -14,7 +14,7 @@ * The CFA-10057 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -#include "imx28-cfa10036.dts" +/include/ "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10057 Board"; @@ -26,51 +26,51 @@ usb_pins_cfa10057: usb-10057@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10057: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 2469d34..64c64c5 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -14,7 +14,7 @@ * The CFA-10058 is an expansion board for the CFA-10036 module, thus we * need to include the CFA-10036 DTS. */ -#include "imx28-cfa10036.dts" +/include/ "imx28-cfa10036.dts" / { model = "Crystalfontz CFA-10058 Board"; @@ -26,24 +26,24 @@ usb_pins_cfa10058: usb-10058@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 + 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_cfa10058: lcdif-10058@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 4267c2b..15715d9 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx28.dtsi" +/include/ "imx28.dtsi" / { model = "Freescale i.MX28 Evaluation Kit"; @@ -70,52 +70,52 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP1_DATA3__GPIO_2_15 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 + 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ + 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */ + 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */ + 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ + 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; led_pin_gpio3_5: led_gpio3_5@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART1_TX__GPIO_3_5 + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; gpmi_pins_evk: gpmi-nand-evk@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPMI_CE1N - MX28_PAD_GPMI_RDY1__GPMI_READY1 + 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_evk: lcdif-evk@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; @@ -182,12 +182,7 @@ }; lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; }; i2c0: i2c@80058000 { @@ -247,8 +242,6 @@ ahb@80080000 { usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_a>; vbus-supply = <®_usb0_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts deleted file mode 100644 index d3958da..0000000 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "MSR M28CU3"; - compatible = "msr,m28cu3", "fsl,imx28"; - - memory { - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - gpmi-nand@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "gpmi-nfc-0-boot"; - reg = <0x00000000 0x01400000>; - read-only; - }; - - partition@1 { - label = "gpmi-nfc-general-use"; - reg = <0x01400000 0x0ec00000>; - }; - }; - - ssp0: ssp@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: ssp@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_a - &mmc2_cd_cfg - &mmc2_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd1>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - MX28_PAD_PWM4__GPIO_3_29 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_RESET__LCD_RESET - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - led_pins_gpio: leds-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SCK__GPIO_2_24 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - }; - - ocotp@8002c000 { - status = "okay"; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display>; - reset-active-high; - status = "okay"; - - display: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <6410256>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hfront-porch = <20>; - vback-porch = <15>; - vfront-porch = <5>; - hsync-len = <30>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usbphy1_pins_a>; - disable-over-current; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 0>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_gpio>; - - user1 { - label = "sd0-led"; - gpios = <&gpio2 26 0>; - linux,default-trigger = "mmc0"; - }; - - user2 { - label = "sd1-led"; - gpios = <&gpio2 24 0>; - linux,default-trigger = "mmc2"; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 0>; - }; - - reg_vddio_sd1: vddio-sd1 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 0>; - }; - - reg_usb1_vbus: usb1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 8e2477f..0d322a2 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx28.dtsi" +/include/ "imx28.dtsi" / { model = "DENX M28EVK"; @@ -92,26 +92,26 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_AUART2_CTS__GPIO_3_10 - MX28_PAD_AUART2_RTS__GPIO_3_11 - MX28_PAD_AUART3_RX__GPIO_3_12 - MX28_PAD_AUART3_TX__GPIO_3_13 + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ + 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ + 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_pins_m28: lcdif-m28@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE + 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ + 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h deleted file mode 100644 index e11f69b..0000000 --- a/arch/arm/boot/dts/imx28-pinfunc.h +++ /dev/null @@ -1,506 +0,0 @@ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ -#define __DT_BINDINGS_MX28_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -#define MX28_PAD_LCD_D00__LCD_D0 0x1000 -#define MX28_PAD_LCD_D01__LCD_D1 0x1010 -#define MX28_PAD_LCD_D02__LCD_D2 0x1020 -#define MX28_PAD_LCD_D03__LCD_D3 0x1030 -#define MX28_PAD_LCD_D04__LCD_D4 0x1040 -#define MX28_PAD_LCD_D05__LCD_D5 0x1050 -#define MX28_PAD_LCD_D06__LCD_D6 0x1060 -#define MX28_PAD_LCD_D07__LCD_D7 0x1070 -#define MX28_PAD_LCD_D08__LCD_D8 0x1080 -#define MX28_PAD_LCD_D09__LCD_D9 0x1090 -#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX28_PAD_LCD_D16__LCD_D16 0x1100 -#define MX28_PAD_LCD_D17__LCD_D17 0x1110 -#define MX28_PAD_LCD_D18__LCD_D18 0x1120 -#define MX28_PAD_LCD_D19__LCD_D19 0x1130 -#define MX28_PAD_LCD_D20__LCD_D20 0x1140 -#define MX28_PAD_LCD_D21__LCD_D21 0x1150 -#define MX28_PAD_LCD_D22__LCD_D22 0x1160 -#define MX28_PAD_LCD_D23__LCD_D23 0x1170 -#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 -#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -#define MX28_PAD_PWM0__PWM_0 0x3100 -#define MX28_PAD_PWM1__PWM_1 0x3110 -#define MX28_PAD_PWM2__PWM_2 0x3120 -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -#define MX28_PAD_PWM3__PWM_3 0x31c0 -#define MX28_PAD_PWM4__PWM_4 0x31d0 -#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 -#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 -#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 -#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -#define MX28_PAD_PWM0__I2C1_SCL 0x3101 -#define MX28_PAD_PWM1__I2C1_SDA 0x3111 -#define MX28_PAD_PWM2__USB0_ID 0x3121 -#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 -#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 -#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 -#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 -#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 -#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 -#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 -#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 -#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 -#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 -#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 -#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 -#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 -#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 -#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 -#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 -#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 -#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 -#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -#define MX28_PAD_AUART1_RX__PWM_0 0x3042 -#define MX28_PAD_AUART1_TX__PWM_1 0x3052 -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -#define MX28_PAD_PWM0__DUART_RX 0x3102 -#define MX28_PAD_PWM1__DUART_TX 0x3112 -#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -#define MX28_PAD_PWM0__GPIO_3_16 0x3103 -#define MX28_PAD_PWM1__GPIO_3_17 0x3113 -#define MX28_PAD_PWM2__GPIO_3_18 0x3123 -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 -#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 -#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 4870f07..6c6a544 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "imx28.dtsi" +/include/ "imx28.dtsi" / { model = "SchulerControl GmbH, SC SPS 1"; @@ -29,13 +29,13 @@ hog_pins_a: hog-gpios@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPIO_0_0 - MX28_PAD_GPMI_D03__GPIO_0_3 - MX28_PAD_GPMI_D06__GPIO_0_6 + 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */ + 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */ + 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index be5a055..37be532 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -1,139 +1,106 @@ -/* - * Copyright 2012 Shawn Guo <shawn.guo@linaro.org> - * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - /dts-v1/; -#include "imx28.dtsi" -#include <dt-bindings/gpio/gpio.h> +/include/ "imx28.dtsi" / { model = "Ka-Ro electronics TX28 module"; compatible = "karo,tx28", "fsl,imx28"; - aliases { - can0 = &can0; - can1 = &can1; - display = &display; - ds1339 = &ds1339; - gpio5 = &gpio5; - lcdif = &lcdif; - lcdif_23bit_pins = &tx28_lcdif_23bit_pins; - lcdif_24bit_pins = &lcdif_24bit_pins_a; - stk5led = &user_led; - usbotg = &usb0; - }; - memory { - reg = <0 0>; /* will be filled in by U-Boot */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio2 7 0>; - status = "disabled"; - }; - - regulators { - compatible = "simple-bus"; - - reg_usb0_vbus: usb0_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 0>; - enable-active-high; - }; + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; - reg_usb1_vbus: usb1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 0>; - enable-active-high; + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mac0_pins_gpio: mac0-gpio-mode@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ + 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ + 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ + 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ + 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ + 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ + 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ + 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ + 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + ds1339: rtc@68 { + compatible = "mxim,ds1339"; + reg = <0x68>; + }; + }; - reg_can_xcvr: can-xcvr { - compatible = "regulator-fixed"; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 0>; - enable-active-low; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_flexcan_xcvr_pins>; - }; + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; + }; - reg_lcd: lcd-power { - compatible = "regulator-fixed"; - regulator-name = "LCD POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 0>; - enable-active-high; - }; + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; + }; - reg_lcd_reset: lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "LCD RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; - startup-delay-us = <300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; + }; }; }; - clocks { - #address-cells = <1>; - #size-cells = <0>; - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <27000000>; + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default", "gpio_mode"; + pinctrl-0 = <&mac0_pins_a>; + pinctrl-1 = <&mac0_pins_gpio>; + status = "okay"; }; }; - sound { - compatible = "fsl,imx28-tx28-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-tx28-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - leds { compatible = "gpio-leds"; - user_led: user { + user { label = "Heartbeat"; gpios = <&gpio4 10 0>; linux,default-trigger = "heartbeat"; @@ -142,512 +109,8 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 0 500000>; - /* - * a silly way to create a 1:1 relationship between the - * PWM value and the actual duty cycle - */ - brightness-levels = < 0 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 - 20 21 22 23 24 25 26 27 28 29 - 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 - 70 71 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 88 89 - 90 91 92 93 94 95 96 97 98 99 - 100>; - default-brightness-level = <50>; - }; - - matrix_keypad: matrix-keypad@0 { - compatible = "gpio-matrix-keypad"; - col-gpios = < - &gpio5 0 0 - &gpio5 1 0 - &gpio5 2 0 - &gpio5 3 0 - >; - row-gpios = < - &gpio5 4 0 - &gpio5 5 0 - &gpio5 6 0 - &gpio5 7 0 - >; - /* sample keymap */ - linux,keymap = < - 0x00000074 /* row 0, col 0, KEY_POWER */ - 0x00010052 /* row 0, col 1, KEY_KP0 */ - 0x0002004f /* row 0, col 2, KEY_KP1 */ - 0x00030050 /* row 0, col 3, KEY_KP2 */ - 0x01000051 /* row 1, col 0, KEY_KP3 */ - 0x0101004b /* row 1, col 1, KEY_KP4 */ - 0x0102004c /* row 1, col 2, KEY_KP5 */ - 0x0103004d /* row 1, col 3, KEY_KP6 */ - 0x02000047 /* row 2, col 0, KEY_KP7 */ - 0x02010048 /* row 2, col 1, KEY_KP8 */ - 0x02020049 /* row 2, col 2, KEY_KP9 */ - >; - gpio-activelow; - linux,wakeup; - debounce-delay-ms = <100>; - col-scan-delay-us = <5000>; - linux,no-autorepeat; - }; -}; - -/* 2nd TX-Std UART - (A)UART1 */ -&auart1 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; -}; - -/* 3rd TX-Std UART - (A)UART3 */ -&auart3 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; -}; - -&can0 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_xcvr>; - status = "okay"; -}; - -&digctl { - status = "okay"; -}; - -/* 1st TX-Std UART - (D)UART */ -&duart { - pinctrl-names = "default"; - pinctrl-0 = <&duart_4pins_a>; - status = "okay"; -}; - -&gpmi { - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - clock-frequency = <400000>; - status = "okay"; - - sgtl5000: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - clocks = <&mclk>; - }; - - gpio5: pca953x@20 { - compatible = "nxp,pca9554"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_pca9554_pins>; - interrupt-parent = <&gpio3>; - interrupts = <28 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_edt_ft5x06_pins>; - interrupt-parent = <&gpio2>; - interrupts = <5 0>; - reset-gpios = <&gpio2 6 1>; - wake-gpios = <&gpio4 9 0>; - }; - - touchscreen: tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tx28_tsc2007_pins>; - interrupt-parent = <&gpio3>; - interrupts = <20 0>; - pendown-gpio = <&gpio3 20 1>; - ti,x-plate-ohms = /bits/ 16 <660>; - }; - - ds1339: rtc@68 { - compatible = "mxim,ds1339"; - reg = <0x68>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; - lcd-supply = <®_lcd>; - display = <&display>; - status = "okay"; - - display: display@0 { - bits-per-pixel = <32>; - bus-width = <24>; - display-timings { - native-mode = <&timing5>; - timing0: timing0 { - panel-name = "VGA"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hsync-len = <96>; - hfront-porch = <16>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing1: timing1 { - panel-name = "ETV570"; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <114>; - hsync-len = <30>; - hfront-porch = <16>; - vback-porch = <32>; - vsync-len = <3>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing2: timing2 { - panel-name = "ET0350"; - clock-frequency = <6500000>; - hactive = <320>; - vactive = <240>; - hback-porch = <34>; - hsync-len = <34>; - hfront-porch = <20>; - vback-porch = <15>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing3: timing3 { - panel-name = "ET0430"; - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hback-porch = <2>; - hsync-len = <41>; - hfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - vfront-porch = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing4: timing4 { - panel-name = "ET0500", "ET0700"; - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hsync-len = <128>; - hfront-porch = <40>; - vback-porch = <33>; - vsync-len = <2>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - timing5: timing5 { - panel-name = "ETQ570"; - clock-frequency = <6400000>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hsync-len = <30>; - hfront-porch = <30>; - vback-porch = <16>; - vsync-len = <3>; - vfront-porch = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; -}; - -&lradc { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; -}; - -&mac0 { - phy-mode = "rmii"; - pinctrl-names = "default", "gpio_mode"; - pinctrl-0 = <&mac0_pins_a>; - pinctrl-1 = <&tx28_mac0_pins_gpio>; - status = "okay"; -}; - -&mac1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - /* not enabled by default */ -}; - -&mxs_rtc { - status = "okay"; -}; - -&ocotp { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */ - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins { - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */ - MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */ - MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */ - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins { - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__GPIO_1_0 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_lcdif_23bit_pins: tx28-lcdif-23bit { - fsl,pinmux-ids = < - /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */ - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl { - fsl,pinmux-ids = < - MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */ - MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */ - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_mac0_pins_gpio: tx28-mac0-gpio-pins { - fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__GPIO_4_0 - MX28_PAD_ENET0_MDIO__GPIO_4_1 - MX28_PAD_ENET0_RX_EN__GPIO_4_2 - MX28_PAD_ENET0_RXD0__GPIO_4_3 - MX28_PAD_ENET0_RXD1__GPIO_4_4 - MX28_PAD_ENET0_TX_EN__GPIO_4_6 - MX28_PAD_ENET0_TXD0__GPIO_4_7 - MX28_PAD_ENET0_TXD1__GPIO_4_8 - MX28_PAD_ENET_CLK__GPIO_4_16 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_pca9554_pins: tx28-pca9554-pins { - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_tsc2007_pins: tx28-tsc2007-pins { - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - - tx28_usbphy0_pins: tx28-usbphy0-pins { - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */ - MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */ - >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - tx28_usbphy1_pins: tx28-usbphy1-pins { - fsl,pinmux-ids = < - MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */ - MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */ - >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; -}; - -&saif0 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_b>; - fsl,saif-master; - status = "okay"; -}; - -&saif1 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - status = "okay"; -}; - -&ssp0 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default", "special"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; -}; - -&ssp3 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins_a>; - clock-frequency = <57600000>; - status = "okay"; - - spidev0: spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <57600000>; - }; - - spidev1: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <57600000>; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; }; }; - -&usb0 { - vbus-supply = <®_usb0_vbus>; - disable-over-current; - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb1 { - vbus-supply = <®_usb1_vbus>; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbphy0 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy0_pins>; - phy_type = "utmi"; - status = "okay"; -}; - -&usbphy1 { - pinctrl-names = "default"; - pinctrl-0 = <&tx28_usbphy1_pins>; - phy_type = "utmi"; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index cda19c8..7363fde 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -9,8 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "skeleton.dtsi" -#include "imx28-pinfunc.h" +/include/ "skeleton.dtsi" / { interrupt-parent = <&icoll>; @@ -208,579 +207,538 @@ duart_pins_a: duart@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM0__DUART_RX - MX28_PAD_PWM1__DUART_TX + 0x3102 /* MX28_PAD_PWM0__DUART_RX */ + 0x3112 /* MX28_PAD_PWM1__DUART_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; duart_pins_b: duart@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; duart_4pins_a: duart-4pins@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART0_CTS__DUART_RX - MX28_PAD_AUART0_RTS__DUART_TX - MX28_PAD_AUART0_RX__DUART_CTS - MX28_PAD_AUART0_TX__DUART_RTS + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ + 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPMI_D0 - MX28_PAD_GPMI_D01__GPMI_D1 - MX28_PAD_GPMI_D02__GPMI_D2 - MX28_PAD_GPMI_D03__GPMI_D3 - MX28_PAD_GPMI_D04__GPMI_D4 - MX28_PAD_GPMI_D05__GPMI_D5 - MX28_PAD_GPMI_D06__GPMI_D6 - MX28_PAD_GPMI_D07__GPMI_D7 - MX28_PAD_GPMI_CE0N__GPMI_CE0N - MX28_PAD_GPMI_RDY0__GPMI_READY0 - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_ALE__GPMI_ALE - MX28_PAD_GPMI_CLE__GPMI_CLE - MX28_PAD_GPMI_RESETN__GPMI_RESETN + 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ + 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ + 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ + 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ + 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ + 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ + 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ + 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ + 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ + 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ + 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; gpmi_status_cfg: gpmi-status-cfg { fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPMI_RDN - MX28_PAD_GPMI_WRN__GPMI_WRN - MX28_PAD_GPMI_RESETN__GPMI_RESETN + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,drive-strength = <2>; }; auart0_pins_a: auart0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX - MX28_PAD_AUART0_CTS__AUART0_CTS - MX28_PAD_AUART0_RTS__AUART0_RTS + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ + 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart0_2pins_a: auart0-2pins@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__AUART0_RX - MX28_PAD_AUART0_TX__AUART0_TX + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart1_pins_a: auart1@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX - MX28_PAD_AUART1_CTS__AUART1_CTS - MX28_PAD_AUART1_RTS__AUART1_RTS + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ + 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart1_2pins_a: auart1-2pins@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__AUART1_RX - MX28_PAD_AUART1_TX__AUART1_TX + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart2_2pins_a: auart2-2pins@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__AUART2_RX - MX28_PAD_SSP2_MOSI__AUART2_TX + 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ + 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart2_2pins_b: auart2-2pins@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__AUART2_RX - MX28_PAD_AUART2_TX__AUART2_TX + 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */ + 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart3_pins_a: auart3@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX - MX28_PAD_AUART3_CTS__AUART3_CTS - MX28_PAD_AUART3_RTS__AUART3_RTS + 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ + 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ + 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ + 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart3_2pins_a: auart3-2pins@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_MISO__AUART3_RX - MX28_PAD_SSP2_SS0__AUART3_TX + 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ + 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart3_2pins_b: auart3-2pins@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_AUART3_RX__AUART3_RX - MX28_PAD_AUART3_TX__AUART3_TX + 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ + 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; auart4_2pins_a: auart4@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP3_SCK__AUART4_TX - MX28_PAD_SSP3_MOSI__AUART4_RX + 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */ + 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; mac0_pins_a: mac0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_ENET0_MDC__ENET0_MDC - MX28_PAD_ENET0_MDIO__ENET0_MDIO - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN - MX28_PAD_ENET0_RXD0__ENET0_RXD0 - MX28_PAD_ENET0_RXD1__ENET0_RXD1 - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN - MX28_PAD_ENET0_TXD0__ENET0_TXD0 - MX28_PAD_ENET0_TXD1__ENET0_TXD1 - MX28_PAD_ENET_CLK__CLKCTRL_ENET + 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ + 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ + 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ + 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ + 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ + 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ + 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ + 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ + 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mac1_pins_a: mac1@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_ENET0_CRS__ENET1_RX_EN - MX28_PAD_ENET0_RXD2__ENET1_RXD0 - MX28_PAD_ENET0_RXD3__ENET1_RXD1 - MX28_PAD_ENET0_COL__ENET1_TX_EN - MX28_PAD_ENET0_TXD2__ENET1_TXD0 - MX28_PAD_ENET0_TXD3__ENET1_TXD1 + 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ + 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ + 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ + 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ + 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ + 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ + 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ + 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ + 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mmc0_4bit_pins_a: mmc0-4bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; mmc0_cd_cfg: mmc0-cd-cfg { fsl,pinmux-ids = < - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ >; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,pull-up = <0>; }; mmc0_sck_cfg: mmc0-sck-cfg { fsl,pinmux-ids = < - MX28_PAD_SSP0_SCK__SSP0_SCK + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - mmc2_4bit_pins_a: mmc2-4bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP1_SCK__SSP2_D1 - MX28_PAD_SSP1_CMD__SSP2_D2 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; - }; - - mmc2_cd_cfg: mmc2-cd-cfg { - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__SSP2_CARD_DETECT - >; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - mmc2_sck_cfg: mmc2-sck-cfg { - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <2>; + fsl,pull-up = <0>; }; i2c0_pins_a: i2c0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__I2C0_SCL - MX28_PAD_I2C0_SDA__I2C0_SDA + 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ + 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; i2c0_pins_b: i2c0@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_AUART0_RX__I2C0_SCL - MX28_PAD_AUART0_TX__I2C0_SDA + 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ + 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; i2c1_pins_a: i2c1@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM0__I2C1_SCL - MX28_PAD_PWM1__I2C1_SDA + 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ + 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__SAIF0_MCLK - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 + 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ + 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ + 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ + 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; saif0_pins_b: saif0@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK - MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK - MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 + 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ + 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ + 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; saif1_pins_a: saif1@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 + 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; pwm0_pins_a: pwm0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM0__PWM_0 + 0x3100 /* MX28_PAD_PWM0__PWM_0 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; pwm2_pins_a: pwm2@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM2__PWM_2 + 0x3120 /* MX28_PAD_PWM2__PWM_2 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; pwm3_pins_a: pwm3@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM3__PWM_3 + 0x31c0 /* MX28_PAD_PWM3__PWM_3 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; pwm3_pins_b: pwm3@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__PWM_3 + 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; pwm4_pins_a: pwm4@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_PWM4__PWM_4 + 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - MX28_PAD_LCD_D18__LCD_D18 - MX28_PAD_LCD_D19__LCD_D19 - MX28_PAD_LCD_D20__LCD_D20 - MX28_PAD_LCD_D21__LCD_D21 - MX28_PAD_LCD_D22__LCD_D22 - MX28_PAD_LCD_D23__LCD_D23 + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ + 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ + 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ + 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ + 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ + 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_16bit_pins_a: lcdif-16bit@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; lcdif_sync_pins_a: lcdif-sync@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; can0_pins_a: can0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY2__CAN0_TX - MX28_PAD_GPMI_RDY3__CAN0_RX + 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ + 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; can1_pins_a: can1@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_GPMI_CE2N__CAN1_TX - MX28_PAD_GPMI_CE3N__CAN1_RX + 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ + 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; spi2_pins_a: spi2@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__SSP2_SCK - MX28_PAD_SSP2_MOSI__SSP2_CMD - MX28_PAD_SSP2_MISO__SSP2_D0 - MX28_PAD_SSP2_SS0__SSP2_D3 + 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ + 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ + 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ + 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; }; spi3_pins_a: spi3@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_AUART2_RX__SSP3_D4 - MX28_PAD_AUART2_TX__SSP3_D5 - MX28_PAD_SSP3_SCK__SSP3_SCK - MX28_PAD_SSP3_MOSI__SSP3_CMD - MX28_PAD_SSP3_MISO__SSP3_D0 - MX28_PAD_SSP3_SS0__SSP3_D3 + 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */ + 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */ + 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */ + 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */ + 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */ + 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */ >; - fsl,drive-strength = <MXS_DRIVE_8mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; usbphy0_pins_a: usbphy0@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__USB0_OVERCURRENT + 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; usbphy0_pins_b: usbphy0@1 { reg = <1>; fsl,pinmux-ids = < - MX28_PAD_AUART1_CTS__USB0_OVERCURRENT + 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; usbphy1_pins_a: usbphy1@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_SSP2_SS1__USB1_OVERCURRENT - >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - usb0_id_pins_a: usb0id@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RTS__USB0_ID + 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ >; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; }; }; @@ -944,7 +902,6 @@ interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>; status = "disabled"; - clocks = <&clks 41>; }; spdif: spdif@80054000 { diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index 5a7f552..123fe84 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -16,33 +16,6 @@ model = "Armadeus Systems APF51Dev docking/development board"; compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; - display@di1 { - compatible = "fsl,imx-parallel-display"; - crtcs = <&ipu 0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp1_1>; - - display-timings { - lw700 { - native-mode; - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index be1407c..1d337d9 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -27,20 +27,6 @@ interface-pix-fmt = "rgb24"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu_disp1_1>; - display-timings { - native-mode = <&timing0>; - timing0: dvi { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; }; display@di1 { @@ -49,25 +35,6 @@ interface-pix-fmt = "rgb565"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu_disp2_1>; - status = "disabled"; - display-timings { - native-mode = <&timing1>; - timing1: claawvga { - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <60>; - vback-porch = <10>; - vfront-porch = <10>; - hsync-len = <20>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; }; gpio-keys { @@ -128,7 +95,7 @@ &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; @@ -285,7 +252,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>; + pinctrl-0 = <&pinctrl_uart1_1>; fsl,uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 4bcdd3a..54cee65 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -86,11 +86,6 @@ interrupt-parent = <&tzic>; ranges; - iram: iram@1ffe0000 { - compatible = "mmio-sram"; - reg = <0x1ffe0000 0x20000>; - }; - ipu: ipu@40000000 { #crtc-cells = <1>; compatible = "fsl,imx51-ipu"; @@ -190,7 +185,7 @@ usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; - clocks = <&clks 75>; + clocks = <&clks 124>; clock-names = "main_clk"; status = "okay"; }; @@ -379,14 +374,6 @@ clocks = <&clks 107>; }; - owire: owire@83fa4000 { - compatible = "fsl,imx51-owire", "fsl,imx21-owire"; - reg = <0x83fa4000 0x4000>; - interrupts = <88>; - clocks = <&clks 159>; - status = "disabled"; - }; - ecspi2: ecspi@83fac000 { #address-cells = <1>; #size-cells = <0>; @@ -760,11 +747,6 @@ fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 - >; - }; - - pinctrl_uart1_rtscts_1: uart1rtscts-1 { - fsl,pins = < MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 >; @@ -785,11 +767,6 @@ fsl,pins = < MX51_PAD_EIM_D25__UART3_RXD 0x1c5 MX51_PAD_EIM_D26__UART3_TXD 0x1c5 - >; - }; - - pinctrl_uart3_rtscts_1: uart3rtscts-1 { - fsl,pins = < MX51_PAD_EIM_D27__UART3_RTS 0x1c5 MX51_PAD_EIM_D24__UART3_CTS 0x1c5 >; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 91a5935..e97ddae 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -55,20 +55,19 @@ label = "Power Button"; gpios = <&gpio1 8 0>; linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; }; volume-up { label = "Volume Up"; gpios = <&gpio2 14 0>; linux,code = <115>; /* KEY_VOLUMEUP */ - gpio-key,wakeup; }; volume-down { label = "Volume Down"; gpios = <&gpio2 15 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ - gpio-key,wakeup; }; }; @@ -123,6 +122,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1_1>; + cd-gpios = <&gpio3 13 0>; status = "okay"; }; @@ -136,7 +136,6 @@ pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; - bus-width = <8>; status = "okay"; }; @@ -153,6 +152,7 @@ MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 + MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 @@ -318,6 +318,5 @@ }; &usbotg { - dr_mode = "peripheral"; - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index 97ed081..9bbe82b 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -536,7 +536,7 @@ #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 @@ -654,7 +654,7 @@ #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index f004913..3530280 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -65,10 +65,8 @@ }; }; -&audmux { +&sata { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux_1>; }; &ecspi1 { @@ -85,27 +83,9 @@ }; }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_1>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; - status = "okay"; -}; - -&i2c1 { +&ssi1 { + fsl,mode = "i2s-slave"; status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clks 201>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; }; &iomuxc { @@ -123,61 +103,28 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 >; }; }; }; -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&ssi1 { - fsl,mode = "i2s-slave"; - status = "okay"; -}; - -&uart2 { - status = "okay"; +&usbotg { + vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; + pinctrl-0 = <&pinctrl_usbotg_1>; + disable-over-current; + status = "okay"; }; &usbh1 { status = "okay"; }; -&usbotg { - vbus-supply = <®_usb_otg_vbus>; +&fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; - disable-over-current; + pinctrl-0 = <&pinctrl_enet_1>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; status = "okay"; }; @@ -198,3 +145,30 @@ vmmc-supply = <®_3p3v>; status = "okay"; }; + +&audmux { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts deleted file mode 100644 index 6e1ccdc..0000000 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -/dts-v1/; -#include "imx6q.dtsi" - -/ { - model = "Udoo i.MX6 Quad Board"; - compatible = "udoo,imx6q-udoo", "fsl,imx6q"; - - memory { - reg = <0x10000000 0x40000000>; - }; -}; - -&sata { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_1>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_2>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index ff6f1e8..1cbbc51 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -54,7 +54,6 @@ fsl,pins = < MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 - MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 >; }; }; @@ -75,10 +74,8 @@ }; &usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3_1>; - pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; cd-gpios = <&gpio6 15 0>; wp-gpios = <&gpio1 13 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index e75e11b..39eafc2 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -80,14 +80,6 @@ mux-int-port = <2>; mux-ext-port = <3>; }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - status = "okay"; - }; }; &audmux { @@ -116,7 +108,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 0>; status = "okay"; }; @@ -181,7 +172,6 @@ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 >; }; }; @@ -212,12 +202,6 @@ }; }; -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_1>; - status = "okay"; -}; - &ssi2 { fsl,mode = "i2s-slave"; status = "okay"; @@ -245,7 +229,6 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_1>; - bus-width = <8>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; status = "okay"; @@ -254,7 +237,6 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3_1>; - bus-width = <8>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 35f5479..a55113e 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -43,13 +43,6 @@ mux-int-port = <1>; mux-ext-port = <3>; }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; }; &audmux { @@ -88,7 +81,6 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 >; }; }; @@ -98,13 +90,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 29 0>; - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_3>; status = "okay"; }; @@ -130,14 +115,6 @@ status = "okay"; }; -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_1>; - disable-over-current; - dr_mode = "peripheral"; - status = "okay"; -}; - &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_2>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index fb28b2e..ccd55c2 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -116,22 +116,6 @@ arm,data-latency = <4 2 3>; }; - pcie: pcie@0x01000000 { - compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x4000>; /* DBI */ - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ - 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <0 123 0x04>; - clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; - status = "disabled"; - }; - pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 94 0x04>; @@ -152,23 +136,8 @@ ranges; spdif: spdif@02004000 { - compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 0x04>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks 197>, <&clks 3>, - <&clks 197>, <&clks 107>, - <&clks 0>, <&clks 118>, - <&clks 0>, <&clks 139>, - <&clks 0>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7"; - status = "disabled"; }; ecspi1: ecspi@02008000 { @@ -1041,12 +1010,6 @@ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 >; }; - - pinctrl_spdif_3: spdifgrp-3 { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 - >; - }; }; uart1 { @@ -1221,36 +1184,6 @@ >; }; - pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - >; - }; - pinctrl_usdhc3_2: usdhc3grp-2 { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index cc68e19..2886a59 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -17,44 +17,6 @@ memory { reg = <0x80000000 0x40000000>; }; - - regulators { - compatible = "simple-bus"; - - reg_usb_otg1_vbus: usb_otg1_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 0>; - enable-active-high; - }; - - reg_usb_otg2_vbus: usb_otg2_vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 0>; - enable-active-high; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 11 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1_1>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32"; - spi-max-frequency = <20000000>; - reg = <0>; - }; }; &fec { @@ -76,8 +38,6 @@ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 >; }; }; @@ -89,26 +49,9 @@ status = "okay"; }; -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_1>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_1>; - pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>; bus-width = <8>; cd-gpios = <&gpio4 7 0>; wp-gpios = <&gpio4 6 0>; @@ -116,20 +59,16 @@ }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_1>; - pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; cd-gpios = <&gpio5 0 0>; wp-gpios = <&gpio4 29 0>; status = "okay"; }; &usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3_1>; - pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; cd-gpios = <&gpio3 22 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 28558f1..c46651e 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -13,20 +13,16 @@ / { aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; }; cpus { @@ -384,9 +380,7 @@ }; anatop: anatop@020c8000 { - compatible = "fsl,imx6sl-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-bus"; + compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; @@ -534,26 +528,10 @@ interrupts = <0 89 0x04>; }; - gpr: iomuxc-gpr@020e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - }; - iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 - >; - }; - }; - fec { pinctrl_fec_1: fecgrp-1 { fsl,pins = < @@ -579,64 +557,6 @@ }; }; - usbotg1 { - pinctrl_usbotg1_1: usbotg1grp-1 { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_2: usbotg1grp-2 { - fsl,pins = < - MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_3: usbotg1grp-3 { - fsl,pins = < - MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_4: usbotg1grp-4 { - fsl,pins = < - MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usbotg1_5: usbotg1grp-5 { - fsl,pins = < - MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059 - >; - }; - }; - - usbotg2 { - pinctrl_usbotg2_1: usbotg2grp-1 { - fsl,pins = < - MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059 - >; - }; - - pinctrl_usbotg2_2: usbotg2grp-2 { - fsl,pins = < - MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059 - >; - }; - - pinctrl_usbotg2_3: usbotg2grp-3 { - fsl,pins = < - MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059 - >; - }; - - pinctrl_usbotg2_4: usbotg2grp-4 { - fsl,pins = < - MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059 - >; - }; - }; - usdhc1 { pinctrl_usdhc1_1: usdhc1grp-1 { fsl,pins = < @@ -652,38 +572,6 @@ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 >; }; - - pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - >; - }; - - }; usdhc2 { @@ -697,29 +585,6 @@ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 >; }; - - pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - }; usdhc3 { @@ -733,28 +598,6 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 >; }; - - pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; }; }; @@ -776,8 +619,7 @@ <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; - /* imx6sl reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; }; pxp: pxp@020f0000 { @@ -821,7 +663,7 @@ usbotg2: usb@02184200 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; - interrupts = <0 42 0x04>; + interrupts = <0 40 0x04>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbphy = <&usbphy2>; fsl,usbmisc = <&usbmisc 1>; @@ -831,7 +673,7 @@ usbh: usb@02184400 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; - interrupts = <0 40 0x04>; + interrupts = <0 42 0x04>; clocks = <&clks IMX6SL_CLK_USBOH3>; fsl,usbmisc = <&usbmisc 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 0f06f86..813b91d 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -5,11 +5,6 @@ /include/ "skeleton.dtsi" / { - core-module@10000000 { - compatible = "arm,core-module-integrator"; - reg = <0x10000000 0x200>; - }; - timer@13000000 { reg = <0x13000000 0x100>; interrupt-parent = <&pic>; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index e6be931..b6b82ec 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -19,11 +19,8 @@ }; syscon { - compatible = "arm,integrator-ap-syscon"; + /* AP system controller registers */ reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logical module IRQs */ - interrupts = <9>, <10>, <11>, <12>; }; timer0: timer@13000000 { diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 7deb3a3..72693a6 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -13,8 +13,8 @@ bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; }; - syscon { - compatible = "arm,integrator-cp-syscon"; + cpcon { + /* CP controller registers */ reg = <0xcb000000 0x100>; }; diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi deleted file mode 100644 index d6713b1..0000000 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ /dev/null @@ -1,821 +0,0 @@ -/* - * Device Tree Source for Keystone 2 clock tree - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - refclkmain: refclkmain { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-main"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclkmain>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; - fixed-postdiv = <2>; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; - clock-output-names = "pa-pll-clk"; - reg = <0x02620358 4>; - reg-names = "control"; - fixed-postdiv = <6>; - }; - - ddr3allclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - fixed-postdiv = <6>; - }; - - ddr3bllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - fixed-postdiv = <6>; - }; - - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - fixed-postdiv = <6>; - }; - - mainmuxclk: mainmuxclk@2310108 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclkmain>; - reg = <0x02310108 4>; - bit-shift = <23>; - bit-mask = <1>; - clock-output-names = "mainmuxclk"; - }; - - chipclk1: chipclk1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1"; - }; - - chipclk1rstiso: chipclk1rstiso { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso"; - }; - - gemtraceclk: gemtraceclk@2310120 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310120 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "gemtraceclk"; - }; - - chipstmxptclk: chipstmxptclk { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310164 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "chipstmxptclk"; - }; - - chipclk12: chipclk12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <2>; - clock-mult = <1>; - clock-output-names = "chipclk12"; - }; - - chipclk13: chipclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk13"; - }; - - chipclk14: chipclk14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk14"; - }; - - chipclk16: chipclk16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk16"; - }; - - chipclk112: chipclk112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk112"; - }; - - chipclk124: chipclk124 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <24>; - clock-mult = <1>; - clock-output-names = "chipclk114"; - }; - - chipclk1rstiso13: chipclk1rstiso13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso13"; - }; - - chipclk1rstiso14: chipclk1rstiso14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso14"; - }; - - chipclk1rstiso16: chipclk1rstiso16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso16"; - }; - - chipclk1rstiso112: chipclk1rstiso112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso112"; - }; - - clkmodrst0: clkmodrst0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "modrst0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkusb: clkusb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemifspi: clkaemifspi { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "aemif-spi"; - reg = <0x0235000c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkdebugsstrc: clkdebugsstrc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "debugss-trc"; - reg = <0x02350014 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clktetbtrc: clktetbtrc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tetb-trc"; - reg = <0x02350018 0xb00>, <0x02350004 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clkpa: clkpa { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "pa"; - reg = <0x0235001c 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkcpgmac: clkcpgmac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "cpgmac"; - reg = <0x02350020 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clksa: clksa { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "sa"; - reg = <0x02350024 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkpcie: clkpcie { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x02350028 0xb00>, <0x0235000c 0x400>; - reg-names = "control", "domain"; - domain-id = <3>; - }; - - clksrio: clksrio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clksr: clksr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso112>; - clock-output-names = "sr"; - reg = <0x02350034 0xb00>, <0x02350018 0x400>; - reg-names = "control", "domain"; - domain-id = <6>; - }; - - clkmsmcsram: clkmsmcsram { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "msmcsram"; - reg = <0x02350038 0xb00>, <0x0235001c 0x400>; - reg-names = "control", "domain"; - domain-id = <7>; - }; - - clkgem0: clkgem0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem0"; - reg = <0x0235003c 0xb00>, <0x02350020 0x400>; - reg-names = "control", "domain"; - domain-id = <8>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr30: clkddr30 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "ddr3-0"; - reg = <0x0235005c 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clkddr31: clkddr31 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clktac01 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clktac23 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x0235000a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkwdtimer0: clkwdtimer0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer1: clkwdtimer1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer2: clkwdtimer2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer3: clkwdtimer3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart0: clkuart0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart1: clkuart1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemif: clkaemif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "aemif"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkusim: clkusim { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "usim"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clki2c: clki2c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "i2c"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkspi: clkspi { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "spi"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkgpio: clkgpio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "gpio"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkkeymgr: clkkeymgr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "keymgr"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts index 100bdf5..a68e34b 100644 --- a/arch/arm/boot/dts/keystone.dts +++ b/arch/arm/boot/dts/keystone.dts @@ -100,15 +100,13 @@ reg = <0x023100e8 4>; /* pll reset control reg */ }; - /include/ "keystone-clocks.dtsi" - uart0: serial@02530c00 { compatible = "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; + clock-frequency = <133120000>; interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; @@ -118,66 +116,9 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02531000 0x100>; - clocks = <&clkuart1>; + clock-frequency = <133120000>; interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; }; - i2c0: i2c@2530000 { - compatible = "ti,davinci-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; - }; - - i2c1: i2c@2530400 { - compatible = "ti,davinci-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; - }; - - i2c2: i2c@2530800 { - compatible = "ti,davinci-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; - }; - - spi0: spi@21000400 { - compatible = "ti,dm6441-spi"; - reg = <0x21000400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkspi>; - }; - - spi1: spi@21000600 { - compatible = "ti,dm6441-spi"; - reg = <0x21000600 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkspi>; - }; - - spi2: spi@21000800 { - compatible = "ti,dm6441-spi"; - reg = <0x21000800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkspi>; - }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts index c39dd76..72c4b0a 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -19,6 +19,7 @@ compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts index 701c6b6..36c411d 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -19,6 +19,7 @@ compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 053aa20..c0e2a58 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -39,6 +39,28 @@ status = "ok"; }; + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; + }; + sata@80000 { nr-ports = <2>; status = "okay"; @@ -58,28 +80,6 @@ }; }; -&nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - chip-delay = <25>; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x500000 0x1fb00000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index aefa375..d544f77 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -148,6 +148,44 @@ status = "okay"; nr-ports = <2>; }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x500000>; + }; + + partition@600000 { + label = "ramdisk"; + reg = <0x0600000 0x500000>; + }; + + partition@b00000 { + label = "image"; + reg = <0x0b00000 0x6600000>; + }; + + partition@7100000 { + label = "mini firmware"; + reg = <0x7100000 0xa00000>; + }; + + partition@7b00000 { + label = "config"; + reg = <0x7b00000 0x500000>; + }; + }; }; regulators { @@ -182,44 +220,6 @@ }; }; -&nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 33ff368..59a2117 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -34,6 +34,26 @@ serial@12000 { status = "ok"; }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x0500000 0xfb00000>; + }; + }; }; gpio-leds { compatible = "gpio-leds"; @@ -71,26 +91,6 @@ }; }; -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index a43bebb..6f7c7d7 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -67,6 +67,31 @@ status = "ok"; }; + nand@3000000 { + chip-delay = <40>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "pogoplug"; + reg = <0x0500000 0x2000000>; + }; + + partition@2500000 { + label = "root"; + reg = <0x02500000 0xd800000>; + }; + }; sata@80000 { status = "okay"; nr-ports = <2>; @@ -146,32 +171,6 @@ }; }; -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index d30a91a..6548b9d 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -40,6 +40,26 @@ status = "ok"; }; + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x00100000 0x00400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x00500000 0x1fb00000>; + }; + }; + sata@80000 { status = "okay"; nr-ports = <1>; @@ -77,26 +97,6 @@ }; }; -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index c5fb02f..cb711a3 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -5,7 +5,7 @@ / { model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; memory { device_type = "memory"; @@ -43,7 +43,6 @@ marvell,function = "gpio"; }; }; - serial@12000 { status = "okay"; }; @@ -52,6 +51,28 @@ status = "okay"; nr-ports = <2>; }; + + nand@3000000 { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x600000>; + }; + + partition@700000 { + label = "root"; + reg = <0x0700000 0xf900000>; + }; + + }; }; gpio_keys { @@ -72,7 +93,6 @@ gpios = <&gpio0 28 1>; }; }; - gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green @@ -93,39 +113,13 @@ gpios = <&gpio0 27 0>; }; }; - gpio_poweroff { compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_power_off>; pinctrl-names = "default"; gpios = <&gpio0 24 0>; }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0xe0000>; - }; - partition@e0000 { - label = "u-boot environment"; - reg = <0xe0000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; }; @@ -140,7 +134,6 @@ ð0 { status = "okay"; - ethernet0-port@0 { phy-handle = <ðphy0>; }; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 4a62b20..0323f01 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -19,6 +19,7 @@ }; mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; @@ -82,6 +83,35 @@ serial@12000 { status = "ok"; }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0xc0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + }; + + partition@100000 { + label = "zImage"; + reg = <0x100000 0x300000>; + }; + + partition@540000 { + label = "initrd"; + reg = <0x540000 0x300000>; + }; + + partition@980000 { + label = "boot"; + reg = <0x980000 0x1f400000>; + }; + }; }; gpio-leds { @@ -150,35 +180,6 @@ }; }; -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index d15395d..df84474 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -113,6 +113,31 @@ status = "ok"; }; + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "uInitrd"; + reg = <0x540000 0x1000000>; + }; + }; sata@80000 { status = "okay"; nr-ports = <2>; @@ -170,32 +195,6 @@ }; }; -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { - label = "uInitrd"; - reg = <0x540000 0x1000000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index cd44f37..6899408 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -34,6 +34,13 @@ serial@12000 { status = "ok"; }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "ok"; + chip-delay = <25>; + }; }; i2c@0 { @@ -44,13 +51,6 @@ }; }; -&nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "ok"; - chip-delay = <25>; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 6c1ec27..ce2b94b 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -17,6 +17,7 @@ }; mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; @@ -95,6 +96,37 @@ pinctrl-names = "default"; }; + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "fdt"; + reg = <0x180000 0x80000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x400000>; + }; + + partition@600000 { + label = "rootfs"; + reg = <0x600000 0x1fa00000>; + }; + }; + rtc@10300 { status = "disabled"; }; @@ -162,37 +194,6 @@ }; }; -&nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "env"; - reg = <0x100000 0x80000>; - }; - - partition@180000 { - label = "fdt"; - reg = <0x180000 0x80000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x400000>; - }; - - partition@600000 { - label = "rootfs"; - reg = <0x600000 0x1fa00000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index e6a102c..874857e 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -17,6 +17,7 @@ }; mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; @@ -97,6 +98,36 @@ status = "okay"; }; + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "jffs2"; + reg = <0x1800000 0x6800000>; + }; + }; + sata@80000 { status = "okay"; nr-ports = <2>; @@ -177,36 +208,6 @@ }; }; -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - read-only; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "minirootfs"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "jffs2"; - reg = <0x1800000 0x6800000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi index e3f915d..06267a9 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi @@ -27,6 +27,49 @@ nr-ports = <2>; }; + nand@3000000 { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; + reg = <0x0100000 0x0080000>; + }; + partition@180000 { + label = "key_store"; + reg = <0x0180000 0x0080000>; + }; + partition@200000 { + label = "info"; + reg = <0x0200000 0x0080000>; + }; + partition@280000 { + label = "etc"; + reg = <0x0280000 0x0a00000>; + }; + partition@c80000 { + label = "kernel_1"; + reg = <0x0c80000 0x0a00000>; + }; + partition@1680000 { + label = "rootfs1"; + reg = <0x1680000 0x2fc0000>; + }; + partition@4640000 { + label = "kernel_2"; + reg = <0x4640000 0x0a00000>; + }; + partition@5040000 { + label = "rootfs2"; + reg = <0x5040000 0x2fc0000>; + }; + }; + pcie-controller { status = "okay"; @@ -62,46 +105,3 @@ }; }; }; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index b5418bc..7aeae0c 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -15,6 +15,7 @@ }; mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index f0e3d21..85ccf8d 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -29,6 +29,43 @@ pinctrl-names = "default"; }; + nand@3000000 { + chip-delay = <25>; + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x90000>; + }; + + partition@90000 { + label = "env"; + reg = <0x90000 0x44000>; + }; + + partition@d4000 { + label = "test"; + reg = <0xd4000 0x24000>; + }; + + partition@f4000 { + label = "conf"; + reg = <0xf4000 0x400000>; + }; + + partition@4f4000 { + label = "linux"; + reg = <0x4f4000 0x1d20000>; + }; + + partition@2214000 { + label = "user"; + reg = <0x2214000 0x1dec000>; + }; + }; + sata@80000 { nr-ports = <1>; status = "okay"; @@ -130,43 +167,6 @@ }; }; -&nand { - chip-delay = <25>; - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x90000>; - }; - - partition@90000 { - label = "env"; - reg = <0x90000 0x44000>; - }; - - partition@d4000 { - label = "test"; - reg = <0xd4000 0x24000>; - }; - - partition@f4000 { - label = "conf"; - reg = <0xf4000 0x400000>; - }; - - partition@4f4000 { - label = "linux"; - reg = <0x4f4000 0x1d20000>; - }; - - partition@2214000 { - label = "user"; - reg = <0x2214000 0x1dec000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts deleted file mode 100644 index 851fb2a..0000000 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Device Tree file for OpenBlocks A7 board - * - * Copyright (C) 2013 Free Electrons - * - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6282.dtsi" - -/ { - model = "Plat'Home OpenBlocksA7"; - compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - ocp@f1000000 { - serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - }; - - serial@12100 { - status = "ok"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - }; - - sata@80000 { - nr-ports = <1>; - status = "okay"; - }; - - i2c@11100 { - status = "okay"; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; - - s24c02: s24c02@50 { - compatible = "24c02"; - reg = <0x50>; - }; - }; - - pinctrl: pinctrl@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; - pinctrl-names = "default"; - - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11", "mpp15", - "mpp16"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14", "mpp8", - "mpp9"; - marvell,function = "uart1"; - }; - - pmx_sysrst: pmx-sysrst { - marvell,pins = "mpp6"; - marvell,function = "sysrst"; - }; - - pmx_dip_switches: pmx-dip-switches { - marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47"; - marvell,function = "gpio"; - }; - - /* - * Accessible on connector J202. The MPP - * listed below are pin 1-7, pin 8 is unused, - * pin 9 is external reset input and pin 10 is - * ground. - */ - pmx_gpio_header: pmx-gpio-header { - marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28", - "mpp35", "mpp34", "mpp40"; - marvell,function = "gpio"; - }; - - pmx_gpio_init: pmx-init { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_usb_oc: pmx-usb-oc { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_leds: pmx-leds { - marvell,pins = "mpp41", "mpp42", "mpp43"; - marvell,function = "gpio"; - }; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_leds>; - pinctrl-names = "default"; - - led-red { - label = "obsa7:red:stat"; - gpios = <&gpio1 9 1>; - }; - - led-green { - label = "obsa7:green:stat"; - gpios = <&gpio1 10 1>; - }; - - led-yellow { - label = "obsa7:yellow:stat"; - gpios = <&gpio1 11 1>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - pinctrl-0 = <&pmx_gpio_init>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "Init Button"; - linux,code = <116>; - gpios = <&gpio1 6 0>; - }; - }; -}; - -&nand { - chip-delay = <25>; - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "uboot"; - reg = <0x0 0x1c0000>; - }; - - partition@1c0000 { - label = "env"; - reg = <0x1c0000 0x2c0000>; - }; - - partition@480000 { - label = "test"; - reg = <0x480000 0x160000>; - }; - - partition@5e0000 { - label = "conf"; - reg = <0x5e0000 0x540000>; - }; - - partition@b20000 { - label = "linux"; - reg = <0xb20000 0x3d40000>; - }; - - partition@4860000 { - label = "user"; - reg = <0x4860000 0xb7a0000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 1173d7f..5696b63 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -48,6 +48,27 @@ pinctrl-names = "default"; status = "okay"; }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x0500000 0x1fb00000>; + }; + }; }; regulators { @@ -71,27 +92,6 @@ }; }; -&nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 320da67..30842b4 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -90,6 +90,37 @@ pinctrl-names = "default"; }; + nand@3000000 { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + }; + + partition@180000 { + label = "u-boot env"; + reg = <0x0180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "uInitrd"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "rootfs"; + reg = <0x1800000 0xe800000>; + }; + }; + sata@80000 { status = "okay"; nr-ports = <1>; @@ -173,37 +204,6 @@ }; }; -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x180000>; - }; - - partition@180000 { - label = "u-boot env"; - reg = <0x0180000 0x20000>; - }; - - partition@200000 { - label = "uImage"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { - label = "uInitrd"; - reg = <0x0800000 0x1000000>; - }; - - partition@1800000 { - label = "rootfs"; - reg = <0x1800000 0xe800000>; - }; -}; - &mdio { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 345562f..9efcd2d 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -6,6 +6,7 @@ / { mbus { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 8b73c80..1335b2e 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -28,43 +28,16 @@ compatible = "marvell,kirkwood-mbus", "simple-bus"; #address-cells = <2>; #size-cells = <1>; - /* If a board file needs to change this ranges it must replace it completely */ - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */ - MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */ - MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ - >; controller = <&mbusc>; pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - - crypto@0301 { - compatible = "marvell,orion-crypto"; - reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>, - <MBUS_ID(0x03, 0x01) 0 0x800>; - reg-names = "regs", "sram"; - interrupts = <22>; - clocks = <&gate_clk 17>; - status = "okay"; - }; - - nand: nand@012f { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = <MBUS_ID(0x01, 0x2f) 0 0x400>; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - status = "disabled"; - }; }; ocp@f1000000 { compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000>; + ranges = <0x00000000 0xf1000000 0x0100000 + 0xf4000000 0xf4000000 0x0000400 + 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -220,6 +193,20 @@ status = "okay"; }; + nand@3000000 { + #address-cells = <1>; + #size-cells = <1>; + cle = <0>; + ale = <1>; + bank-width = <1>; + compatible = "marvell,orion-nand"; + reg = <0xf4000000 0x400>; + chip-delay = <25>; + /* set partition map and/or chip-delay in board dts */ + clocks = <&gate_clk 7>; + status = "disabled"; + }; + i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; @@ -231,6 +218,16 @@ status = "disabled"; }; + crypto@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xf5000000 0x800>; + reg-names = "regs", "sram"; + interrupts = <22>; + clocks = <&gate_clk 17>; + status = "okay"; + }; + mdio: mdio-bus@72004 { compatible = "marvell,orion-mdio"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 386d428..386d428 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index 93e9f7e..93e9f7e 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h deleted file mode 100644 index c6da987..0000000 --- a/arch/arm/boot/dts/mxs-pinfunc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ -#define __DT_BINDINGS_MXS_PINCTRL_H__ - -/* fsl,drive-strength property */ -#define MXS_DRIVE_4mA 0 -#define MXS_DRIVE_8mA 1 -#define MXS_DRIVE_12mA 2 -#define MXS_DRIVE_16mA 3 - -/* fsl,voltage property */ -#define MXS_VOLTAGE_LOW 0 -#define MXS_VOLTAGE_HIGH 1 - -/* fsl,pull-up property */ -#define MXS_PULL_DISABLE 0 -#define MXS_PULL_ENABLE 1 - -#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi deleted file mode 100644 index f577b7d..0000000 --- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Common file for GPMC connected smsc911x on omaps - * - * Note that the board specifc DTS file needs to specify - * ranges, pinctrl, reg, interrupt parent and interrupts. - */ - -/ { - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; -}; - -&gpmc { - ethernet@gpmc { - compatible = "smsc,lan9221", "smsc,lan9115"; - bank-width = <2>; - gpmc,mux-add-data; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - vddvario-supply = <&vddvario>; - vdd33a-supply = <&vdd33a>; - reg-io-width = <4>; - smsc,save-mac-address; - }; -}; diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi deleted file mode 100644 index 68221fa..0000000 --- a/arch/arm/boot/dts/omap-zoom-common.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Common features on the Zoom debug board - */ - -#include "omap-gpmc-smsc911x.dtsi" - -&gpmc { - ranges = <3 0 0x10000000 0x00000400>, - <7 0 0x2c000000 0x01000000>; - - /* - * Four port TL16CP754C serial port on GPMC, - * they probably share the same GPIO IRQ - * REVISIT: Add timing support from slls644g.pdf - */ - uart@3,0 { - compatible = "ns16550a"; - reg = <3 0 0x100>; - bank-width = <2>; - reg-shift = <1>; - reg-io-width = <1>; - interrupt-parent = <&gpio4>; - interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ - clock-frequency = <1843200>; - current-speed = <115200>; - }; - - ethernet@gpmc { - reg = <7 0 0xff>; - interrupt-parent = <&gpio5>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */ - }; -}; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index d0c5b37..a2bfcde 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -9,7 +9,6 @@ */ #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/omap.h> #include "skeleton.dtsi" @@ -22,8 +21,6 @@ serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; - i2c0 = &i2c1; - i2c1 = &i2c2; }; cpus { @@ -56,28 +53,6 @@ ranges; ti,hwmods = "l3_main"; - aes: aes@480a6000 { - compatible = "ti,omap2-aes"; - ti,hwmods = "aes"; - reg = <0x480a6000 0x50>; - dmas = <&sdma 9 &sdma 10>; - dma-names = "tx", "rx"; - }; - - hdq1w: 1w@480b2000 { - compatible = "ti,omap2420-1w"; - ti,hwmods = "hdq1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - }; - - mailbox: mailbox@48094000 { - compatible = "ti,omap2-mailbox"; - ti,hwmods = "mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - }; - intc: interrupt-controller@1 { compatible = "ti,omap2-intc"; interrupt-controller; @@ -88,7 +63,6 @@ sdma: dma-controller@48056000 { compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; - ti,hwmods = "dma"; reg = <0x48056000 0x1000>; interrupts = <12>, <13>, @@ -99,91 +73,21 @@ #dma-requests = <64>; }; - i2c1: i2c@48070000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48070000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap2-i2c"; - ti,hwmods = "i2c2"; - reg = <0x48072000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; - }; - - mcspi1: mcspi@48098000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi1"; - reg = <0x48098000 0x100>; - interrupts = <65>; - dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 - &sdma 39 &sdma 40 &sdma 41 &sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: mcspi@4809a000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi2"; - reg = <0x4809a000 0x100>; - interrupts = <66>; - dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - rng: rng@480a0000 { - compatible = "ti,omap2-rng"; - ti,hwmods = "rng"; - reg = <0x480a0000 0x50>; - interrupts = <36>; - }; - - sham: sham@480a4000 { - compatible = "ti,omap2-sham"; - ti,hwmods = "sham"; - reg = <0x480a4000 0x64>; - interrupts = <51>; - dmas = <&sdma 13>; - dma-names = "rx"; - }; - uart1: serial@4806a000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart1"; - reg = <0x4806a000 0x2000>; - interrupts = <72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart2"; - reg = <0x4806c000 0x400>; - interrupts = <73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; clock-frequency = <48000000>; }; uart3: serial@4806e000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart3"; - reg = <0x4806e000 0x400>; - interrupts = <74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; clock-frequency = <48000000>; }; diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 34cdecb..224c08f 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -50,15 +50,15 @@ label = "bootloader"; reg = <0 0x20000>; }; - partition@20000 { + partition@0x20000 { label = "params"; reg = <0x20000 0x20000>; }; - partition@40000 { + partition@0x40000 { label = "kernel"; reg = <0x40000 0x200000>; }; - partition@240000 { + partition@0x240000 { label = "file-system"; reg = <0x240000 0x3dc0000>; }; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 60c605d..c8f9c55 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -114,15 +114,6 @@ dma-names = "tx", "rx"; }; - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; - timer1: timer@48028000 { compatible = "ti,omap2420-timer"; reg = <0x48028000 0x400>; @@ -130,19 +121,5 @@ ti,hwmods = "timer1"; ti,timer-alwon; }; - - wd_timer2: wdt@48022000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x48022000 0x80>; - }; }; }; - -&i2c1 { - compatible = "ti,omap2420-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2420-i2c"; -}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index d624345..c535a5a 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -175,25 +175,6 @@ dma-names = "tx", "rx"; }; - mmc1: mmc@4809c000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; - ti,hwmods = "mmc1"; - ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap2-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; - ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - timer1: timer@49018000 { compatible = "ti,omap2420-timer"; reg = <0x49018000 0x400>; @@ -201,35 +182,5 @@ ti,hwmods = "timer1"; ti,timer-alwon; }; - - mcspi3: mcspi@480b8000 { - compatible = "ti,omap2-mcspi"; - ti,hwmods = "mcspi3"; - reg = <0x480b8000 0x100>; - interrupts = <91>; - dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - usb_otg_hs: usb_otg_hs@480ac000 { - compatible = "ti,omap2-musb"; - ti,hwmods = "usb_otg_hs"; - reg = <0x480ac000 0x1000>; - interrupts = <93>; - }; - - wd_timer2: wdt@49016000 { - compatible = "ti,omap2-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x49016000 0x80>; - }; }; }; - -&i2c1 { - compatible = "ti,omap2430-i2c"; -}; - -&i2c2 { - compatible = "ti,omap2430-i2c"; -}; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index df33a50..2816bf6 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -69,23 +69,6 @@ }; }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ - vcc-supply = <&hsusb2_power>; - }; }; &omap3_pmx_wkup { @@ -96,37 +79,6 @@ }; }; -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - >; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ - >; - }; - - hsusbb2_pins: pinmux_hsusbb2_pins { - pinctrl-single,pins = < - 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; -}; - &i2c1 { clock-frequency = <2600000>; @@ -192,12 +144,19 @@ &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; mode = <3>; power = <50>; }; +&omap3_pmx_core { + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; @@ -207,18 +166,3 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 3ba4a62..dfd8310 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -44,6 +44,17 @@ }; }; + /* HS USB Port 2 RESET */ + hsusb2_reset: hsusb2_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 19 0>; /* gpio_147 */ + startup-delay-us = <70000>; + enable-active-high; + }; + /* HS USB Port 2 Power */ hsusb2_power: hsusb2_power_reg { compatible = "regulator-fixed"; @@ -57,18 +68,10 @@ /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ + reset-supply = <&hsusb2_reset>; vcc-supply = <&hsusb2_power>; }; - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; - gpio_keys { compatible = "gpio-keys"; @@ -98,18 +101,18 @@ hsusbb2_pins: pinmux_hsusbb2_pins { pinctrl-single,pins = < - 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ + 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ + 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ + 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ + 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ + 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ + 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ + 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ + 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ + 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ + 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ >; }; @@ -128,12 +131,6 @@ reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; }; }; @@ -183,19 +180,3 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio1_pins>; }; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&vaux2 { - regulator-name = "vdd_ehci"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 4665421..7ef2827 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -125,7 +125,7 @@ nand-bus-width = <16>; gpmc,device-nand; - gpmc,sync-clk-ps = <0>; + gpmc,sync-clki-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts deleted file mode 100644 index 4df68ad..0000000 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-evm-common.dtsi" - - -/ { - model = "TI OMAP37XX EVM (TMDSEVM3730)"; - compatible = "ti,omap3-evm-37xx", "ti,omap36xx"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&omap3_pmx_core { - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - 0x120 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - 0x122 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - 0x124 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - 0x126 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - 0x12e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - 0x150 (PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ - 0x14e (PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: pinmux_smsc911x_pins { - pinctrl-single,pins = < - 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&gpmc { - ranges = <0 0 0x00000000 0x20000000>, - <5 0 0x2c000000 0x01000000>; - - nand@0,0 { - linux,mtd-name= "hynix,h8kds0un0mer-4em"; - reg = <0 0 0>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@0x1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@0x280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "Filesystem"; - reg = <0x780000 0x1f880000>; - }; - }; - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi deleted file mode 100644 index 3007e79..0000000 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Common support for omap3 EVM boards - */ - -#include "omap-gpmc-smsc911x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - leds { - compatible = "gpio-leds"; - ledb { - label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - linux,default-trigger = "default-on"; - }; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 22 0>; /* gpio150 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; -}; - -&twl_gpio { - ti,use-leds; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ethernet@gpmc { - interrupt-parent = <&gpio6>; - interrupts = <16 8>; - reg = <5 0 0xff>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index e10dcd0..7d4329d 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -8,14 +8,68 @@ /dts-v1/; #include "omap34xx.dtsi" -#include "omap3-evm-common.dtsi" / { - model = "TI OMAP35XX EVM (TMDSEVM3530)"; + model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; compatible = "ti,omap3-evm", "ti,omap3"; + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "omap3evm::ledb"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + linux,default-trigger = "default-on"; + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&twl_gpio { + ti,use-leds; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + mode = <3>; + power = <50>; }; diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts deleted file mode 100644 index b9b55c9..0000000 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) 2013 Marek Belisko <marek@goldelico.com> - * - * Based on omap3-beagle-xm.dts - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - aux-button { - label = "aux"; - linux,code = <169>; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; - }; - }; -}; - -&omap3_pmx_core { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; - - /* pressure sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - }; - - /* leds */ - tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gta04_led0: red_aux@0 { - label = "gta04:red:aux"; - reg = <0x0>; - }; - - gta04_led1: green_aux@1 { - label = "gta04:green:aux"; - reg = <0x1>; - }; - - gta04_led3: red_power@3 { - label = "gta04:red:power"; - reg = <0x3>; - linux,default-trigger = "default-on"; - }; - - gta04_led4: green_power@4 { - label = "gta04:green:power"; - reg = <0x4>; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <4>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 165aaf7..2326d11 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -1,5 +1,5 @@ /* - * Common device tree for IGEP boards based on AM/DM37x + * Device Tree Source for IGEP Technology devices * * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> @@ -10,7 +10,7 @@ */ /dts-v1/; -#include "omap36xx.dtsi" +#include "omap34xx.dtsi" / { memory { @@ -24,25 +24,6 @@ ti,mcbsp = <&mcbsp2>; ti,codec = <&twl_audio>; }; - - vdd33: regulator-vdd33 { - compatible = "regulator-fixed"; - regulator-name = "vdd33"; - regulator-always-on; - }; - - lbee1usjyc_vmmc: lbee1usjyc_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&lbee1usjyc_pins>; - compatible = "regulator-fixed"; - regulator-name = "regulator-lbee1usjyc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */ - startup-delay-us = <10000>; - enable-active-high; - vin-supply = <&vdd33>; - }; }; &omap3_pmx_core { @@ -67,15 +48,6 @@ >; }; - /* WiFi/BT combo */ - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */ - 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; - mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ @@ -93,17 +65,10 @@ 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + 0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + 0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + 0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + 0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ >; }; @@ -112,34 +77,9 @@ 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ - 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ - 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ - >; - }; - - leds_pins: pinmux_leds_pins { }; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; clock-frequency = <2600000>; twl: twl@48 { @@ -159,16 +99,9 @@ #include "twl4030_omap3.dtsi" &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; }; -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; -}; - &mcbsp2 { pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; @@ -179,15 +112,11 @@ pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; vmmc_aux-supply = <&vsim>; - bus-width = <4>; + bus-width = <8>; }; &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&lbee1usjyc_vmmc>; - bus-width = <4>; - non-removable; + status = "disabled"; }; &mmc3 { @@ -212,12 +141,3 @@ &twl_gpio { ti,use-leds; }; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 1c7e74d..e8c4828 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) + * Device Tree Source for IGEPv2 board * * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> @@ -10,17 +10,13 @@ */ #include "omap3-igep.dtsi" -#include "omap-gpmc-smsc911x.dtsi" / { - model = "IGEPv2 (TI OMAP AM/DM37x)"; + model = "IGEPv2"; compatible = "isee,omap3-igep0020", "ti,omap3"; leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; compatible = "gpio-leds"; - boot { label = "omap3:green:boot"; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; @@ -45,95 +41,17 @@ }; }; - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ - vcc-supply = <&hsusb1_power>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - &tfp410_pins - &dss_pins - >; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - 0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - 0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; + vddvario: regulator-vddvario { + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; - tfp410_pins: tfp410_dvi_pins { - pinctrl-single,pins = < - 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; + vdd33a: regulator-vdd33a { + compatible = "regulator-fixed"; + regulator-name = "vdd33a"; + regulator-always-on; }; - - dss_pins: pinmux_dss_dvi_pins { - pinctrl-single,pins = < - 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; -}; - -&leds_pins { - pinctrl-single,pins = < - 0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - 0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - 0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ - >; }; &i2c3 { @@ -181,42 +99,59 @@ label = "SPL"; reg = <0 0x100000>; }; - partition@80000 { + partition@0x80000 { label = "U-Boot"; reg = <0x100000 0x180000>; }; - partition@1c0000 { + partition@0x1c0000 { label = "Environment"; reg = <0x280000 0x100000>; }; - partition@280000 { + partition@0x280000 { label = "Kernel"; reg = <0x380000 0x300000>; }; - partition@780000 { + partition@0x780000 { label = "Filesystem"; reg = <0x680000 0x1f980000>; }; }; - ethernet@gpmc { + ethernet@5,0 { pinctrl-names = "default"; pinctrl-0 = <&smsc911x_pins>; + compatible = "smsc,lan9221", "smsc,lan9115"; reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; -}; + bank-width = <2>; -&usbhshost { - port1-mode = "ehci-phy"; -}; + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; -&usbhsehci { - phys = <&hsusb1_phy>; -}; + interrupt-parent = <&gpio6>; + interrupts = <16 8>; + vmmc-supply = <&vddvario>; + vmmc_aux-supply = <&vdd33a>; + reg-io-width = <4>; -&vpll2 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; + smsc,save-mac-address; + }; }; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 02a23f8..644d053 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x) + * Device Tree Source for IGEP COM Module * * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> @@ -12,14 +12,11 @@ #include "omap3-igep.dtsi" / { - model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; + model = "IGEP COM Module"; compatible = "isee,omap3-igep0030", "ti,omap3"; leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; compatible = "gpio-leds"; - boot { label = "omap3:green:boot"; gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; @@ -46,12 +43,6 @@ }; }; -&leds_pins { - pinctrl-single,pins = < - 0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ - >; -}; - &gpmc { ranges = <0 0 0x00000000 0x20000000>; @@ -83,19 +74,19 @@ label = "SPL"; reg = <0 0x100000>; }; - partition@80000 { + partition@0x80000 { label = "U-Boot"; reg = <0x100000 0x180000>; }; - partition@1c0000 { + partition@0x1c0000 { label = "Environment"; reg = <0x280000 0x100000>; }; - partition@280000 { + partition@0x280000 { label = "Kernel"; reg = <0x380000 0x300000>; }; - partition@780000 { + partition@0x780000 { label = "Filesystem"; reg = <0x680000 0x1f980000>; }; diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts deleted file mode 100644 index 39828ce..0000000 --- a/arch/arm/boot/dts/omap3-n9.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* - * omap3-n9.dts - Device Tree file for Nokia N9 - * - * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" - -/ { - model = "Nokia N9"; - compatible = "nokia,omap3-n9", "ti,omap3"; -}; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts deleted file mode 100644 index c2c306d..0000000 --- a/arch/arm/boot/dts/omap3-n900.dts +++ /dev/null @@ -1,505 +0,0 @@ -/* - * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz> - * Copyright 2013 Aaro Koskinen <aaro.koskinen@iki.fi> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 (or later) as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap34xx.dtsi" - -/ { - model = "Nokia N900"; - compatible = "nokia,omap3-n900", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - gpio_keys { - compatible = "gpio-keys"; - - camera_lens_cover { - label = "Camera Lens Cover"; - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */ - gpio-key,wakeup; - }; - - camera_focus { - label = "Camera Focus"; - gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ - linux,code = <0x210>; /* KEY_CAMERA_FOCUS */ - gpio-key,wakeup; - }; - - camera_capture { - label = "Camera Capture"; - gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ - linux,code = <0xd4>; /* KEY_CAMERA */ - gpio-key,wakeup; - }; - - lock_button { - label = "Lock Button"; - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ - linux,code = <0x98>; /* KEY_SCREENLOCK */ - gpio-key,wakeup; - }; - - keypad_slide { - label = "Keypad Slide"; - gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */ - gpio-key,wakeup; - }; - - proximity_sensor { - label = "Proximity Sensor"; - gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */ - }; - }; - -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */ - 0x136 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */ - 0x13a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ - >; - }; - - display_pins: pinmux_display_pins { - pinctrl-single,pins = < - 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <2200000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux1 { - regulator-name = "V28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; /* due battery cover sensor */ -}; - -&vaux2 { - regulator-name = "VCSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vaux3 { - regulator-name = "VMMC2_30"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-name = "VCAM_ANA_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&vmmc1 { - regulator-name = "VMMC1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; -}; - -&vmmc2 { - regulator-name = "V28_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; /* due VIO leak to AIC34 VDDs */ -}; - -&vpll1 { - regulator-name = "VPLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&vpll2 { - regulator-name = "VSDI_CSI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; - -&vsim { - regulator-name = "VMMC2_IO_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&vio { - regulator-name = "VIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - -}; - -&vintana1 { - regulator-name = "VINTANA1"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&vintana2 { - regulator-name = "VINTANA2"; - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; -}; - -&vintdig { - regulator-name = "VINTDIG"; - /* fixed to 1500000 */ - regulator-always-on; -}; - -&twl { - twl_audio: audio { - compatible = "ti,twl4030-audio"; - ti,enable-vibra = <1>; - }; -}; - -&twl_gpio { - ti,pullups = <0x0>; - ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <100000>; - - tlv320aic3x: tlv320aic3x@18 { - compatible = "ti,tlv320aic3x"; - reg = <0x18>; - gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ - ai3x-gpio-func = < - 0 /* AIC3X_GPIO1_FUNC_DISABLED */ - 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ - >; - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - }; - - tlv320aic3x_aux: tlv320aic3x@19 { - compatible = "ti,tlv320aic3x"; - reg = <0x19>; - gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */ - - AVDD-supply = <&vmmc2>; - DRVDD-supply = <&vmmc2>; - IOVDD-supply = <&vio>; - DVDD-supply = <&vio>; - }; - - lp5523: lp5523@32 { - compatible = "national,lp5523"; - reg = <0x32>; - clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - - chan0 { - chan-name = "lp5523:kb1"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan1 { - chan-name = "lp5523:kb2"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan2 { - chan-name = "lp5523:kb3"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan3 { - chan-name = "lp5523:kb4"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan4 { - chan-name = "lp5523:b"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan5 { - chan-name = "lp5523:g"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan6 { - chan-name = "lp5523:r"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan7 { - chan-name = "lp5523:kb5"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - - chan8 { - chan-name = "lp5523:kb6"; - led-cur = /bits/ 8 <50>; - max-cur = /bits/ 8 <100>; - }; - }; - - bq27200: bq27200@55 { - compatible = "ti,bq27200"; - reg = <0x55>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ -}; - -/* most boards use vaux3, only some old versions use vmmc2 instead */ -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vaux3>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; - non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ - - /* gpio-irq for dma: 65 */ - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x10000000>; - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - /* - * MTD partition table corresponding to Nokia's - * Maemo 5 (Fremantle) release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@1 { - label = "config"; - reg = <0x00020000 0x00060000>; - }; - partition@2 { - label = "log"; - reg = <0x00080000 0x00040000>; - }; - partition@3 { - label = "kernel"; - reg = <0x000c0000 0x00200000>; - }; - partition@4 { - label = "initfs"; - reg = <0x002c0000 0x00200000>; - }; - partition@5 { - label = "rootfs"; - reg = <0x004c0000 0x0fb40000>; - }; - }; -}; - -&mcspi1 { - /* - * For some reason, touchscreen is necessary for screen to work at - * all on real hw. It works well without it on emulator. - * - * Also... order in the device tree actually matters here. - */ - tsc2005@0 { - compatible = "tsc2005"; - spi-max-frequency = <6000000>; - reg = <0>; - }; - mipid@2 { - compatible = "acx565akm"; - spi-max-frequency = <6000000>; - reg = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&display_pins>; - }; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <2>; - power = <50>; -}; - -&uart1 { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi deleted file mode 100644 index 94eb77d..0000000 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -/* - * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) - * - * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "omap36xx.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vemmc: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VEMMC"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - gpio = <&gpio5 29 0>; /* gpio line 157 */ - startup-delay-us = <150>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ - 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */ - 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ - 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2900000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -/include/ "twl4030.dtsi" - -&twl { - compatible = "ti,twl5031"; -}; - -&twl_gpio { - ti,pullups = <0x000001>; /* BIT(0) */ - ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&mmc1 { - status = "disabled"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&vemmc>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x20000000>; - - onenand@0,0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x20000000>; - - gpmc,sync-read; - gpmc,sync-write; - gpmc,burst-length = <16>; - gpmc,burst-read; - gpmc,burst-wrap; - gpmc,burst-write; - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; - gpmc,sync-clk-ps = <15000>; - - /* - * MTD partition table corresponding to Nokia's MeeGo 1.2 - * Harmattan release. - */ - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "config"; - reg = <0x00100000 0x002c0000>; - }; - partition@2 { - label = "kernel"; - reg = <0x003c0000 0x01000000>; - }; - partition@3 { - label = "log"; - reg = <0x013c0000 0x00200000>; - }; - partition@4 { - label = "var"; - reg = <0x015c0000 0x1ca40000>; - }; - partition@5 { - label = "moslo"; - reg = <0x1e000000 0x02000000>; - }; - partition@6 { - label = "omap2-onenand"; - reg = <0x00000000 0x20000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts deleted file mode 100644 index b076a52..0000000 --- a/arch/arm/boot/dts/omap3-n950.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* - * omap3-n950.dts - Device Tree file for Nokia N950 - * - * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; - -#include "omap3-n950-n9.dtsi" - -/ { - model = "Nokia N950"; - compatible = "nokia,omap3-n950", "ti,omap3"; -}; diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index a461d2f..8f1abec 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -76,8 +76,6 @@ &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; mode = <3>; power = <50>; }; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts deleted file mode 100644 index 15eb9fe..0000000 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap-zoom-common.dtsi" - -/ { - model = "TI Zoom3"; - compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; - }; - - vdd33a: regulator-vdd33a { - compatible = "regulator-fixed"; - regulator-name = "vdd33a"; - regulator-always-on; - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio4 5 0>; /* gpio101 */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&omap3_pmx_core { - /* REVISIT: twl gpio0 is mmc0_cd */ - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - 0x12c (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - 0x12e (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - 0x130 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - 0x132 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - 0x134 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */ - 0x136 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */ - 0x138 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */ - 0x13a (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - 0x168 (PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ - 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - 0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - 0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ - 0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */ - 0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */ - 0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - 0x150 (PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - 0x14e (PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - 0x152 (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - 0x14c (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - 0x146 (PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - 0x14a (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16a (PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - 0x16c (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - 0xea (PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ - >; - }; -}; - -&omap3_pmx_wkup { - wlan_host_wkup: pinmux_wlan_host_wkup_pins { - pinctrl-single,pins = < - 0x1a (PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; -/* -&mmc2 { - vmmc-supply = <&vmmc2>; - ti,non-removable; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; -*/ -&mmc3 { - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&uart4 { - status = "disabled"; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index daabf99..b41bd57 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -19,9 +19,6 @@ interrupt-parent = <&intc>; aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -40,7 +37,6 @@ pmu { compatible = "arm,cortex-a8-pmu"; - reg = <0x54000000 0x800000>; interrupts = <3>; ti,hwmods = "debugss"; }; @@ -75,20 +71,11 @@ */ ocp { compatible = "simple-bus"; - reg = <0x68000000 0x10000>; - interrupts = <9 10>; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; - aes: aes@480c5000 { - compatible = "ti,omap3-aes"; - ti,hwmods = "aes"; - reg = <0x480c5000 0x50>; - interrupts = <0>; - }; - counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; @@ -120,19 +107,15 @@ reg = <0x48002030 0x05cc>; #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; - omap3_pmx_wkup: pinmux@48002a00 { + omap3_pmx_wkup: pinmux@0x48002a00 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x48002a00 0x5c>; #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; @@ -206,40 +189,24 @@ uart1: serial@4806a000 { compatible = "ti,omap3-uart"; - reg = <0x4806a000 0x2000>; - interrupts = <72>; - dmas = <&sdma 49 &sdma 50>; - dma-names = "tx", "rx"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap3-uart"; - reg = <0x4806c000 0x400>; - interrupts = <73>; - dmas = <&sdma 51 &sdma 52>; - dma-names = "tx", "rx"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@49020000 { compatible = "ti,omap3-uart"; - reg = <0x49020000 0x400>; - interrupts = <74>; - dmas = <&sdma 53 &sdma 54>; - dma-names = "tx", "rx"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; - reg = <0x48070000 0x80>; - interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -247,10 +214,6 @@ i2c2: i2c@48072000 { compatible = "ti,omap3-i2c"; - reg = <0x48072000 0x80>; - interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -258,26 +221,13 @@ i2c3: i2c@48060000 { compatible = "ti,omap3-i2c"; - reg = <0x48060000 0x80>; - interrupts = <61>; - dmas = <&sdma 25 &sdma 26>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; - mailbox: mailbox@48094000 { - compatible = "ti,omap3-mailbox"; - ti,hwmods = "mailbox"; - reg = <0x48094000 0x200>; - interrupts = <26>; - }; - mcspi1: spi@48098000 { compatible = "ti,omap2-mcspi"; - reg = <0x48098000 0x100>; - interrupts = <65>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -296,8 +246,6 @@ mcspi2: spi@4809a000 { compatible = "ti,omap2-mcspi"; - reg = <0x4809a000 0x100>; - interrupts = <66>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -311,8 +259,6 @@ mcspi3: spi@480b8000 { compatible = "ti,omap2-mcspi"; - reg = <0x480b8000 0x100>; - interrupts = <91>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -326,8 +272,6 @@ mcspi4: spi@480ba000 { compatible = "ti,omap2-mcspi"; - reg = <0x480ba000 0x100>; - interrupts = <48>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -336,17 +280,8 @@ dma-names = "tx0", "rx0"; }; - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - ti,hwmods = "hdq1w"; - }; - mmc1: mmc@4809c000 { compatible = "ti,omap3-hsmmc"; - reg = <0x4809c000 0x200>; - interrupts = <83>; ti,hwmods = "mmc1"; ti,dual-volt; dmas = <&sdma 61>, <&sdma 62>; @@ -355,8 +290,6 @@ mmc2: mmc@480b4000 { compatible = "ti,omap3-hsmmc"; - reg = <0x480b4000 0x200>; - interrupts = <86>; ti,hwmods = "mmc2"; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; @@ -364,23 +297,13 @@ mmc3: mmc@480ad000 { compatible = "ti,omap3-hsmmc"; - reg = <0x480ad000 0x200>; - interrupts = <94>; ti,hwmods = "mmc3"; dmas = <&sdma 77>, <&sdma 78>; dma-names = "tx", "rx"; }; - mmu_isp: mmu@480bd400 { - compatible = "ti,omap3-mmu-isp"; - ti,hwmods = "mmu_isp"; - reg = <0x480bd400 0x80>; - interrupts = <8>; - }; - wdt2: wdt@48314000 { compatible = "ti,omap3-wdt"; - reg = <0x48314000 0x80>; ti,hwmods = "wd_timer2"; }; @@ -463,27 +386,6 @@ dma-names = "tx", "rx"; }; - sham: sham@480c3000 { - compatible = "ti,omap3-sham"; - ti,hwmods = "sham"; - reg = <0x480c3000 0x64>; - interrupts = <49>; - }; - - smartreflex_core: smartreflex@480cb000 { - compatible = "ti,omap3-smartreflex-core"; - ti,hwmods = "smartreflex_core"; - reg = <0x480cb000 0x400>; - interrupts = <19>; - }; - - smartreflex_mpu_iva: smartreflex@480c9000 { - compatible = "ti,omap3-smartreflex-iva"; - ti,hwmods = "smartreflex_mpu_iva"; - reg = <0x480c9000 0x400>; - interrupts = <18>; - }; - timer1: timer@48318000 { compatible = "ti,omap3430-timer"; reg = <0x48318000 0x400>; diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 281914e..e2249bc 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -84,15 +84,15 @@ label = "bootloader-nor"; reg = <0 0x40000>; }; - partition@40000 { + partition@0x40000 { label = "params-nor"; reg = <0x40000 0x40000>; }; - partition@80000 { + partition@0x80000 { label = "kernel-nor"; reg = <0x80000 0x200000>; }; - partition@280000 { + partition@0x280000 { label = "filesystem-nor"; reg = <0x240000 0x7d80000>; }; @@ -125,19 +125,19 @@ label = "xloader-nand"; reg = <0 0x80000>; }; - partition@80000 { + partition@0x80000 { label = "bootloader-nand"; reg = <0x80000 0x140000>; }; - partition@1c0000 { + partition@0x1c0000 { label = "params-nand"; reg = <0x1c0000 0xc0000>; }; - partition@280000 { + partition@0x280000 { label = "kernel-nand"; reg = <0x280000 0x500000>; }; - partition@780000 { + partition@0x780000 { label = "filesystem-nand"; reg = <0x780000 0x7880000>; }; @@ -170,19 +170,19 @@ label = "xloader-onenand"; reg = <0 0x80000>; }; - partition@80000 { + partition@0x80000 { label = "bootloader-onenand"; reg = <0x80000 0x40000>; }; - partition@c0000 { + partition@0xc0000 { label = "params-onenand"; reg = <0xc0000 0x20000>; }; - partition@e0000 { + partition@0xe0000 { label = "kernel-onenand"; reg = <0xe0000 0x200000>; }; - partition@2e0000 { + partition@0x2e0000 { label = "filesystem-onenand"; reg = <0x2e0000 0xfd20000>; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 380c22e..f8b3765 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -31,10 +31,6 @@ ocp { uart4: serial@49042000 { compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 88c6a05..814ab67 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -60,6 +60,22 @@ "AFMR", "Line In"; }; + /* + * Temp hack: Need to be replaced with the proper gpio-controlled + * reset driver as soon it will be merged. + * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830 + */ + /* HS USB Port 1 RESET */ + hsusb1_reset: hsusb1_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 30 0>; /* gpio_62 */ + startup-delay-us = <70000>; + enable-active-high; + }; + /* HS USB Port 1 Power */ hsusb1_power: hsusb1_power_reg { compatible = "regulator-fixed"; @@ -81,7 +97,7 @@ /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ + reset-supply = <&hsusb1_reset>; vcc-supply = <&hsusb1_power>; /** * FIXME: @@ -106,19 +122,37 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &mcbsp1_pins - &dss_dpi_pins - &tfp410_pins &dss_hdmi_pins &tpd12s015_pins &hsusbb1_pins >; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ @@ -145,47 +179,6 @@ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - 0x122 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ - 0x124 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ - 0x126 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ - 0x128 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ - 0x12a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ - 0x12c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ - 0x12e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ - 0x130 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ - 0x132 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ - 0x134 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ - 0x136 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ - - 0x174 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ - 0x176 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ - 0x178 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ - 0x17a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ - 0x17c (PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ - 0x17e (PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ - 0x180 (PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ - 0x182 (PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ - 0x184 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ - 0x186 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ - 0x188 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ - 0x18a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ - 0x18c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ - 0x18e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ - - 0x190 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ - 0x192 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ - 0x194 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ - >; - }; - - tfp410_pins: pinmux_tfp410_pins { - pinctrl-single,pins = < - 0x144 (PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ - >; - }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { pinctrl-single,pins = < 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ @@ -246,6 +239,15 @@ 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; +}; + +&omap4_pmx_wkup { + led_wkgpio_pins: pinmux_leds_wkpins { + pinctrl-single,pins = < + 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ + 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ + >; + }; /* * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP @@ -265,7 +267,7 @@ pinctrl-single,pins = < 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ + 0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ @@ -275,15 +277,6 @@ }; }; -&omap4_pmx_wkup { - led_wkgpio_pins: pinmux_leds_wkpins { - pinctrl-single,pins = < - 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ - 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ - >; - }; -}; - &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -312,7 +305,6 @@ }; #include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" &i2c2 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 816d1c9..56c4354 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -62,7 +62,3 @@ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; - -&gpio1 { - ti,no-reset-on-init; -}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index dbc81fb..4f78380 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -155,9 +155,23 @@ }; }; +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_wkup_pins + >; + + twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + pinctrl-single,pins = < + 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ + >; + }; +}; + &omap4_pmx_core { pinctrl-names = "default"; pinctrl-0 = < + &twl6030_pins &twl6040_pins &mcpdm_pins &dmic_pins @@ -192,6 +206,12 @@ >; }; + twl6030_pins: pinmux_twl6030_pins { + pinctrl-single,pins = < + 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ + >; + }; + twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ @@ -300,12 +320,12 @@ wl12xx_pins: pinmux_wl12xx_pins { pinctrl-single,pins = < 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ - 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ - 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ - 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ - 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ - 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ + 0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */ + 0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */ + 0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */ + 0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */ + 0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; }; @@ -350,7 +370,6 @@ }; #include "twl6030.dtsi" -#include "twl6030_omap4.dtsi" &i2c2 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index a1e0585..22d9f2b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -17,10 +17,6 @@ interrupt-parent = <&gic>; aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -60,7 +56,7 @@ cache-level = <2>; }; - local-timer@48240600 { + local-timer@0x48240600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x48240600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; @@ -118,8 +114,6 @@ reg = <0x4a100040 0x0196>; #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; @@ -128,8 +122,6 @@ reg = <0x4a31e040 0x0038>; #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; @@ -222,7 +214,6 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; - ti,no-idle-on-init; }; uart1: serial@4806a000 { @@ -257,12 +248,6 @@ clock-frequency = <48000000>; }; - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - }; - i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; @@ -507,7 +492,6 @@ reg = <0x4c000000 0x100>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "emif1"; - ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; @@ -519,7 +503,6 @@ reg = <0x4d000000 0x100>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "emif2"; - ti,no-idle-on-init; phy-type = <1>; hw-caps-read-idle-ctrl; hw-caps-ll-interface; @@ -536,8 +519,7 @@ usb2_phy: usb2phy@4a0ad080 { compatible = "ti,omap-usb2"; reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb2phy>; - #phy-cells = <0>; + ctrl-module = <&omap_control_usb>; }; }; @@ -661,16 +643,12 @@ }; }; - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usbotg: control-phy@4a00233c { - compatible = "ti,control-phy-otghs"; - reg = <0x4a00233c 0x4>; - reg-names = "otghs_control"; + omap_control_usb: omap-control-usb@4a002300 { + compatible = "ti,omap-control-usb"; + reg = <0x4a002300 0x4>, + <0x4a00233c 0x4>; + reg-names = "control_dev_conf", "otghs_control"; + ti,type = <1>; }; usb_otg_hs: usb_otg_hs@4a0ab000 { @@ -680,30 +658,10 @@ interrupt-names = "mc", "dma"; ti,hwmods = "usb_otg_hs"; usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; multipoint = <1>; num-eps = <16>; ram-bits = <12>; - ctrl-module = <&omap_control_usbotg>; - }; - - aes: aes@4b501000 { - compatible = "ti,omap4-aes"; - ti,hwmods = "aes"; - reg = <0x4b501000 0xa0>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; - }; - - des: des@480a5000 { - compatible = "ti,omap4-des"; - ti,hwmods = "des"; - reg = <0x480a5000 0xa0>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 117>, <&sdma 116>; - dma-names = "tx", "rx"; + ti,has-mailbox; }; }; }; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 002fa70..65d7b60 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -27,10 +27,21 @@ regulator-max-microvolt = <3000000>; }; + /* HS USB Port 2 RESET */ + hsusb2_reset: hsusb2_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ + startup-delay-us = <70000>; + enable-active-high; + }; + /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ + reset-supply = <&hsusb2_reset>; /** * FIXME * Put the right clock phandle here when available @@ -40,10 +51,21 @@ clock-frequency = <19200000>; }; + /* HS USB Port 3 RESET */ + hsusb3_reset: hsusb3_reset_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb3_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ + startup-delay-us = <70000>; + enable-active-high; + }; + /* HS USB Host PHY on PORT 3 */ hsusb3_phy: hsusb3_phy { compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ + reset-supply = <&hsusb3_reset>; }; leds { @@ -62,6 +84,7 @@ pinctrl-0 = < &twl6040_pins &mcpdm_pins + &dmic_pins &mcbsp1_pins &mcbsp2_pins &usbhost_pins @@ -70,7 +93,7 @@ twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < - 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ + 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ >; }; @@ -84,6 +107,15 @@ >; }; + dmic_pins: pinmux_dmic_pins { + pinctrl-single,pins = < + 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ + 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ + 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ + 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ + >; + }; + mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ @@ -121,25 +153,25 @@ 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ + 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ >; }; mcspi3_pins: pinmux_mcspi3_pins { pinctrl-single,pins = < - 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ - 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ - 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ - 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ + 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ + 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ + 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ + 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ >; }; mcspi4_pins: pinmux_mcspi4_pins { pinctrl-single,pins = < - 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */ - 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */ - 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */ - 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */ + 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ + 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ + 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ + 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ >; }; @@ -239,14 +271,6 @@ reg = <0x48>; interrupt-controller; #interrupt-cells = <2>; - ti,system-power-controller; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - }; palmas_pmic { compatible = "ti,palmas-pmic"; @@ -310,22 +334,15 @@ ti,smps-range = <0x80>; }; - smps10_out2_reg: smps10_out2 { + smps10_reg: smps10 { /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; + regulator-name = "smps10"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; }; - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - ldo1_reg: ldo1 { /* VDDAPHY_CAM: vdda_csiport */ regulator-name = "ldo1"; @@ -453,11 +470,6 @@ phys = <0 &hsusb2_phy &hsusb3_phy>; }; -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - &mcspi1 { }; @@ -491,7 +503,3 @@ pinctrl-names = "default"; pinctrl-0 = <&uart5_pins>; }; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fc3fad5..7cdea1b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -21,11 +21,6 @@ interrupt-parent = <&gic>; aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -38,17 +33,10 @@ #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; - - operating-points = < - /* kHz uV */ - 500000 880000 - 1000000 1060000 - 1500000 1250000 - >; }; cpu@1 { device_type = "cpu"; @@ -64,6 +52,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <6144000>; }; gic: interrupt-controller@48211000 { @@ -287,12 +276,6 @@ ti,hwmods = "i2c5"; }; - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - }; - mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; @@ -621,10 +604,9 @@ ti,hwmods = "wd_timer2"; }; - emif1: emif@4c000000 { + emif1: emif@0x4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; - ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -633,10 +615,9 @@ hw-caps-temp-alert; }; - emif2: emif@4d000000 { + emif2: emif@0x4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; - ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; @@ -645,19 +626,15 @@ hw-caps-temp-alert; }; - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usb3phy: control-phy@4a002370 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002370 0x4>; - reg-names = "power"; + omap_control_usb: omap-control-usb@4a002300 { + compatible = "ti,omap-control-usb"; + reg = <0x4a002300 0x4>, + <0x4a002370 0x4>; + reg-names = "control_dev_conf", "phy_power_usb"; + ti,type = <2>; }; - usb3: omap_dwc3@4a020000 { + omap_dwc3@4a020000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; reg = <0x4a020000 0x10000>; @@ -671,7 +648,6 @@ reg = <0x4a030000 0x10000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb2_phy>, <&usb3_phy>; - dr_mode = "peripheral"; tx-fifo-resize; }; }; @@ -686,7 +662,7 @@ usb2_phy: usb2phy@4a084000 { compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; - ctrl-module = <&omap_control_usb2phy>; + ctrl-module = <&omap_control_usb>; }; usb3_phy: usb3phy@4a084400 { @@ -695,7 +671,7 @@ <0x4a084800 0x64>, <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb3phy>; + ctrl-module = <&omap_control_usb>; }; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index daee5894..27ed9f5 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -76,11 +76,6 @@ compatible = "sirf,prima2-rsc"; reg = <0x88020000 0x1000>; }; - - cphifbg@88030000 { - compatible = "sirf,prima2-cphifbg"; - reg = <0x88030000 0x1000>; - }; }; mem-iobg { @@ -91,17 +86,10 @@ memory-controller@90000000 { compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x2000>; + reg = <0x90000000 0x10000>; interrupts = <27>; clocks = <&clks 5>; }; - - memc-monitor { - compatible = "sirf,prima2-memcmon"; - reg = <0x90002000 0x200>; - interrupts = <4>; - clocks = <&clks 32>; - }; }; disp-iobg { @@ -299,13 +287,7 @@ compatible = "sirf,prima2-spi"; reg = <0xb00d0000 0x10000>; interrupts = <15>; - sirf,spi-num-chipselects = <1>; - sirf,spi-dma-rx-channel = <25>; - sirf,spi-dma-tx-channel = <20>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clks 19>; - status = "disabled"; }; spi1: spi@b0170000 { @@ -313,13 +295,7 @@ compatible = "sirf,prima2-spi"; reg = <0xb0170000 0x10000>; interrupts = <16>; - sirf,spi-num-chipselects = <1>; - sirf,spi-dma-rx-channel = <12>; - sirf,spi-dma-tx-channel = <13>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&clks 20>; - status = "disabled"; }; i2c0: i2c@b00e0000 { @@ -328,8 +304,6 @@ reg = <0xb00e0000 0x10000>; interrupts = <24>; clocks = <&clks 17>; - #address-cells = <1>; - #size-cells = <0>; }; i2c1: i2c@b00f0000 { @@ -338,8 +312,6 @@ reg = <0xb00f0000 0x10000>; interrupts = <25>; clocks = <&clks 18>; - #address-cells = <1>; - #size-cells = <0>; }; tsc@b0110000 { @@ -388,12 +360,6 @@ sirf,function = "uart0"; }; }; - uart0_noflow_pins_a: uart0@1 { - uart { - sirf,pins = "uart0_nostreamctrlgrp"; - sirf,function = "uart0_nostreamctrl"; - }; - }; uart1_pins_a: uart1@0 { uart { sirf,pins = "uart1grp"; @@ -532,42 +498,18 @@ sirf,function = "usp0"; }; }; - usp0_uart_nostreamctrl_pins_a: usp0@1 { - usp0 { - sirf,pins = - "usp0_uart_nostreamctrl_grp"; - sirf,function = - "usp0_uart_nostreamctrl"; - }; - }; usp1_pins_a: usp1@0 { usp1 { sirf,pins = "usp1grp"; sirf,function = "usp1"; }; }; - usp1_uart_nostreamctrl_pins_a: usp1@1 { - usp1 { - sirf,pins = - "usp1_uart_nostreamctrl_grp"; - sirf,function = - "usp1_uart_nostreamctrl"; - }; - }; usp2_pins_a: usp2@0 { usp2 { sirf,pins = "usp2grp"; sirf,function = "usp2"; }; }; - usp2_uart_nostreamctrl_pins_a: usp2@1 { - usp2 { - sirf,pins = - "usp2_uart_nostreamctrl_grp"; - sirf,function = - "usp2_uart_nostreamctrl"; - }; - }; usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { usb0_utmi_drvbus { sirf,pins = "usb0_utmi_drvbusgrp"; @@ -580,18 +522,6 @@ sirf,function = "usb1_utmi_drvbus"; }; }; - usb1_dp_dn_pins_a: usb1_dp_dn@0 { - usb1_dp_dn { - sirf,pins = "usb1_dp_dngrp"; - sirf,function = "usb1_dp_dn"; - }; - }; - uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { - uart1_route_io_usb1 { - sirf,pins = "uart1_route_io_usb1grp"; - sirf,function = "uart1_route_io_usb1"; - }; - }; warm_rst_pins_a: warm_rst@0 { warm_rst { sirf,pins = "warm_rstgrp"; diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts deleted file mode 100644 index 1fb20f2..0000000 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Device Tree Source for the Genmai board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -/include/ "r7s72100.dtsi" - -/ { - model = "Genmai"; - compatible = "renesas,genmai", "renesas,r7s72100"; - - chosen { - bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; - }; - - memory { - device_type = "memory"; - reg = <0x08000000 0x08000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi deleted file mode 100644 index 46b82aa..0000000 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Device Tree Source for the r7s72100 SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/ { - compatible = "renesas,r7s72100"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - }; - - gic: interrupt-controller@e8201000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; -}; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 9443e93..f444624 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -10,7 +10,6 @@ /dts-v1/; /include/ "r8a73a4.dtsi" -#include <dt-bindings/gpio/gpio.h> / { model = "APE6EVM"; @@ -25,34 +24,6 @@ reg = <0 0x40000000 0 0x40000000>; }; - vcc_mmc0: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "MMC0 Vcc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_sdhi0: regulator@1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* Common 3.3V rail, used by several devices on APE6EVM */ - ape6evm_fixed_3v3: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - lbsc { compatible = "simple-bus"; #address-cells = <1>; @@ -62,7 +33,6 @@ }; &i2c5 { - status = "okay"; vdd_dvfs: max8973@1b { compatible = "maxim,max8973"; reg = <0x1b>; @@ -92,47 +62,4 @@ renesas,groups = "scifa0_data"; renesas,function = "scifa0"; }; - - mmc0_pins: mmcif { - renesas,groups = "mmc0_data8", "mmc0_ctrl"; - renesas,function = "mmc0"; - }; - - sdhi0_pins: sdhi0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; - }; - - sdhi1_pins: sdhi1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; - }; -}; - -&mmcif0 { - vmmc-supply = <&vcc_mmc0>; - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "okay"; -}; - -&sdhi0 { - vmmc-supply = <&vcc_sdhi0>; - bus-width = <4>; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - status = "okay"; -}; - -&sdhi1 { - vmmc-supply = <&ape6evm_fixed_3v3>; - bus-width = <4>; - broken-cd; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 91436b5..72f867e 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -52,7 +52,6 @@ }; &i2c5 { - status = "okay"; vdd_dvfs: max8973@1b { compatible = "maxim,max8973"; reg = <0x1b>; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 287e047..658fcc5 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -78,49 +78,6 @@ <0 56 4>, <0 57 4>; }; - dmac: dma-multiplexer@0 { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupt-parent = <&gic>; - interrupts = <0 220 4 - 0 200 4 - 0 201 4 - 0 202 4 - 0 203 4 - 0 204 4 - 0 205 4 - 0 206 4 - 0 207 4 - 0 208 4 - 0 209 4 - 0 210 4 - 0 211 4 - 0 212 4 - 0 213 4 - 0 214 4 - 0 215 4 - 0 216 4 - 0 217 4 - 0 218 4 - 0 219 4>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - }; - }; - thermal@e61f0000 { compatible = "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, @@ -136,7 +93,6 @@ reg = <0 0xe6500000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 174 0x4>; - status = "disabled"; }; i2c1: i2c@e6510000 { @@ -146,7 +102,6 @@ reg = <0 0xe6510000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 175 0x4>; - status = "disabled"; }; i2c2: i2c@e6520000 { @@ -156,7 +111,6 @@ reg = <0 0xe6520000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 176 0x4>; - status = "disabled"; }; i2c3: i2c@e6530000 { @@ -166,7 +120,6 @@ reg = <0 0xe6530000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 177 0x4>; - status = "disabled"; }; i2c4: i2c@e6540000 { @@ -176,7 +129,6 @@ reg = <0 0xe6540000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 178 0x4>; - status = "disabled"; }; i2c5: i2c@e60b0000 { @@ -186,7 +138,6 @@ reg = <0 0xe60b0000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 179 0x4>; - status = "disabled"; }; i2c6: i2c@e6550000 { @@ -196,7 +147,6 @@ reg = <0 0xe6550000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 184 0x4>; - status = "disabled"; }; i2c7: i2c@e6560000 { @@ -206,7 +156,6 @@ reg = <0 0xe6560000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 185 0x4>; - status = "disabled"; }; i2c8: i2c@e6570000 { @@ -216,7 +165,6 @@ reg = <0 0xe6570000 0 0x428>; interrupt-parent = <&gic>; interrupts = <0 173 0x4>; - status = "disabled"; }; mmcif0: mmcif@ee200000 { diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 1c56c5e..c638e4a 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -11,7 +11,6 @@ /dts-v1/; /include/ "r8a7740.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pwm/pwm.h> / { model = "armadillo 800 eva reference"; @@ -35,33 +34,6 @@ regulator-boot-on; }; - vcc_sdhi0: regulator@1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator@2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sdhi0>; - - enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; - gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; - states = <3300000 0 - 1800000 1>; - - enable-active-high; - }; - leds { compatible = "gpio-leds"; led1 { @@ -77,19 +49,9 @@ gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; }; }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - }; }; &i2c0 { - status = "okay"; touchscreen: st1232@55 { compatible = "sitronix,st1232"; reg = <0x55>; @@ -114,44 +76,4 @@ renesas,groups = "intc_irq10"; renesas,function = "intc"; }; - - backlight_pins: backlight { - renesas,groups = "tpu0_to2_1"; - renesas,function = "tpu0"; - }; - - mmc0_pins: mmc0 { - renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1"; - renesas,function = "mmc0"; - }; - - sdhi0_pins: sdhi0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - renesas,function = "sdhi0"; - }; -}; - -&tpu { - status = "okay"; -}; - -&mmcif0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ae1e230..44d3d52 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -131,7 +131,6 @@ 0 202 0x4 0 203 0x4 0 204 0x4>; - status = "disabled"; }; i2c1: i2c@e6c20000 { @@ -144,7 +143,6 @@ 0 71 0x4 0 72 0x4 0 73 0x4>; - status = "disabled"; }; pfc: pfc@e6050000 { @@ -161,37 +159,4 @@ status = "disabled"; #pwm-cells = <3>; }; - - mmcif0: mmcif@e6bd0000 { - compatible = "renesas,sh-mmcif"; - reg = <0xe6bd0000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 56 4 - 0 57 4>; - status = "disabled"; - }; - - sdhi0: sdhi@e6850000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6850000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 117 4 - 0 118 4 - 0 119 4>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; - - sdhi1: sdhi@e6860000 { - compatible = "renesas,sdhi-r8a7740"; - reg = <0xe6860000 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 121 4 - 0 122 4 - 0 123 4>; - cap-sd-highspeed; - cap-sdio-irq; - status = "disabled"; - }; }; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 969e386..9bb903a 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -22,36 +22,11 @@ compatible = "renesas,bockw-reference", "renesas,r8a7778"; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "console=ttySC0,115200 ignore_loglevel rw"; }; memory { device_type = "memory"; reg = <0x60000000 0x10000000>; }; - - fixedregulator3v3: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18300000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x18300000 0x1000>; - - phy-mode = "mii"; - interrupt-parent = <&irqpin>; - interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */ - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; -}; - -&irqpin { - status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index a6308a3..3577aba 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -33,25 +33,6 @@ <0xfe430000 0x100>; }; - /* irqpin: IRQ0 - IRQ3 */ - irqpin: irqpin@fe78001c { - compatible = "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - status = "disabled"; /* default off */ - reg = <0xfe78001c 4>, - <0xfe780010 4>, - <0xfe780024 4>, - <0xfe780044 4>, - <0xfe780064 4>; - interrupt-parent = <&gic>; - interrupts = <0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4>; - sense-bitfield-width = <2>; - }; - gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index ab4110a..6d55083 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -42,8 +42,8 @@ pinctrl-names = "default"; phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ + interrupt-parent = <&gic>; + interrupts = <0 28 0x4>; reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; @@ -63,10 +63,6 @@ }; }; -&irqpin0 { - status = "okay"; -}; - &pfc { pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 19faeac..ebbe507 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -135,7 +135,6 @@ irqpin0: irqpin@fe780010 { compatible = "renesas,intc-irqpin"; #interrupt-cells = <2>; - status = "disabled"; interrupt-controller; reg = <0xfe78001c 4>, <0xfe780010 4>, @@ -157,7 +156,6 @@ reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 0x4>; - status = "disabled"; }; i2c1: i2c@ffc71000 { @@ -167,7 +165,6 @@ reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 0x4>; - status = "disabled"; }; i2c2: i2c@ffc72000 { @@ -177,7 +174,6 @@ reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 0x4>; - status = "disabled"; }; i2c3: i2c@ffc73000 { @@ -187,7 +183,6 @@ reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 0x4>; - status = "disabled"; }; pfc: pfc@fffc0000 { diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ee845fa..413b4c2 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -24,55 +24,6 @@ reg = <0>; clock-frequency = <1300000000>; }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1300000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - clock-frequency = <1300000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - clock-frequency = <1300000000>; - }; - - cpu4: cpu@4 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clock-frequency = <780000000>; - }; - - cpu5: cpu@5 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <780000000>; - }; - - cpu6: cpu@6 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <780000000>; - }; - - cpu7: cpu@7 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <780000000>; - }; }; gic: interrupt-controller@f1001000 { @@ -176,46 +127,6 @@ interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; }; - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6508000 0 0x40>; - interrupt-parent = <&gic>; - interrupts = <0 287 0x4>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6518000 0 0x40>; - interrupt-parent = <&gic>; - interrupts = <0 288 0x4>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6530000 0 0x40>; - interrupt-parent = <&gic>; - interrupts = <0 286 0x4>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790"; - reg = <0 0xe6540000 0 0x40>; - interrupt-parent = <&gic>; - interrupts = <0 290 0x4>; - status = "disabled"; - }; - mmcif0: mmcif@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts deleted file mode 100644 index 1ce5250..0000000 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -/include/ "r8a7791.dtsi" - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch", "renesas,r8a7791"; - - chosen { - bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi deleted file mode 100644 index fea5cfe..0000000 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Device Tree Source for the r8a7791 SoC - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/ { - compatible = "renesas,r8a7791"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1300000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1300000000>; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupt-parent = <&gic>; - interrupts = <0 0 4>, - <0 1 4>, - <0 2 4>, - <0 3 4>, - <0 12 4>, - <0 13 4>, - <0 14 4>, - <0 15 4>, - <0 16 4>, - <0 17 4>; - }; -}; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts deleted file mode 100644 index 035df40..0000000 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "rk3066a.dtsi" - -/ { - model = "bq Curie 2"; - - memory { - reg = <0x60000000 0x40000000>; - }; - - soc { - uart0: serial@10124000 { - status = "okay"; - }; - - uart1: serial@10126000 { - status = "okay"; - }; - - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; - - uart3: serial@20068000 { - status = "okay"; - }; - - vcc_sd0: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; - startup-delay-us = <100000>; - }; - - dwmmc@10214000 { /* sdmmc */ - num-slots = <1>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - dwmmc@10218000 { /* wifi */ - num-slots = <1>; - status = "okay"; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = <116>; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - button@1 { - gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = <104>; - label = "GPIO Key Vol-"; - linux,input-type = <1>; - gpio-key,wakeup = <0>; - debounce-interval = <100>; - }; - /* VOL+ comes somehow thru the ADC */ - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index be5d2b0..56bfac9 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -14,12 +14,15 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> -#include "rk3xxx.dtsi" +#include "skeleton.dtsi" #include "rk3066a-clocks.dtsi" / { compatible = "rockchip,rk3066a"; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -40,6 +43,33 @@ }; soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&dummy150m>; + }; + timer@20038000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; @@ -161,14 +191,17 @@ uart0_xfer: uart0-xfer { rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; uart0_cts: uart0-cts { rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; uart0_rts: uart0-rts { rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; }; @@ -176,14 +209,17 @@ uart1_xfer: uart1-xfer { rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; uart1_cts: uart1-cts { rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; uart1_rts: uart1-rts { rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; }; @@ -191,6 +227,7 @@ uart2_xfer: uart2-xfer { rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; /* no rts / cts for uart2 */ }; @@ -199,36 +236,44 @@ uart3_xfer: uart3-xfer { rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; uart3_cts: uart3-cts { rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; uart3_rts: uart3-rts { rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; }; sd0 { sd0_clk: sd0-clk { rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd0_cmd: sd0-cmd { rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd0_cd: sd0-cd { rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd0_wp: sd0-wp { rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd0_bus1: sd0-bus-width1 { rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd0_bus4: sd0-bus-width4 { @@ -236,28 +281,34 @@ <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; }; sd1 { sd1_clk: sd1-clk { rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd1_cmd: sd1-cmd { rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd1_cd: sd1-cd { rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd1_wp: sd1-wp { rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd1_bus1: sd1-bus-width1 { rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; sd1_bus4: sd1-bus-width4 { @@ -265,8 +316,75 @@ <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; }; }; }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 8>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 10>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 12>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 14>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi deleted file mode 100644 index b1b92dc..0000000 --- a/arch/arm/boot/dts/rk3188-clocks.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/ { - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - dummy: dummy { - compatible = "fixed-clock"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - dummy48m: dummy48m { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - - dummy150m: dummy150m { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy150m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_aclk_core", - "reserved", "gate_i2s0", - "gate_i2s0_frac", "reserved", - "reserved", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer3", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@200000d8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d8 0x4>; - clocks = <&clk_gates2 1>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&clk_gates2 3>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy48m>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_periph_src", "gate_aclk_periph", - "gate_hclk_periph", "gate_pclk_periph", - "gate_smc", "gate_mac", - "gate_hsadc", "gate_hsadc_frac", - "gate_saradc", "gate_spi0", - "gate_spi1", "gate_mmc0", - "gate_mac_lbtest", "gate_mmc1", - "gate_emmc", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@200000dc { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000dc 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&xin24m>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", - "gate_dclk_lcdc1", "gate_pclkin_cif0", - "gate_timer2", "gate_timer4", - "gate_hsicphy", "gate_cif0_out", - "gate_timer5", "gate_aclk_vepu", - "gate_hclk_vepu", "gate_aclk_vdpu", - "gate_hclk_vdpu", "reserved", - "gate_timer6", "gate_aclk_gpu_src"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@200000e0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e0 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates2 3>, - <&clk_gates2 1>, <&clk_gates2 1>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates0 4>, <&clk_gates0 4>, - <&clk_gates0 3>, <&dummy>, - <&clk_gates0 3>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", - "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", - "gate_aclk_pei_niu", "gate_hclk_usb_peri", - "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", - "gate_hclk_cpubus", "gate_hclk_ahb2apb", - "gate_aclk_strc_sys", "reserved", - "gate_aclk_intmem", "reserved", - "gate_hclk_imem1", "gate_hclk_imem0"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@200000e4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e4 0x4>; - clocks = <&clk_gates0 3>, <&clk_gates2 1>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates0 4>, <&clk_gates0 5>, - <&clk_gates2 1>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates4 5>; - - clock-output-names = - "gate_aclk_dmac1", "gate_aclk_dmac2", - "gate_pclk_efuse", "gate_pclk_tzpc", - "gate_pclk_grf", "gate_pclk_pmu", - "gate_hclk_rom", "gate_pclk_ddrupctl", - "gate_aclk_smc", "gate_hclk_nandc", - "gate_hclk_mmc0", "gate_hclk_mmc1", - "gate_hclk_emmc", "gate_hclk_otg0"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@200000e8 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000e8 0x4>; - clocks = <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>, - <&dummy>, <&dummy>, - <&clk_gates3 0>, <&clk_gates0 4>, - <&clk_gates0 4>, <&clk_gates1 4>, - <&clk_gates0 4>, <&clk_gates3 0>; - - clock-output-names = - "gate_aclk_lcdc0", "gate_hclk_lcdc0", - "gate_hclk_lcdc1", "gate_aclk_lcdc1", - "gate_hclk_cif0", "gate_aclk_cif0", - "reserved", "reserved", - "gate_aclk_ipp", "gate_hclk_ipp", - "gate_hclk_rga", "gate_aclk_rga", - "gate_hclk_vio_bus", "gate_aclk_vio0"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@200000ec { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000ec 0x4>; - clocks = <&clk_gates2 2>, <&clk_gates0 4>, - <&clk_gates0 4>, <&dummy>, - <&dummy>, <&clk_gates2 2>, - <&clk_gates2 2>, <&clk_gates0 5>, - <&dummy>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates2 3>; - - clock-output-names = - "gate_hclk_emac", "gate_hclk_spdif", - "gate_hclk_i2s0_2ch", "gate_hclk_otg1", - "gate_hclk_hsic", "gate_hclk_hsadc", - "gate_hclk_pidf", "gate_pclk_timer0", - "reserved", "gate_pclk_timer2", - "gate_pclk_pwm01", "gate_pclk_pwm23", - "gate_pclk_spi0", "gate_pclk_spi1", - "gate_pclk_saradc", "gate_pclk_wdt"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@200000f0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f0 0x4>; - clocks = <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&clk_gates2 3>, - <&clk_gates2 3>, <&clk_gates0 5>, - <&clk_gates0 5>, <&clk_gates0 5>, - <&clk_gates2 3>, <&dummy>; - - clock-output-names = - "gate_pclk_uart0", "gate_pclk_uart1", - "gate_pclk_uart2", "gate_pclk_uart3", - "gate_pclk_i2c0", "gate_pclk_i2c1", - "gate_pclk_i2c2", "gate_pclk_i2c3", - "gate_pclk_i2c4", "gate_pclk_gpio0", - "gate_pclk_gpio1", "gate_pclk_gpio2", - "gate_pclk_gpio3", "gate_aclk_gps"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@200000f4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000f4 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_clk_core_dbg", "gate_pclk_dbg", - "gate_clk_trace", "gate_atclk", - "gate_clk_l2c", "gate_aclk_vio1", - "gate_pclk_publ", "gate_aclk_gpu"; - - #clock-cells = <1>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts deleted file mode 100644 index 3ba1968..0000000 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/dts-v1/; -#include "rk3188.dtsi" - -/ { - model = "Radxa Rock"; - - memory { - reg = <0x60000000 0x80000000>; - }; - - soc { - uart0: serial@10124000 { - status = "okay"; - }; - - uart1: serial@10126000 { - status = "okay"; - }; - - uart2: serial@20064000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "okay"; - }; - - uart3: serial@20068000 { - status = "okay"; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - linux,code = <116>; - label = "GPIO Key Power"; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green { - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - yellow { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep { - gpios = <&gpio0 15 0>; - default-state = "off"; - }; - }; - - }; -}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi deleted file mode 100644 index 1a26b03..0000000 --- a/arch/arm/boot/dts/rk3188.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "rk3xxx.dtsi" -#include "rk3188-clocks.dtsi" - -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - }; - }; - - soc { - global-timer@1013c200 { - interrupts = <GIC_PPI 11 0xf04>; - }; - - local-timer@1013c600 { - interrupts = <GIC_PPI 13 0xf04>; - }; - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - reg = <0x20008000 0xa0>, - <0x20008164 0x1a0>; - reg-names = "base", "pull"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>, - <0x20004064 0x8>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 11>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 12>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi deleted file mode 100644 index 0fcbcfd..0000000 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" - -/ { - interrupt-parent = <&gic>; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - L2: l2-cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = <GIC_PPI 11 0x304>; - clocks = <&dummy150m>; - }; - - local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = <GIC_PPI 13 0x304>; - clocks = <&dummy150m>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 8>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 10>; - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 12>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&clk_gates1 14>; - status = "disabled"; - }; - - dwmmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clk_gates5 10>, <&clk_gates2 11>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - - dwmmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clk_gates5 11>, <&clk_gates2 13>; - clock-names = "biu", "ciu"; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi deleted file mode 100644 index a7d1c8e..0000000 --- a/arch/arm/boot/dts/s3c6400.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts deleted file mode 100644 index 57e00f9..0000000 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Samsung's S3C6410 based Mini6410 board device tree source - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Device tree source file for FriendlyARM Mini6410 board which is based on - * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> - -#include "s3c6410.dtsi" - -/ { - model = "FriendlyARM Mini6410 board based on S3C6410"; - compatible = "friendlyarm,mini6410", "samsung,s3c6410"; - - memory { - reg = <0x50000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - davicom,no-eeprom; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - autorepeat; - - button-k1 { - label = "K1"; - gpios = <&gpn 0 GPIO_ACTIVE_LOW>; - linux,code = <2>; - debounce-interval = <20>; - }; - - button-k2 { - label = "K2"; - gpios = <&gpn 1 GPIO_ACTIVE_LOW>; - linux,code = <3>; - debounce-interval = <20>; - }; - - button-k3 { - label = "K3"; - gpios = <&gpn 2 GPIO_ACTIVE_LOW>; - linux,code = <4>; - debounce-interval = <20>; - }; - - button-k4 { - label = "K4"; - gpios = <&gpn 3 GPIO_ACTIVE_LOW>; - linux,code = <5>; - debounce-interval = <20>; - }; - - button-k5 { - label = "K5"; - gpios = <&gpn 4 GPIO_ACTIVE_LOW>; - linux,code = <6>; - debounce-interval = <20>; - }; - - button-k6 { - label = "K6"; - gpios = <&gpn 5 GPIO_ACTIVE_LOW>; - linux,code = <7>; - debounce-interval = <20>; - }; - - button-k7 { - label = "K7"; - gpios = <&gpl 11 GPIO_ACTIVE_LOW>; - linux,code = <8>; - debounce-interval = <20>; - }; - - button-k8 { - label = "K8"; - gpios = <&gpl 12 GPIO_ACTIVE_LOW>; - linux,code = <9>; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds>; - - led-1 { - label = "LED1"; - gpios = <&gpk 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "LED2"; - gpios = <&gpk 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - led-3 { - label = "LED3"; - gpios = <&gpk 6 GPIO_ACTIVE_LOW>; - }; - - led-4 { - label = "LED4"; - gpios = <&gpk 7 GPIO_ACTIVE_LOW>; - }; - }; - - buzzer { - compatible = "pwm-beeper"; - pwms = <&pwm 0 1000000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&pinctrl0 { - gpio_leds: gpio-leds { - samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - gpio_keys: gpio-keys { - samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", - "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = <PIN_PULL_NONE>; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts deleted file mode 100644 index ecf35ec..0000000 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Samsung S3C6410 based SMDK6410 board device tree source. - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Device tree source file for SAMSUNG SMDK6410 board which is based on - * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> - -#include "s3c6410.dtsi" - -/ { - model = "SAMSUNG SMDK6410 board based on S3C6410"; - compatible = "samsung,mini6410", "samsung,s3c6410"; - - memory { - reg = <0x50000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "smsc,lan9115"; - reg = <0x18000000 0x10000>; - interrupt-parent = <&gpn>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,force-internal-phy; - }; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi deleted file mode 100644 index eb4226b..0000000 --- a/arch/arm/boot/dts/s3c6410.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Samsung's S3C6410 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6410"; - - aliases { - i2c1 = &i2c1; - }; -}; - -&vic0 { - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6410-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - - i2c1: i2c@7f00f000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f00f000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi deleted file mode 100644 index b1197d8..0000000 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ /dev/null @@ -1,687 +0,0 @@ -/* - * Samsung's S3C64xx SoC series common device tree source - * - pin control-related definitions - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are - * listed as device tree nodes in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 2 - -&pinctrl0 { - /* - * Pin banks - */ - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpi: gpi { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm: gpm { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpn: gpn { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpo: gpo { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpp: gpp { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpq: gpq { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data { - samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - uart2_data: uart2-data { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - uart3_data: uart3-data { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - ext_dma_0: ext-dma-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - ext_dma_1: ext-dma-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - irda_data_0: irda-data-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - irda_data_1: irda-data-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - irda_sdbw: irda-sdbw { - samsung,pins = "gpb-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - }; - - i2c1_bus: i2c1-bus { - /* S3C6410-only */ - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <6>; - samsung,pin-pud = <PIN_PULL_UP>; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - }; - - spi0_cs: spi0-cs { - samsung,pins = "gpc-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - }; - - spi1_cs: spi1-cs { - samsung,pins = "gpc-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpg-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpg-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd0_bus1: sd0-bus1 { - samsung,pins = "gpg-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd0_bus4: sd0-bus4 { - samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_UP>; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gph-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gph-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd1_bus1: sd1-bus1 { - samsung,pins = "gph-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd1_bus4: sd1-bus4 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd1_bus8: sd1-bus8 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", - "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_UP>; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd2_bus1: sd2-bus1 { - samsung,pins = "gph-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - sd2_bus4: sd2-bus4 { - samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2s0_cdclk: i2s0-cdclk { - samsung,pins = "gpd-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2s1_cdclk: i2s1-cdclk { - samsung,pins = "gpe-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2s2_bus: i2s2-bus { - /* S3C6410-only */ - samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", - "gph-8", "gph-9"; - samsung,pin-function = <5>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - i2s2_cdclk: i2s2-cdclk { - /* S3C6410-only */ - samsung,pins = "gph-7"; - samsung,pin-function = <5>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pcm0_extclk: pcm0-extclk { - samsung,pins = "gpd-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pcm1_extclk: pcm1-extclk { - samsung,pins = "gpe-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - ac97_bus_0: ac97-bus-0 { - samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - ac97_bus_1: ac97-bus-1 { - samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - cam_port: cam-port { - samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", - "gpf-5", "gpf-6", "gpf-7", "gpf-8", - "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - cam_rst: cam-rst { - samsung,pins = "gpf-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - cam_field: cam-field { - /* S3C6410-only */ - samsung,pins = "gpb-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pwm_extclk: pwm-extclk { - samsung,pins = "gpf-13"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpf-14"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpf-15"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - clkout0: clkout-0 { - samsung,pins = "gpf-14"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col0_0: keypad-col0-0 { - samsung,pins = "gph-0"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col1_0: keypad-col1-0 { - samsung,pins = "gph-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col2_0: keypad-col2-0 { - samsung,pins = "gph-2"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col3_0: keypad-col3-0 { - samsung,pins = "gph-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col4_0: keypad-col4-0 { - samsung,pins = "gph-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col5_0: keypad-col5-0 { - samsung,pins = "gph-5"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col6_0: keypad-col6-0 { - samsung,pins = "gph-6"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col7_0: keypad-col7-0 { - samsung,pins = "gph-7"; - samsung,pin-function = <4>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col0_1: keypad-col0-1 { - samsung,pins = "gpl-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col1_1: keypad-col1-1 { - samsung,pins = "gpl-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col2_1: keypad-col2-1 { - samsung,pins = "gpl-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col3_1: keypad-col3-1 { - samsung,pins = "gpl-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col4_1: keypad-col4-1 { - samsung,pins = "gpl-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col5_1: keypad-col5-1 { - samsung,pins = "gpl-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col6_1: keypad-col6-1 { - samsung,pins = "gpl-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_col7_1: keypad-col7-1 { - samsung,pins = "gpl-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row0_0: keypad-row0-0 { - samsung,pins = "gpk-8"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row1_0: keypad-row1-0 { - samsung,pins = "gpk-9"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row2_0: keypad-row2-0 { - samsung,pins = "gpk-10"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row3_0: keypad-row3-0 { - samsung,pins = "gpk-11"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row4_0: keypad-row4-0 { - samsung,pins = "gpk-12"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row5_0: keypad-row5-0 { - samsung,pins = "gpk-13"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row6_0: keypad-row6-0 { - samsung,pins = "gpk-14"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row7_0: keypad-row7-0 { - samsung,pins = "gpk-15"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row0_1: keypad-row0-1 { - samsung,pins = "gpn-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row1_1: keypad-row1-1 { - samsung,pins = "gpn-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row2_1: keypad-row2-1 { - samsung,pins = "gpn-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row3_1: keypad-row3-1 { - samsung,pins = "gpn-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row4_1: keypad-row4-1 { - samsung,pins = "gpn-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row5_1: keypad-row5-1 { - samsung,pins = "gpn-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row6_1: keypad-row6-1 { - samsung,pins = "gpn-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - keypad_row7_1: keypad-row7-1 { - samsung,pins = "gpn-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", - "gpi-7", "gpi-10", "gpi-11", "gpi-12", - "gpi-13", "gpi-14", "gpi-15", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", - "gpi-6", "gpi-7", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-2", "gpj-3", "gpj-4", "gpj-5", - "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6", "gpi-7", - "gpi-8", "gpi-9", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-0", "gpj-1", "gpj-2", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; - - hsi_bus: hsi-bus { - samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", - "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <PIN_PULL_NONE>; - }; -}; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi deleted file mode 100644 index 4e3be4d..0000000 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Samsung's S3C64xx SoC series common device tree source - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * Samsung's S3C64xx SoC series device nodes are listed in this file. - * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include <dt-bindings/clock/samsung,s3c64xx-clock.h> - -/ { - aliases { - i2c0 = &i2c0; - pinctrl0 = &pinctrl0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s", "arm,arm1176"; - reg = <0x0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic0: interrupt-controller@71200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@71300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71300000 0x1000>; - #interrupt-cells = <1>; - }; - - sdhci0: sdhci@7c200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c200000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: sdhci@7c300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c300000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <25>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: sdhci@7c400000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c400000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <17>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - watchdog: watchdog@7e004000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x7e004000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks PCLK_WDT>; - status = "disabled"; - }; - - i2c0: i2c@7f004000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f004000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <18>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@7f005000 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <5>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart1: serial@7f005400 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005400 0x100>; - interrupt-parent = <&vic1>; - interrupts = <6>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart2: serial@7f005800 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005800 0x100>; - interrupt-parent = <&vic1>; - interrupts = <7>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart3: serial@7f005c00 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005c00 0x100>; - interrupt-parent = <&vic1>; - interrupts = <8>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - pwm: pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clock-names = "timers"; - clocks = <&clocks PCLK_PWM>; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pinctrl0: pinctrl@7f008000 { - compatible = "samsung,s3c64xx-pinctrl"; - reg = <0x7f008000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <21>; - - pctrl_int_map: pinctrl-interrupt-map { - interrupt-map = <0 &vic0 0>, - <1 &vic0 1>, - <2 &vic1 0>, - <3 &vic1 1>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <1>; - }; - - wakeup-interrupt-controller { - compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts = <0>, <1>, <2>, <3>; - interrupt-parent = <&pctrl_int_map>; - }; - }; - }; -}; - -#include "s3c64xx-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5cdaba4..b7f4961 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -31,6 +31,7 @@ gpio3 = &pioD; gpio4 = &pioE; tcb0 = &tcb0; + tcb1 = &tcb1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -104,6 +105,15 @@ status = "disabled"; }; + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + status = "disabled"; + }; + tcb0: timer@f0010000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; @@ -156,6 +166,15 @@ status = "disabled"; }; + macb0: ethernet@f0028000 { + compatible = "cdns,pc302-gem", "cdns,gem"; + reg = <0xf0028000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + status = "disabled"; + }; + isi: isi@f0034000 { compatible = "atmel,at91sam9g45-isi"; reg = <0xf0034000 0x4000>; @@ -176,6 +195,19 @@ #size-cells = <0>; }; + mmc2: mmc@f8004000 { + compatible = "atmel,hsmci"; + reg = <0xf8004000 0x600>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + spi1: spi@f8008000 { #address-cells = <1>; #size-cells = <0>; @@ -199,6 +231,20 @@ status = "disabled"; }; + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + }; + + tcb1: timer@f8014000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8014000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + }; + adc0: adc@f8018000 { compatible = "atmel,at91sam9260-adc"; reg = <0xf8018000 0x100>; @@ -295,6 +341,15 @@ status = "disabled"; }; + macb1: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + status = "disabled"; + }; + sha@f8034000 { compatible = "atmel,sam9g46-sha"; reg = <0xf8034000 0x100>; @@ -419,6 +474,22 @@ }; }; + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ + AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = @@ -466,6 +537,107 @@ }; }; + lcd { + pinctrl_lcd: lcd-0 { + atmel,pins = + <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ + AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ + AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ + AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ + AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ + AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ + AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ + AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ + AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ + }; + }; + + macb0 { + pinctrl_macb0_data_rgmii: macb0_data_rgmii { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ + }; + pinctrl_macb0_data_gmii: macb0_data_gmii { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ + AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ + AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ + AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ + AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ + AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ + AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ + AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ + }; + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ + }; + pinctrl_macb0_signal_gmii: macb0_signal_gmii { + atmel,pins = + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ + }; + + }; + + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ + }; + }; + mmc0 { pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { atmel,pins = @@ -503,6 +675,21 @@ }; }; + mmc2 { + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { + atmel,pins = + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ + }; + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { + atmel,pins = + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + }; + }; + nand0 { pinctrl_nand0_ale_cle: nand0_ale_cle-0 { atmel,pins = @@ -561,6 +748,22 @@ }; }; + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi deleted file mode 100644 index 7997dc9..0000000 --- a/arch/arm/boot/dts/sama5d31.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* - * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" - -/ { - compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index 04eec0d..027bac7 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -7,13 +7,12 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -#include "sama5d31.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D31-EK"; - compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi deleted file mode 100644 index 39f8322..0000000 --- a/arch/arm/boot/dts/sama5d33.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -/* - * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" - -/ { - compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts index cbd6a3f..99bd0c8 100644 --- a/arch/arm/boot/dts/sama5d33ek.dts +++ b/arch/arm/boot/dts/sama5d33ek.dts @@ -7,13 +7,12 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -#include "sama5d33.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D33-EK"; - compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi deleted file mode 100644 index 89cda2c..0000000 --- a/arch/arm/boot/dts/sama5d34.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* - * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_lcd.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" - -/ { - compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 878aa16..fb8ee11 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -7,13 +7,12 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -#include "sama5d34.dtsi" #include "sama5d3xmb.dtsi" #include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D34-EK"; - compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi deleted file mode 100644 index d20cd71..0000000 --- a/arch/arm/boot/dts/sama5d35.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2 or later. - */ -#include "sama5d3.dtsi" -#include "sama5d3_gmac.dtsi" -#include "sama5d3_emac.dtsi" -#include "sama5d3_can.dtsi" -#include "sama5d3_mci2.dtsi" -#include "sama5d3_uart.dtsi" -#include "sama5d3_tcb1.dtsi" - -/ { - compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5"; -}; diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts index 9089c7c..509a53d 100644 --- a/arch/arm/boot/dts/sama5d35ek.dts +++ b/arch/arm/boot/dts/sama5d35ek.dts @@ -7,12 +7,11 @@ * Licensed under GPLv2 or later. */ /dts-v1/; -#include "sama5d35.dtsi" #include "sama5d3xmb.dtsi" / { model = "Atmel SAMA5D35-EK"; - compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; ahb { apb { diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi deleted file mode 100644 index 8ed3260..0000000 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -/* - * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * CAN support - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff200 { - can0 { - pinctrl_can0_rx_tx: can0_rx_tx { - atmel,pins = - <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ - AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ - }; - }; - - can1 { - pinctrl_can1_rx_tx: can1_rx_tx { - atmel,pins = - <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ - AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ - }; - }; - - }; - - can0: can@f000c000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf000c000 0x300>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can0_rx_tx>; - status = "disabled"; - }; - - can1: can@f8010000 { - compatible = "atmel,at91sam9x5-can"; - reg = <0xf8010000 0x300>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_rx_tx>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi deleted file mode 100644 index 4d4f351..0000000 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -/* - * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb1 { - pinctrl_macb1_rmii: macb1_rmii-0 { - atmel,pins = - <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ - AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ - AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ - AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ - AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ - AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ - AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ - AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ - AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ - AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ - }; - }; - }; - - macb1: ethernet@f802c000 { - compatible = "cdns,at32ap7000-macb", "cdns,macb"; - reg = <0xf802c000 0x100>; - interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb1_rmii>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi deleted file mode 100644 index 0ba8be3..0000000 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* - * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * Gigabit Ethernet. - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff200 { - macb0 { - pinctrl_macb0_data_rgmii: macb0_data_rgmii { - atmel,pins = - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ - }; - pinctrl_macb0_data_gmii: macb0_data_gmii { - atmel,pins = - <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ - AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ - AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ - AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ - AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ - AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ - AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ - AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ - }; - pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { - atmel,pins = - <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ - AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ - }; - pinctrl_macb0_signal_gmii: macb0_signal_gmii { - atmel,pins = - <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ - AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ - AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ - AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ - AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ - AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ - AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ - AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ - AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ - }; - - }; - }; - - macb0: ethernet@f0028000 { - compatible = "cdns,pc302-gem", "cdns,gem"; - reg = <0xf0028000 0x100>; - interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi deleted file mode 100644 index 01f52a7..0000000 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -/* - * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * LCD support - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff200 { - lcd { - pinctrl_lcd: lcd-0 { - atmel,pins = - <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */ - AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */ - AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */ - AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */ - AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */ - AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */ - AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */ - AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */ - AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */ - AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */ - AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */ - AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */ - AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */ - AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */ - AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */ - AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */ - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */ - AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */ - AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */ - AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */ - AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */ - AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */ - AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */ - AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */ - AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */ - AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */ - AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */ - AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */ - AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */ - AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */ - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi deleted file mode 100644 index 38e88e3..0000000 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * 3 MMC ports - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff200 { - mmc2 { - pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { - atmel,pins = - <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ - AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ - AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ - }; - pinctrl_mmc2_dat1_3: mmc2_dat1_3 { - atmel,pins = - <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ - AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ - AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ - }; - }; - }; - - mmc2: mmc@f8004000 { - compatible = "atmel,hsmci"; - reg = <0xf8004000 0x600>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; - dma-names = "rxtx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi deleted file mode 100644 index 5264bb4..0000000 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * 2 TC blocks. - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - aliases { - tcb1 = &tcb1; - }; - - ahb { - apb { - tcb1: timer@f8014000 { - compatible = "atmel,at91sam9x5-tcb"; - reg = <0xf8014000 0x100>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi deleted file mode 100644 index 98fcb2d..0000000 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with - * UART support - * - * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> - * - * Licensed under GPLv2. - */ - -#include <dt-bindings/pinctrl/at91.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - ahb { - apb { - pinctrl@fffff200 { - uart0 { - pinctrl_uart0: uart0-0 { - atmel,pins = - <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ - AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ - }; - }; - - uart1 { - pinctrl_uart1: uart1-0 { - atmel,pins = - <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ - AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ - }; - }; - }; - - uart0: serial@f0024000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf0024000 0x200>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "disabled"; - }; - - uart1: serial@f8028000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf8028000 0x200>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 726a0f3..31ed9e3 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -6,6 +6,7 @@ * * Licensed under GPLv2 or later. */ +#include "sama5d3.dtsi" / { compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 8ee06dd..2122306 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -108,7 +108,6 @@ }; &i2c0 { - status = "okay"; as3711@40 { compatible = "ams,as3711"; reg = <0x40>; @@ -184,7 +183,6 @@ &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; - status = "okay"; }; &mmcif { diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index fcf2688..3955c76 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -135,7 +135,6 @@ 0 168 0x4 0 169 0x4 0 170 0x4>; - status = "disabled"; }; i2c1: i2c@e6822000 { @@ -148,7 +147,6 @@ 0 52 0x4 0 53 0x4 0 54 0x4>; - status = "disabled"; }; i2c2: i2c@e6824000 { @@ -161,7 +159,6 @@ 0 172 0x4 0 173 0x4 0 174 0x4>; - status = "disabled"; }; i2c3: i2c@e6826000 { @@ -174,7 +171,6 @@ 0 184 0x4 0 185 0x4 0 186 0x4>; - status = "disabled"; }; i2c4: i2c@e6828000 { @@ -187,7 +183,6 @@ 0 188 0x4 0 189 0x4 0 190 0x4>; - status = "disabled"; }; mmcif: mmcif@e6bd0000 { diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f936476..e273fa9 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -147,7 +147,7 @@ reg = <0x58>; }; - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -198,7 +198,7 @@ reg = <0x98>; }; - h2f_usr1_clk: h2f_usr1_clk { + s2f_usr1_clk: s2f_usr1_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; @@ -235,7 +235,7 @@ reg = <0xD0>; }; - h2f_usr2_clk: h2f_usr2_clk { + s2f_usr2_clk: s2f_usr2_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; @@ -243,198 +243,197 @@ }; }; - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <4>; + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; }; - mpu_l2_ram_clk: mpu_l2_ram_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <2>; + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; }; - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - clk-gate = <0x60 0>; + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; }; - l3_main_clk: l3_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mainclk>; - fixed-divider = <1>; + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; }; - l3_mp_clk: l3_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 0 2>; - clk-gate = <0x60 1>; + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; }; - l3_sp_clk: l3_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 2 2>; - }; + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 4 3>; - clk-gate = <0x60 2>; + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; }; - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 7 3>; - clk-gate = <0x60 3>; + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; }; - dbg_at_clk: dbg_at_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 0 2>; - clk-gate = <0x60 4>; + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; }; - dbg_clk: dbg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 2 2>; - clk-gate = <0x60 5>; + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; }; - dbg_trace_clk: dbg_trace_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x6C 0 3>; - clk-gate = <0x60 6>; + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; }; - dbg_timer_clk: dbg_timer_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - clk-gate = <0x60 7>; + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; }; - cfg_clk: cfg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 8>; + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 8>; }; - h2f_user0_clk: h2f_user0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 9>; + s2f_user0_clk: s2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_s2f_usr0_clk>; + clk-gate = <0x60 9>; }; - emac_0_clk: emac_0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac0_clk>; - clk-gate = <0xa0 0>; + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; }; - emac_1_clk: emac_1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac1_clk>; - clk-gate = <0xa0 1>; + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; }; - usb_mp_clk: usb_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 2>; - div-reg = <0xa4 0 3>; + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; }; - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 3>; - div-reg = <0xa4 3 3>; + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; }; - can0_clk: can0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 4>; - div-reg = <0xa4 6 3>; + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; }; - can1_clk: can1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 5>; - div-reg = <0xa4 9 3>; + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; }; - gpio_db_clk: gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 6>; - div-reg = <0xa8 0 24>; + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; }; - h2f_user1_clk: h2f_user1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr1_clk>; - clk-gate = <0xa0 7>; + s2f_user1_clk: s2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&s2f_usr1_clk>; + clk-gate = <0xa0 7>; }; - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 8>; + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; }; - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 9>; + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; }; - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 10>; - fixed-divider = <4>; + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; }; - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; - clk-gate = <0xa0 11>; + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; }; }; }; @@ -474,7 +473,6 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xfffec600 0x100>; interrupts = <1 13 0xf04>; - clocks = <&mpu_periph_clk>; }; timer0: timer0@ffc08000 { @@ -518,9 +516,9 @@ }; rstmgr@ffd05000 { - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; sysmgr@ffd08000 { compatible = "altr,sys-mgr"; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi deleted file mode 100644 index a85b404..0000000 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/dts-v1/; -/include/ "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - serial0@ffc02000 { - clock-frequency = <100000000>; - }; - - serial1@ffc03000 { - clock-frequency = <100000000>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - - timer0@ffc08000 { - clock-frequency = <100000000>; - }; - - timer1@ffc09000 { - clock-frequency = <100000000>; - }; - - timer2@ffd00000 { - clock-frequency = <25000000>; - }; - - timer3@ffd01000 { - clock-frequency = <25000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts deleted file mode 100644 index 5beffb2..0000000 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/include/ "socfpga_arria5.dtsi" - -/ { - model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; -}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dts index a8716f6..973999d 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -19,6 +19,26 @@ /include/ "socfpga.dtsi" / { + model = "Altera SOCFPGA Cyclone V"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + soc { clkmgr@ffd04000 { clocks { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts deleted file mode 100644 index 2ee52ab..0000000 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/include/ "socfpga_cyclone5.dtsi" - -/ { - model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; -}; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 7da99fe..1c1091e 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -10,7 +10,6 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/mfd/dbx500-prcmu.h> #include "skeleton.dtsi" / { @@ -43,56 +42,16 @@ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; - - clocks { - compatible = "stericsson,u8500-clks"; - - prcmu_clk: prcmu-clock { - #clock-cells = <1>; - }; - - prcc_pclk: prcc-periph-clock { - #clock-cells = <2>; - }; - - prcc_kclk: prcc-kernel-clock { - #clock-cells = <2>; - }; - - rtc_clk: rtc32k-clock { - #clock-cells = <0>; - }; - - smp_twd_clk: smp-twd-clock { - #clock-cells = <0>; - }; - }; - - mtu@a03c6000 { - /* Nomadik System Timer */ - compatible = "st,nomadik-mtu"; - reg = <0xa03c6000 0x1000>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; - clock-names = "timclk", "apb_pclk"; - }; - timer@a0410600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xa0410600 0x20>; interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ - - clocks = <&smp_twd_clk>; }; rtc@80154000 { compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&rtc_clk>; - clock-names = "apb_pclk"; }; gpio0: gpio@8012e000 { @@ -106,8 +65,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; - - clocks = <&prcc_pclk 1 9>; }; gpio1: gpio@8012e080 { @@ -121,8 +78,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; - - clocks = <&prcc_pclk 1 9>; }; gpio2: gpio@8000e000 { @@ -136,8 +91,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; - - clocks = <&prcc_pclk 3 8>; }; gpio3: gpio@8000e080 { @@ -151,8 +104,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; - - clocks = <&prcc_pclk 3 8>; }; gpio4: gpio@8000e100 { @@ -166,8 +117,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <4>; - - clocks = <&prcc_pclk 3 8>; }; gpio5: gpio@8000e180 { @@ -181,8 +130,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <5>; - - clocks = <&prcc_pclk 3 8>; }; gpio6: gpio@8011e000 { @@ -196,8 +143,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <6>; - - clocks = <&prcc_pclk 2 11>; }; gpio7: gpio@8011e080 { @@ -211,8 +156,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <7>; - - clocks = <&prcc_pclk 2 11>; }; gpio8: gpio@a03fe000 { @@ -226,8 +169,6 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <8>; - - clocks = <&prcc_pclk 5 1>; }; pinctrl { @@ -236,7 +177,8 @@ }; usb_per5@a03e0000 { - compatible = "stericsson,db8500-musb"; + compatible = "stericsson,db8500-musb", + "mentor,musb"; reg = <0xa03e0000 0x10000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; @@ -268,8 +210,6 @@ "iep_6_14", "oep_6_14", "iep_7_15", "oep_7_15", "iep_8", "oep_8"; - - clocks = <&prcc_pclk 5 0>; }; dma: dma-controller@801C0000 { @@ -280,8 +220,6 @@ #dma-cells = <3>; memcpy-channels = <56 57 58 59 60>; - - clocks = <&prcmu_clk PRCMU_DMACLK>; }; prcmu: prcmu@80157000 { @@ -300,13 +238,6 @@ reg = <0x80157450 0xC>; }; - cpufreq { - compatible = "stericsson,cpufreq-ux500"; - clocks = <&prcmu_clk PRCMU_ARMSS>; - clock-names = "armss"; - status = "disabled"; - }; - thermal@801573c0 { compatible = "stericsson,db8500-thermal"; reg = <0x801573c0 0x40>; @@ -628,74 +559,65 @@ compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; - clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; - clock-names = "i2cclk", "apb_pclk"; }; i2c@80122000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; - clock-names = "i2cclk", "apb_pclk"; }; i2c@80128000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; - clock-names = "i2cclk", "apb_pclk"; }; i2c@80110000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; + arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; - - clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; - clock-names = "i2cclk", "apb_pclk"; }; i2c@8012a000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + arm,primecell-periphid = <0x180024>; #address-cells = <1>; #size-cells = <0>; v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; - - clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; - clock-names = "i2cclk", "apb_pclk"; }; ssp@80002000 { @@ -704,80 +626,7 @@ interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "ssp0clk", "apb_pclk"; - dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ - <&dma 8 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - }; - - ssp@80003000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80003000 0x1000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "ssp1clk", "apb_pclk"; - dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ - <&dma 9 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - }; - - spi@8011a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8011a000 0x1000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "spi0clk", "apb_pclk"; - dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ - <&dma 0 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - }; - - spi@80112000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80112000 0x1000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "spi1clk", "apb_pclk"; - dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ - <&dma 35 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - }; - - spi@80111000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80111000 0x1000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "spi2clk", "apb_pclk"; - dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ - <&dma 33 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; - }; - - spi@80129000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x80129000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - /* Same clock wired to kernel and pclk */ - clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "spi3clk", "apb_pclk"; - dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ - <&dma 40 0 0x0>; /* Logical - MemToDev */ - dma-names = "rx", "tx"; + status = "disabled"; }; uart@80120000 { @@ -789,9 +638,6 @@ <&dma 13 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; }; @@ -804,9 +650,6 @@ <&dma 12 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; }; @@ -819,9 +662,6 @@ <&dma 11 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; - clock-names = "uart", "apb_pclk"; - status = "disabled"; }; @@ -834,9 +674,6 @@ <&dma 29 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; - clock-names = "sdi", "apb_pclk"; - status = "disabled"; }; @@ -849,9 +686,6 @@ <&dma 32 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; - clock-names = "sdi", "apb_pclk"; - status = "disabled"; }; @@ -864,9 +698,6 @@ <&dma 28 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; - clock-names = "sdi", "apb_pclk"; - status = "disabled"; }; @@ -874,10 +705,6 @@ compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; - clock-names = "sdi", "apb_pclk"; - status = "disabled"; }; @@ -890,9 +717,6 @@ <&dma 42 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; - clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; - clock-names = "sdi", "apb_pclk"; - status = "disabled"; }; @@ -900,10 +724,6 @@ compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; - clock-names = "sdi", "apb_pclk"; - status = "disabled"; }; @@ -912,10 +732,6 @@ reg = <0x80123000 0x1000>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; - - clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; - clock-names = "msp", "apb_pclk"; - status = "disabled"; }; @@ -924,10 +740,6 @@ reg = <0x80124000 0x1000>; interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; - - clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; - clock-names = "msp", "apb_pclk"; - status = "disabled"; }; @@ -937,10 +749,6 @@ reg = <0x80117000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; - - clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; - clock-names = "msp", "apb_pclk"; - status = "disabled"; }; @@ -949,10 +757,6 @@ reg = <0x80125000 0x1000>; interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; - - clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; - clock-names = "msp", "apb_pclk"; - status = "disabled"; }; @@ -968,7 +772,7 @@ cpufreq-cooling { compatible = "stericsson,db8500-cpufreq-cooling"; status = "disabled"; - }; + }; vmmci: regulator-gpio { compatible = "regulator-gpio"; @@ -993,7 +797,6 @@ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; - clocks = <&prcc_pclk 6 1>; }; hash@a03c2000 { @@ -1001,7 +804,6 @@ reg = <0xa03c2000 0x1000>; v-ape-supply = <&db8500_vape_reg>; - clocks = <&prcc_pclk 6 2>; }; }; }; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi deleted file mode 100644 index 76d3ef1..0000000 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the TVK1281618 UIB - */ - -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - soc { - /* Add Synaptics touch screen, TC35892 keypad etc here */ - i2c@80004000 { - tc3589x@44 { - compatible = "tc3589x"; - reg = <0x44>; - interrupt-parent = <&gpio6>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - - tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index aa3f020..370e03f 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -41,6 +41,28 @@ status = "okay"; }; + i2c@80004000 { + tc3589x@42 { + compatible = "tc3589x"; + reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + i2c@80128000 { lp5521@33 { compatible = "national,lp5521"; @@ -50,7 +72,6 @@ chan0 { led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; - linux,default-trigger = "heartbeat"; }; chan1 { led-cur = /bits/ 8 <0x2f>; @@ -81,7 +102,7 @@ }; bh1780@29 { compatible = "rohm,bh1780gli"; - reg = <0x29>; + reg = <0x33>; }; }; @@ -146,11 +167,89 @@ }; prcmu@80157000 { - ab8500 { - ab8500-gpio { - compatible = "stericsson,ab8500-gpio"; + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; }; + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts deleted file mode 100644 index 2b1cb5b..0000000 --- a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-hrefprev60.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and ST UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - touch-gpio = <&gpio2 12 0x4>; - reset-gpio = <&tc3589x_gpio 13 0x4>; - }; - bu21013_tp@5d { - touch-gpio = <&gpio2 12 0x4>; - reset-gpio = <&tc3589x_gpio 13 0x4>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts deleted file mode 100644 index 59523f8..0000000 --- a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "ste-hrefprev60.dtsi" -#include "ste-href-tvk1281618.dtsi" - -/ { - model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB"; - compatible = "st-ericsson,mop500", "st-ericsson,u8500"; -}; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dts index b2cd7bc..d8d3b99 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dts @@ -7,14 +7,17 @@ * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the HREF+ prior to the v60 variant. */ +/dts-v1/; #include "ste-dbx5x0.dtsi" #include "ste-href.dtsi" +#include "ste-stuib.dtsi" / { + model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; + compatible = "st-ericsson,mop500", "st-ericsson,u8500"; + gpio_keys { button@1 { gpios = <&tc3589x_gpio 7 0x4>; @@ -22,30 +25,24 @@ }; soc { + prcmu@80157000 { + ab8500@5 { + ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; + }; + }; + }; + i2c@80004000 { tps61052@33 { compatible = "tps61052"; reg = <0x33>; }; + }; - tc3589x@42 { - compatible = "tc3589x"; - reg = <0x42>; - interrupt-parent = <&gpio6>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - - tc3589x_gpio: tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; + i2c@80110000 { + bu21013_tp@5c { + reset-gpio = <&tc3589x_gpio 13 0x4>; }; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts deleted file mode 100644 index 8c6a2de..0000000 --- a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the HREF version 60 or later with the ST UIB - */ - -/dts-v1/; -#include "ste-hrefv60plus.dtsi" -#include "ste-href-stuib.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and ST UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - soc { - /* Reset line for the BU21013 touchscreen */ - i2c@80110000 { - /* Only one of these will be used */ - bu21013_tp@5c { - touch-gpio = <&gpio2 20 0x4>; - reset-gpio = <&gpio4 17 0x4>; - }; - bu21013_tp@5d { - touch-gpio = <&gpio2 20 0x4>; - reset-gpio = <&gpio4 17 0x4>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts deleted file mode 100644 index d53cccd..0000000 --- a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Device Tree for the HREF version 60 or later with the TVK1281618 UIB - */ - -/dts-v1/; -#include "ste-hrefv60plus.dtsi" -#include "ste-href-tvk1281618.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; -}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts new file mode 100644 index 0000000..6e52ebb --- /dev/null +++ b/arch/arm/boot/dts/ste-hrefv60plus.dts @@ -0,0 +1,210 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "ste-dbx5x0.dtsi" +#include "ste-href.dtsi" +#include "ste-stuib.dtsi" + +/ { + model = "ST-Ericsson HREF (v60+) platform with Device Tree"; + compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; + + gpio_keys { + button@1 { + gpios = <&gpio6 25 0x4>; + }; + }; + + soc { + i2c@80110000 { + bu21013_tp@0x5c { + reset-gpio = <&gpio4 15 0x4>; + }; + }; + + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + mmc-cap-sd-highspeed; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + + cd-gpios = <&tc3589x_gpio 3 0x4>; + + status = "okay"; + }; + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + + status = "okay"; + }; + + // PoP:ed eMMC + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + + status = "okay"; + }; + + // On-board eMMC + sdi4_per2@80114000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; + vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; + }; + + prcmu@80157000 { + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; + }; + + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500 { + ab8500-regulators { + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-name = "V-DISPLAY"; + }; + + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-name = "V-eMMC1"; + }; + + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-name = "V-MMC-SD"; + }; + + ab8500_ldo_intcore_reg: ab8500_ldo_intcore { + regulator-name = "V-INTCORE"; + }; + + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-name = "V-TVOUT"; + }; + + ab8500_ldo_usb_reg: ab8500_ldo_usb { + regulator-name = "dummy"; + }; + + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-name = "V-AUD"; + }; + + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-name = "V-AMIC1"; + }; + + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-name = "V-AMIC2"; + }; + + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-name = "V-DMIC"; + }; + + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi deleted file mode 100644 index aed511b..0000000 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2012 ST-Ericsson AB - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "ste-dbx5x0.dtsi" -#include "ste-href.dtsi" - -/ { - model = "ST-Ericsson HREF (v60+) platform with Device Tree"; - compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - - gpio_keys { - button@1 { - gpios = <&gpio5 25 0x4>; - }; - }; - - soc { - // External Micro SD slot - sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - - cd-gpios = <&gpio2 31 0x4>; // 95 - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 79425e3..9169d30 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -653,7 +653,6 @@ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; clocks = <&hclksmc>; status = "okay"; - timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; partition@0 { label = "X-Loader(NAND)"; @@ -708,14 +707,8 @@ pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; stw4811@2d { - compatible = "st,stw4811"; - reg = <0x2d>; - vmmc_regulator: vmmc { - compatible = "st,stw481x-vmmc"; - regulator-name = "VMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; + compatible = "st,stw4811"; + reg = <0x2d>; }; }; @@ -846,7 +839,6 @@ cd-inverted; pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; - vmmc-supply = <&vmmc_regulator>; }; }; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index f0b39f8..f1fc128 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -111,13 +111,12 @@ vdd33a-supply = <&en_3v3_reg>; vddvario-supply = <&db8500_vape_reg>; + reg-shift = <1>; reg-io-width = <2>; smsc,force-internal-phy; smsc,irq-active-high; smsc,irq-push-pull; - - clocks = <&prcc_pclk 3 0>; }; }; @@ -171,8 +170,86 @@ }; prcmu@80157000 { - cpufreq { - status = "okay"; + db8500-prcmu-regulators { + db8500_vape_reg: db8500_vape { + regulator-name = "db8500-vape"; + }; + + db8500_varm_reg: db8500_varm { + regulator-name = "db8500-varm"; + }; + + db8500_vmodem_reg: db8500_vmodem { + regulator-name = "db8500-vmodem"; + }; + + db8500_vpll_reg: db8500_vpll { + regulator-name = "db8500-vpll"; + }; + + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-name = "db8500-vsmps1"; + }; + + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-name = "db8500-vsmps2"; + }; + + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-name = "db8500-vsmps3"; + }; + + db8500_vrf1_reg: db8500_vrf1 { + regulator-name = "db8500-vrf1"; + }; + + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-name = "db8500-sva-mmdsp"; + }; + + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-name = "db8500_sva_pipe"; + }; + + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-name = "db8500_sia_mmdsp"; + }; + + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-name = "db8500-sia-pipe"; + }; + + db8500_sga_reg: db8500_sga { + regulator-name = "db8500-sga"; + }; + + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-name = "db8500-b2r2-mcde"; + }; + + db8500_esram12_reg: db8500_esram12 { + regulator-name = "db8500-esram12"; + }; + + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-name = "db8500-esram12-ret"; + }; + + db8500_esram34_reg: db8500_esram34 { + regulator-name = "db8500-esram34"; + }; + + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-name = "db8500-esram34-ret"; + }; }; thermal@801573c0 { diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-stuib.dtsi index 76704ec..524e332 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-stuib.dtsi @@ -57,6 +57,7 @@ bu21013_tp@5c { compatible = "rohm,bu21013_tp"; reg = <0x5c>; + touch-gpio = <&gpio2 20 0x4>; avdd-supply = <&ab8500_ldo_aux1_reg>; rohm,touch-max-x = <384>; @@ -67,6 +68,7 @@ bu21013_tp@5d { compatible = "rohm,bu21013_tp"; reg = <0x5d>; + touch-gpio = <&gpio2 20 0x4>; avdd-supply = <&ab8500_ldo_aux1_reg>; rohm,touch-max-x = <384>; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 319cc6b..c32770a 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -266,11 +266,6 @@ reg = <0x01c20c90 0x10>; }; - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-sid"; - reg = <0x01c23800 0x10>; - }; - uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 5247674..3b4a057 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -255,11 +255,6 @@ reg = <0x01c20c90 0x10>; }; - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-sid"; - reg = <0x01c23800 0x10>; - }; - uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index ce8ef2a..f6091dc 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -222,11 +222,6 @@ reg = <0x01c20c90 0x10>; }; - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-sid"; - reg = <0x01c23800 0x10>; - }; - uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c1751a6..f244f5f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -175,7 +175,7 @@ apb2_gates: apb2_gates@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; + reg = <0x01c2006c 0x8>; clocks = <&apb2>; clock-output-names = "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", "apb2_i2c3", "apb2_uart0", diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 5c51cb8..15e625e 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -48,18 +48,6 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; }; leds { diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts deleted file mode 100644 index 8a1009d..0000000 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2013 Oliver Schinagl - * - * Oliver Schinagl <oliver@schinagl.nl> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "sun7i-a20.dtsi" - -/ { - model = "Cubietech Cubietruck"; - compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; - - soc@01c00000 { - pinctrl@01c20800 { - led_pins_cubietruck: led_pins@0 { - allwinner,pins = "PH7", "PH11", "PH20", "PH21"; - allwinner,function = "gpio_out"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - }; - - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubietruck>; - - blue { - label = "cubietruck:blue:usr"; - gpios = <&pio 7 21 0>; - }; - - orange { - label = "cubietruck:orange:usr"; - gpios = <&pio 7 20 0>; - }; - - white { - label = "cubietruck:white:usr"; - gpios = <&pio 7 11 0>; - }; - - green { - label = "cubietruck:green:usr"; - gpios = <&pio 7 7 0>; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index ead3013..9e77855 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -60,24 +60,6 @@ pinctrl-0 = <&uart7_pins_a>; status = "okay"; }; - - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - i2c1: i2c@01c2b000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - i2c2: i2c@01c2b400 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; - }; }; leds { diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e46cfed..80559cb 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -215,27 +215,6 @@ allwinner,pull = <0>; }; - i2c0_pins_a: i2c0@0 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "i2c0"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - i2c1_pins_a: i2c1@0 { - allwinner,pins = "PB18", "PB19"; - allwinner,function = "i2c1"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - - i2c2_pins_a: i2c2@0 { - allwinner,pins = "PB20", "PB21"; - allwinner,function = "i2c2"; - allwinner,drive = <0>; - allwinner,pull = <0>; - }; - emac_pins_a: emac0@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", @@ -265,11 +244,6 @@ reg = <0x01c20c90 0x10>; }; - sid: eeprom@01c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200>; - }; - uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -350,51 +324,6 @@ status = "disabled"; }; - i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <0 7 1>; - clocks = <&apb1_gates 0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <0 8 1>; - clocks = <&apb1_gates 1>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <0 9 1>; - clocks = <&apb1_gates 2>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c3: i2c@01c2b800 { - compatible = "allwinner,sun4i-i2c"; - reg = <0x01c2b800 0x400>; - interrupts = <0 88 1>; - clocks = <&apb1_gates 3>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c4: i2c@01c2bc00 { - compatible = "allwinner,sun4i-i2c"; - reg = <0x01c2bc00 0x400>; - interrupts = <0 89 1>; - clocks = <&apb1_gates 15>; - clock-frequency = <100000>; - status = "disabled"; - }; - gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index cb5ec23..6023028 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1,6 +1,5 @@ /dts-v1/; -#include <dt-bindings/input/input.h> #include "tegra114.dtsi" / { @@ -739,14 +738,6 @@ realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; }; - - temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&palmas_ldo6_reg>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>; - }; }; i2c@7000d000 { @@ -956,7 +947,7 @@ regulator-max-microvolt = <1800000>; }; - palmas_ldo6_reg: ldo6 { + ldo6 { regulator-name = "vdd-sensor-2v85"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; @@ -1020,19 +1011,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; }; }; @@ -1103,26 +1081,26 @@ home { label = "Home"; gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - linux,code = <KEY_HOME>; + linux,code = <102>; /* KEY_HOME */ }; power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; + linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; volume_down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; + linux,code = <114>; /* KEY_VOLUMEDOWN */ }; volume_up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; + linux,code = <115>; /* KEY_VOLUMEUP */ }; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8d42787..2905145 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -318,9 +318,9 @@ iommu { compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; - reg = <0x70019010 0x02c - 0x700191f0 0x010 - 0x70019228 0x074>; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x074>; nvidia,#asids = <4>; dma-window = <0 0x40000000>; nvidia,swgroups = <0x18659fe>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts deleted file mode 100644 index 431d67a..0000000 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ /dev/null @@ -1,27 +0,0 @@ -/dts-v1/; - -#include "tegra124.dtsi" - -/ { - model = "NVIDIA Tegra124 Venice2"; - compatible = "nvidia,venice2", "nvidia,tegra124"; - - memory { - reg = <0x80000000 0x80000000>; - }; - - serial@70006000 { - status = "okay"; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; -}; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi deleted file mode 100644 index b741300..0000000 --- a/arch/arm/boot/dts/tegra124.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -#include <dt-bindings/gpio/tegra-gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -#include "skeleton.dtsi" - -/ { - compatible = "nvidia,tegra124"; - interrupt-parent = <&gic>; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x50041000 0x1000>, - <0x50042000 0x1000>, - <0x50044000 0x2000>, - <0x50046000 0x2000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the comptible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - serial@70006000 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - serial@70006040 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; - reg-shift = <2>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - serial@70006200 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x40>; - reg-shift = <2>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - serial@70006300 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x40>; - reg-shift = <2>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - serial@70006400 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x40>; - reg-shift = <2>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmc@7000e400 { - compatible = "nvidia,tegra124-pmc"; - reg = <0x7000e400 0x400>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 5ea7dfa..e19dbf2 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -294,10 +294,9 @@ }; }; - temperature-sensor@4c { + nct1008 { compatible = "onnn,nct1008"; reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2bd55cf..0022c12 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -136,13 +136,12 @@ gr3d { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D - &tegra_car TEGRA30_CLK_GR3D2>; + clocks = <&tegra_car 24 &tegra_car 98>; clock-names = "3d", "3d2"; }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi deleted file mode 100644 index c843720..0000000 --- a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi +++ /dev/null @@ -1,58 +0,0 @@ - -/ { - testcase-data { - interrupts { - #address-cells = <1>; - #size-cells = <1>; - test_intc0: intc0 { - interrupt-controller; - #interrupt-cells = <1>; - }; - - test_intc1: intc1 { - interrupt-controller; - #interrupt-cells = <3>; - }; - - test_intc2: intc2 { - interrupt-controller; - #interrupt-cells = <2>; - }; - - test_intmap0: intmap0 { - #interrupt-cells = <1>; - #address-cells = <0>; - interrupt-map = <1 &test_intc0 9>, - <2 &test_intc1 10 11 12>, - <3 &test_intc2 13 14>, - <4 &test_intc2 15 16>; - }; - - test_intmap1: intmap1 { - #interrupt-cells = <2>; - interrupt-map = <0x5000 1 2 &test_intc0 15>; - }; - - interrupts0 { - interrupt-parent = <&test_intc0>; - interrupts = <1>, <2>, <3>, <4>; - }; - - interrupts1 { - interrupt-parent = <&test_intmap0>; - interrupts = <1>, <2>, <3>, <4>; - }; - - interrupts-extended0 { - reg = <0x5000 0x100>; - interrupts-extended = <&test_intc0 1>, - <&test_intc1 2 3 4>, - <&test_intc2 5 6>, - <&test_intmap0 1>, - <&test_intmap0 2>, - <&test_intmap0 3>, - <&test_intmap1 1 2>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi index 3f123ec..a7c5067 100644 --- a/arch/arm/boot/dts/testcases/tests.dtsi +++ b/arch/arm/boot/dts/testcases/tests.dtsi @@ -1,2 +1 @@ /include/ "tests-phandle.dtsi" -/include/ "tests-interrupts.dtsi" diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 4217096..ae6a17a 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -19,32 +19,10 @@ interrupts = <11>; }; - charger: bci { - compatible = "ti,twl4030-bci"; - interrupts = <9>, <2>; - bci3v1-supply = <&vusb3v1>; - }; - watchdog { compatible = "ti,twl4030-wdt"; }; - vaux1: regulator-vaux1 { - compatible = "ti,twl4030-vaux1"; - }; - - vaux2: regulator-vaux2 { - compatible = "ti,twl4030-vaux2"; - }; - - vaux3: regulator-vaux3 { - compatible = "ti,twl4030-vaux3"; - }; - - vaux4: regulator-vaux4 { - compatible = "ti,twl4030-vaux4"; - }; - vcc: regulator-vdd1 { compatible = "ti,twl4030-vdd1"; regulator-min-microvolt = <600000>; @@ -57,20 +35,10 @@ regulator-max-microvolt = <1800000>; }; - vio: regulator-vio { - compatible = "ti,twl4030-vio"; - }; - - vintana1: regulator-vintana1 { - compatible = "ti,twl4030-vintana1"; - }; - - vintana2: regulator-vintana2 { - compatible = "ti,twl4030-vintana2"; - }; - - vintdig: regulator-vintdig { - compatible = "ti,twl4030-vintdig"; + vpll2: regulator-vpll2 { + compatible = "ti,twl4030-vpll2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vmmc1: regulator-vmmc1 { @@ -97,16 +65,6 @@ compatible = "ti,twl4030-vusb3v1"; }; - vpll1: regulator-vpll1 { - compatible = "ti,twl4030-vpll1"; - }; - - vpll2: regulator-vpll2 { - compatible = "ti,twl4030-vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vsim: regulator-vsim { compatible = "ti,twl4030-vsim"; regulator-min-microvolt = <1800000>; @@ -128,7 +86,6 @@ usb1v8-supply = <&vusb1v8>; usb3v1-supply = <&vusb3v1>; usb_mode = <1>; - #phy-cells = <0>; }; twl_pwm: pwm { @@ -140,9 +97,4 @@ compatible = "ti,twl4030-pwmled"; #pwm-cells = <2>; }; - - twl_pwrbutton: pwrbutton { - compatible = "ti,twl4030-pwrbutton"; - interrupts = <8>; - }; }; diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi deleted file mode 100644 index a4fa570..0000000 --- a/arch/arm/boot/dts/twl6030_omap4.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -&twl { - /* - * On most OMAP4 platforms, the twl6030 IRQ line is connected - * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is - * connected to the fref_clk0_out.sys_drm_msecure line. - * Therefore, configure the defaults for the SYS_NIRQ1 and - * fref_clk0_out.sys_drm_msecure pins here. - */ - pinctrl-names = "default"; - pinctrl-0 = < - &twl6030_pins - &twl6030_wkup_pins - >; -}; - -&omap4_pmx_wkup { - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { - pinctrl-single,pins = < - 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ - >; - }; -}; - -&omap4_pmx_core { - twl6030_pins: pinmux_twl6030_pins { - pinctrl-single,pins = < - 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ - >; - }; -}; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index e01e5a0..dde75ae 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -185,7 +185,7 @@ mmc@5000 { compatible = "arm,primecell"; reg = < 0x5000 0x1000>; - interrupts-extended = <&vic 22 &sic 2>; + interrupts = <22 34>; }; kmi@6000 { compatible = "arm,pl050", "arm,primecell"; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index f43907c..7e81752 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -41,7 +41,7 @@ mmc@b000 { compatible = "arm,primecell"; reg = <0xb000 0x1000>; - interrupts-extended = <&vic 23 &sic 2>; + interrupts = <23 34>; }; }; }; diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts deleted file mode 100644 index c42e4f9..0000000 --- a/arch/arm/boot/dts/vf610-cosmic.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/dts-v1/; -#include "vf610.dtsi" - -/ { - model = "PHYTEC Cosmic/Cosmic+ Board"; - compatible = "phytec,vf610-cosmic", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP1,115200"; - }; - - memory { - reg = <0x80000000 0x10000000>; - }; - - clocks { - enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - }; - -}; - -&fec1 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1_1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index c8047ca..1a58678 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -36,23 +36,6 @@ }; -&dspi0 { - bus-num = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dspi0_1>; - status = "okay"; - - sflash: at26df081a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at26df081a"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b..67d929c 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -123,18 +123,6 @@ status = "disabled"; }; - dspi0: dspi0@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <0 67 0x04>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - status = "disabled"; - }; - sai2: sai@40031000 { compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index e7f73b2..e32b92b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -92,14 +92,6 @@ }; }; - global_timer: timer@f8f00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xf8f00200 0x20>; - interrupts = <1 11 0x301>; - interrupt-parent = <&intc>; - clocks = <&clkc 4>; - }; - ttc0: ttc0@f8001000 { interrupt-parent = <&intc>; interrupts = < 0 10 4 0 11 4 0 12 4 >; diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 4bdc416..8c60f47 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -6,6 +6,7 @@ obj-y += firmware.o obj-$(CONFIG_ICST) += icst.o obj-$(CONFIG_SA1111) += sa1111.o +obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o @@ -16,5 +17,3 @@ obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o AFLAGS_mcpm_head.o := -march=armv7-a AFLAGS_vlock.o := -march=armv7-a obj-$(CONFIG_TI_PRIV_EDMA) += edma.o -obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o -obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c deleted file mode 100644 index 5774b6e..0000000 --- a/arch/arm/common/bL_switcher.c +++ /dev/null @@ -1,822 +0,0 @@ -/* - * arch/arm/common/bL_switcher.c -- big.LITTLE cluster switcher core driver - * - * Created by: Nicolas Pitre, March 2012 - * Copyright: (C) 2012-2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/atomic.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/cpu_pm.h> -#include <linux/cpu.h> -#include <linux/cpumask.h> -#include <linux/kthread.h> -#include <linux/wait.h> -#include <linux/time.h> -#include <linux/clockchips.h> -#include <linux/hrtimer.h> -#include <linux/tick.h> -#include <linux/notifier.h> -#include <linux/mm.h> -#include <linux/mutex.h> -#include <linux/smp.h> -#include <linux/spinlock.h> -#include <linux/string.h> -#include <linux/sysfs.h> -#include <linux/irqchip/arm-gic.h> -#include <linux/moduleparam.h> - -#include <asm/smp_plat.h> -#include <asm/cputype.h> -#include <asm/suspend.h> -#include <asm/mcpm.h> -#include <asm/bL_switcher.h> - -#define CREATE_TRACE_POINTS -#include <trace/events/power_cpu_migrate.h> - - -/* - * Use our own MPIDR accessors as the generic ones in asm/cputype.h have - * __attribute_const__ and we don't want the compiler to assume any - * constness here as the value _does_ change along some code paths. - */ - -static int read_mpidr(void) -{ - unsigned int id; - asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (id)); - return id & MPIDR_HWID_BITMASK; -} - -/* - * Get a global nanosecond time stamp for tracing. - */ -static s64 get_ns(void) -{ - struct timespec ts; - getnstimeofday(&ts); - return timespec_to_ns(&ts); -} - -/* - * bL switcher core code. - */ - -static void bL_do_switch(void *_arg) -{ - unsigned ib_mpidr, ib_cpu, ib_cluster; - long volatile handshake, **handshake_ptr = _arg; - - pr_debug("%s\n", __func__); - - ib_mpidr = cpu_logical_map(smp_processor_id()); - ib_cpu = MPIDR_AFFINITY_LEVEL(ib_mpidr, 0); - ib_cluster = MPIDR_AFFINITY_LEVEL(ib_mpidr, 1); - - /* Advertise our handshake location */ - if (handshake_ptr) { - handshake = 0; - *handshake_ptr = &handshake; - } else - handshake = -1; - - /* - * Our state has been saved at this point. Let's release our - * inbound CPU. - */ - mcpm_set_entry_vector(ib_cpu, ib_cluster, cpu_resume); - sev(); - - /* - * From this point, we must assume that our counterpart CPU might - * have taken over in its parallel world already, as if execution - * just returned from cpu_suspend(). It is therefore important to - * be very careful not to make any change the other guy is not - * expecting. This is why we need stack isolation. - * - * Fancy under cover tasks could be performed here. For now - * we have none. - */ - - /* - * Let's wait until our inbound is alive. - */ - while (!handshake) { - wfe(); - smp_mb(); - } - - /* Let's put ourself down. */ - mcpm_cpu_power_down(); - - /* should never get here */ - BUG(); -} - -/* - * Stack isolation. To ensure 'current' remains valid, we just use another - * piece of our thread's stack space which should be fairly lightly used. - * The selected area starts just above the thread_info structure located - * at the very bottom of the stack, aligned to a cache line, and indexed - * with the cluster number. - */ -#define STACK_SIZE 512 -extern void call_with_stack(void (*fn)(void *), void *arg, void *sp); -static int bL_switchpoint(unsigned long _arg) -{ - unsigned int mpidr = read_mpidr(); - unsigned int clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); - void *stack = current_thread_info() + 1; - stack = PTR_ALIGN(stack, L1_CACHE_BYTES); - stack += clusterid * STACK_SIZE + STACK_SIZE; - call_with_stack(bL_do_switch, (void *)_arg, stack); - BUG(); -} - -/* - * Generic switcher interface - */ - -static unsigned int bL_gic_id[MAX_CPUS_PER_CLUSTER][MAX_NR_CLUSTERS]; -static int bL_switcher_cpu_pairing[NR_CPUS]; - -/* - * bL_switch_to - Switch to a specific cluster for the current CPU - * @new_cluster_id: the ID of the cluster to switch to. - * - * This function must be called on the CPU to be switched. - * Returns 0 on success, else a negative status code. - */ -static int bL_switch_to(unsigned int new_cluster_id) -{ - unsigned int mpidr, this_cpu, that_cpu; - unsigned int ob_mpidr, ob_cpu, ob_cluster, ib_mpidr, ib_cpu, ib_cluster; - struct completion inbound_alive; - struct tick_device *tdev; - enum clock_event_mode tdev_mode; - long volatile *handshake_ptr; - int ipi_nr, ret; - - this_cpu = smp_processor_id(); - ob_mpidr = read_mpidr(); - ob_cpu = MPIDR_AFFINITY_LEVEL(ob_mpidr, 0); - ob_cluster = MPIDR_AFFINITY_LEVEL(ob_mpidr, 1); - BUG_ON(cpu_logical_map(this_cpu) != ob_mpidr); - - if (new_cluster_id == ob_cluster) - return 0; - - that_cpu = bL_switcher_cpu_pairing[this_cpu]; - ib_mpidr = cpu_logical_map(that_cpu); - ib_cpu = MPIDR_AFFINITY_LEVEL(ib_mpidr, 0); - ib_cluster = MPIDR_AFFINITY_LEVEL(ib_mpidr, 1); - - pr_debug("before switch: CPU %d MPIDR %#x -> %#x\n", - this_cpu, ob_mpidr, ib_mpidr); - - this_cpu = smp_processor_id(); - - /* Close the gate for our entry vectors */ - mcpm_set_entry_vector(ob_cpu, ob_cluster, NULL); - mcpm_set_entry_vector(ib_cpu, ib_cluster, NULL); - - /* Install our "inbound alive" notifier. */ - init_completion(&inbound_alive); - ipi_nr = register_ipi_completion(&inbound_alive, this_cpu); - ipi_nr |= ((1 << 16) << bL_gic_id[ob_cpu][ob_cluster]); - mcpm_set_early_poke(ib_cpu, ib_cluster, gic_get_sgir_physaddr(), ipi_nr); - - /* - * Let's wake up the inbound CPU now in case it requires some delay - * to come online, but leave it gated in our entry vector code. - */ - ret = mcpm_cpu_power_up(ib_cpu, ib_cluster); - if (ret) { - pr_err("%s: mcpm_cpu_power_up() returned %d\n", __func__, ret); - return ret; - } - - /* - * Raise a SGI on the inbound CPU to make sure it doesn't stall - * in a possible WFI, such as in bL_power_down(). - */ - gic_send_sgi(bL_gic_id[ib_cpu][ib_cluster], 0); - - /* - * Wait for the inbound to come up. This allows for other - * tasks to be scheduled in the mean time. - */ - wait_for_completion(&inbound_alive); - mcpm_set_early_poke(ib_cpu, ib_cluster, 0, 0); - - /* - * From this point we are entering the switch critical zone - * and can't take any interrupts anymore. - */ - local_irq_disable(); - local_fiq_disable(); - trace_cpu_migrate_begin(get_ns(), ob_mpidr); - - /* redirect GIC's SGIs to our counterpart */ - gic_migrate_target(bL_gic_id[ib_cpu][ib_cluster]); - - tdev = tick_get_device(this_cpu); - if (tdev && !cpumask_equal(tdev->evtdev->cpumask, cpumask_of(this_cpu))) - tdev = NULL; - if (tdev) { - tdev_mode = tdev->evtdev->mode; - clockevents_set_mode(tdev->evtdev, CLOCK_EVT_MODE_SHUTDOWN); - } - - ret = cpu_pm_enter(); - - /* we can not tolerate errors at this point */ - if (ret) - panic("%s: cpu_pm_enter() returned %d\n", __func__, ret); - - /* Swap the physical CPUs in the logical map for this logical CPU. */ - cpu_logical_map(this_cpu) = ib_mpidr; - cpu_logical_map(that_cpu) = ob_mpidr; - - /* Let's do the actual CPU switch. */ - ret = cpu_suspend((unsigned long)&handshake_ptr, bL_switchpoint); - if (ret > 0) - panic("%s: cpu_suspend() returned %d\n", __func__, ret); - - /* We are executing on the inbound CPU at this point */ - mpidr = read_mpidr(); - pr_debug("after switch: CPU %d MPIDR %#x\n", this_cpu, mpidr); - BUG_ON(mpidr != ib_mpidr); - - mcpm_cpu_powered_up(); - - ret = cpu_pm_exit(); - - if (tdev) { - clockevents_set_mode(tdev->evtdev, tdev_mode); - clockevents_program_event(tdev->evtdev, - tdev->evtdev->next_event, 1); - } - - trace_cpu_migrate_finish(get_ns(), ib_mpidr); - local_fiq_enable(); - local_irq_enable(); - - *handshake_ptr = 1; - dsb_sev(); - - if (ret) - pr_err("%s exiting with error %d\n", __func__, ret); - return ret; -} - -struct bL_thread { - spinlock_t lock; - struct task_struct *task; - wait_queue_head_t wq; - int wanted_cluster; - struct completion started; - bL_switch_completion_handler completer; - void *completer_cookie; -}; - -static struct bL_thread bL_threads[NR_CPUS]; - -static int bL_switcher_thread(void *arg) -{ - struct bL_thread *t = arg; - struct sched_param param = { .sched_priority = 1 }; - int cluster; - bL_switch_completion_handler completer; - void *completer_cookie; - - sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m); - complete(&t->started); - - do { - if (signal_pending(current)) - flush_signals(current); - wait_event_interruptible(t->wq, - t->wanted_cluster != -1 || - kthread_should_stop()); - - spin_lock(&t->lock); - cluster = t->wanted_cluster; - completer = t->completer; - completer_cookie = t->completer_cookie; - t->wanted_cluster = -1; - t->completer = NULL; - spin_unlock(&t->lock); - - if (cluster != -1) { - bL_switch_to(cluster); - - if (completer) - completer(completer_cookie); - } - } while (!kthread_should_stop()); - - return 0; -} - -static struct task_struct *bL_switcher_thread_create(int cpu, void *arg) -{ - struct task_struct *task; - - task = kthread_create_on_node(bL_switcher_thread, arg, - cpu_to_node(cpu), "kswitcher_%d", cpu); - if (!IS_ERR(task)) { - kthread_bind(task, cpu); - wake_up_process(task); - } else - pr_err("%s failed for CPU %d\n", __func__, cpu); - return task; -} - -/* - * bL_switch_request_cb - Switch to a specific cluster for the given CPU, - * with completion notification via a callback - * - * @cpu: the CPU to switch - * @new_cluster_id: the ID of the cluster to switch to. - * @completer: switch completion callback. if non-NULL, - * @completer(@completer_cookie) will be called on completion of - * the switch, in non-atomic context. - * @completer_cookie: opaque context argument for @completer. - * - * This function causes a cluster switch on the given CPU by waking up - * the appropriate switcher thread. This function may or may not return - * before the switch has occurred. - * - * If a @completer callback function is supplied, it will be called when - * the switch is complete. This can be used to determine asynchronously - * when the switch is complete, regardless of when bL_switch_request() - * returns. When @completer is supplied, no new switch request is permitted - * for the affected CPU until after the switch is complete, and @completer - * has returned. - */ -int bL_switch_request_cb(unsigned int cpu, unsigned int new_cluster_id, - bL_switch_completion_handler completer, - void *completer_cookie) -{ - struct bL_thread *t; - - if (cpu >= ARRAY_SIZE(bL_threads)) { - pr_err("%s: cpu %d out of bounds\n", __func__, cpu); - return -EINVAL; - } - - t = &bL_threads[cpu]; - - if (IS_ERR(t->task)) - return PTR_ERR(t->task); - if (!t->task) - return -ESRCH; - - spin_lock(&t->lock); - if (t->completer) { - spin_unlock(&t->lock); - return -EBUSY; - } - t->completer = completer; - t->completer_cookie = completer_cookie; - t->wanted_cluster = new_cluster_id; - spin_unlock(&t->lock); - wake_up(&t->wq); - return 0; -} -EXPORT_SYMBOL_GPL(bL_switch_request_cb); - -/* - * Activation and configuration code. - */ - -static DEFINE_MUTEX(bL_switcher_activation_lock); -static BLOCKING_NOTIFIER_HEAD(bL_activation_notifier); -static unsigned int bL_switcher_active; -static unsigned int bL_switcher_cpu_original_cluster[NR_CPUS]; -static cpumask_t bL_switcher_removed_logical_cpus; - -int bL_switcher_register_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&bL_activation_notifier, nb); -} -EXPORT_SYMBOL_GPL(bL_switcher_register_notifier); - -int bL_switcher_unregister_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_unregister(&bL_activation_notifier, nb); -} -EXPORT_SYMBOL_GPL(bL_switcher_unregister_notifier); - -static int bL_activation_notify(unsigned long val) -{ - int ret; - - ret = blocking_notifier_call_chain(&bL_activation_notifier, val, NULL); - if (ret & NOTIFY_STOP_MASK) - pr_err("%s: notifier chain failed with status 0x%x\n", - __func__, ret); - return notifier_to_errno(ret); -} - -static void bL_switcher_restore_cpus(void) -{ - int i; - - for_each_cpu(i, &bL_switcher_removed_logical_cpus) - cpu_up(i); -} - -static int bL_switcher_halve_cpus(void) -{ - int i, j, cluster_0, gic_id, ret; - unsigned int cpu, cluster, mask; - cpumask_t available_cpus; - - /* First pass to validate what we have */ - mask = 0; - for_each_online_cpu(i) { - cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0); - cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1); - if (cluster >= 2) { - pr_err("%s: only dual cluster systems are supported\n", __func__); - return -EINVAL; - } - if (WARN_ON(cpu >= MAX_CPUS_PER_CLUSTER)) - return -EINVAL; - mask |= (1 << cluster); - } - if (mask != 3) { - pr_err("%s: no CPU pairing possible\n", __func__); - return -EINVAL; - } - - /* - * Now let's do the pairing. We match each CPU with another CPU - * from a different cluster. To get a uniform scheduling behavior - * without fiddling with CPU topology and compute capacity data, - * we'll use logical CPUs initially belonging to the same cluster. - */ - memset(bL_switcher_cpu_pairing, -1, sizeof(bL_switcher_cpu_pairing)); - cpumask_copy(&available_cpus, cpu_online_mask); - cluster_0 = -1; - for_each_cpu(i, &available_cpus) { - int match = -1; - cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1); - if (cluster_0 == -1) - cluster_0 = cluster; - if (cluster != cluster_0) - continue; - cpumask_clear_cpu(i, &available_cpus); - for_each_cpu(j, &available_cpus) { - cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(j), 1); - /* - * Let's remember the last match to create "odd" - * pairings on purpose in order for other code not - * to assume any relation between physical and - * logical CPU numbers. - */ - if (cluster != cluster_0) - match = j; - } - if (match != -1) { - bL_switcher_cpu_pairing[i] = match; - cpumask_clear_cpu(match, &available_cpus); - pr_info("CPU%d paired with CPU%d\n", i, match); - } - } - - /* - * Now we disable the unwanted CPUs i.e. everything that has no - * pairing information (that includes the pairing counterparts). - */ - cpumask_clear(&bL_switcher_removed_logical_cpus); - for_each_online_cpu(i) { - cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0); - cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1); - - /* Let's take note of the GIC ID for this CPU */ - gic_id = gic_get_cpu_id(i); - if (gic_id < 0) { - pr_err("%s: bad GIC ID for CPU %d\n", __func__, i); - bL_switcher_restore_cpus(); - return -EINVAL; - } - bL_gic_id[cpu][cluster] = gic_id; - pr_info("GIC ID for CPU %u cluster %u is %u\n", - cpu, cluster, gic_id); - - if (bL_switcher_cpu_pairing[i] != -1) { - bL_switcher_cpu_original_cluster[i] = cluster; - continue; - } - - ret = cpu_down(i); - if (ret) { - bL_switcher_restore_cpus(); - return ret; - } - cpumask_set_cpu(i, &bL_switcher_removed_logical_cpus); - } - - return 0; -} - -/* Determine the logical CPU a given physical CPU is grouped on. */ -int bL_switcher_get_logical_index(u32 mpidr) -{ - int cpu; - - if (!bL_switcher_active) - return -EUNATCH; - - mpidr &= MPIDR_HWID_BITMASK; - for_each_online_cpu(cpu) { - int pairing = bL_switcher_cpu_pairing[cpu]; - if (pairing == -1) - continue; - if ((mpidr == cpu_logical_map(cpu)) || - (mpidr == cpu_logical_map(pairing))) - return cpu; - } - return -EINVAL; -} - -static void bL_switcher_trace_trigger_cpu(void *__always_unused info) -{ - trace_cpu_migrate_current(get_ns(), read_mpidr()); -} - -int bL_switcher_trace_trigger(void) -{ - int ret; - - preempt_disable(); - - bL_switcher_trace_trigger_cpu(NULL); - ret = smp_call_function(bL_switcher_trace_trigger_cpu, NULL, true); - - preempt_enable(); - - return ret; -} -EXPORT_SYMBOL_GPL(bL_switcher_trace_trigger); - -static int bL_switcher_enable(void) -{ - int cpu, ret; - - mutex_lock(&bL_switcher_activation_lock); - lock_device_hotplug(); - if (bL_switcher_active) { - unlock_device_hotplug(); - mutex_unlock(&bL_switcher_activation_lock); - return 0; - } - - pr_info("big.LITTLE switcher initializing\n"); - - ret = bL_activation_notify(BL_NOTIFY_PRE_ENABLE); - if (ret) - goto error; - - ret = bL_switcher_halve_cpus(); - if (ret) - goto error; - - bL_switcher_trace_trigger(); - - for_each_online_cpu(cpu) { - struct bL_thread *t = &bL_threads[cpu]; - spin_lock_init(&t->lock); - init_waitqueue_head(&t->wq); - init_completion(&t->started); - t->wanted_cluster = -1; - t->task = bL_switcher_thread_create(cpu, t); - } - - bL_switcher_active = 1; - bL_activation_notify(BL_NOTIFY_POST_ENABLE); - pr_info("big.LITTLE switcher initialized\n"); - goto out; - -error: - pr_warn("big.LITTLE switcher initialization failed\n"); - bL_activation_notify(BL_NOTIFY_POST_DISABLE); - -out: - unlock_device_hotplug(); - mutex_unlock(&bL_switcher_activation_lock); - return ret; -} - -#ifdef CONFIG_SYSFS - -static void bL_switcher_disable(void) -{ - unsigned int cpu, cluster; - struct bL_thread *t; - struct task_struct *task; - - mutex_lock(&bL_switcher_activation_lock); - lock_device_hotplug(); - - if (!bL_switcher_active) - goto out; - - if (bL_activation_notify(BL_NOTIFY_PRE_DISABLE) != 0) { - bL_activation_notify(BL_NOTIFY_POST_ENABLE); - goto out; - } - - bL_switcher_active = 0; - - /* - * To deactivate the switcher, we must shut down the switcher - * threads to prevent any other requests from being accepted. - * Then, if the final cluster for given logical CPU is not the - * same as the original one, we'll recreate a switcher thread - * just for the purpose of switching the CPU back without any - * possibility for interference from external requests. - */ - for_each_online_cpu(cpu) { - t = &bL_threads[cpu]; - task = t->task; - t->task = NULL; - if (!task || IS_ERR(task)) - continue; - kthread_stop(task); - /* no more switch may happen on this CPU at this point */ - cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1); - if (cluster == bL_switcher_cpu_original_cluster[cpu]) - continue; - init_completion(&t->started); - t->wanted_cluster = bL_switcher_cpu_original_cluster[cpu]; - task = bL_switcher_thread_create(cpu, t); - if (!IS_ERR(task)) { - wait_for_completion(&t->started); - kthread_stop(task); - cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1); - if (cluster == bL_switcher_cpu_original_cluster[cpu]) - continue; - } - /* If execution gets here, we're in trouble. */ - pr_crit("%s: unable to restore original cluster for CPU %d\n", - __func__, cpu); - pr_crit("%s: CPU %d can't be restored\n", - __func__, bL_switcher_cpu_pairing[cpu]); - cpumask_clear_cpu(bL_switcher_cpu_pairing[cpu], - &bL_switcher_removed_logical_cpus); - } - - bL_switcher_restore_cpus(); - bL_switcher_trace_trigger(); - - bL_activation_notify(BL_NOTIFY_POST_DISABLE); - -out: - unlock_device_hotplug(); - mutex_unlock(&bL_switcher_activation_lock); -} - -static ssize_t bL_switcher_active_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - return sprintf(buf, "%u\n", bL_switcher_active); -} - -static ssize_t bL_switcher_active_store(struct kobject *kobj, - struct kobj_attribute *attr, const char *buf, size_t count) -{ - int ret; - - switch (buf[0]) { - case '0': - bL_switcher_disable(); - ret = 0; - break; - case '1': - ret = bL_switcher_enable(); - break; - default: - ret = -EINVAL; - } - - return (ret >= 0) ? count : ret; -} - -static ssize_t bL_switcher_trace_trigger_store(struct kobject *kobj, - struct kobj_attribute *attr, const char *buf, size_t count) -{ - int ret = bL_switcher_trace_trigger(); - - return ret ? ret : count; -} - -static struct kobj_attribute bL_switcher_active_attr = - __ATTR(active, 0644, bL_switcher_active_show, bL_switcher_active_store); - -static struct kobj_attribute bL_switcher_trace_trigger_attr = - __ATTR(trace_trigger, 0200, NULL, bL_switcher_trace_trigger_store); - -static struct attribute *bL_switcher_attrs[] = { - &bL_switcher_active_attr.attr, - &bL_switcher_trace_trigger_attr.attr, - NULL, -}; - -static struct attribute_group bL_switcher_attr_group = { - .attrs = bL_switcher_attrs, -}; - -static struct kobject *bL_switcher_kobj; - -static int __init bL_switcher_sysfs_init(void) -{ - int ret; - - bL_switcher_kobj = kobject_create_and_add("bL_switcher", kernel_kobj); - if (!bL_switcher_kobj) - return -ENOMEM; - ret = sysfs_create_group(bL_switcher_kobj, &bL_switcher_attr_group); - if (ret) - kobject_put(bL_switcher_kobj); - return ret; -} - -#endif /* CONFIG_SYSFS */ - -bool bL_switcher_get_enabled(void) -{ - mutex_lock(&bL_switcher_activation_lock); - - return bL_switcher_active; -} -EXPORT_SYMBOL_GPL(bL_switcher_get_enabled); - -void bL_switcher_put_enabled(void) -{ - mutex_unlock(&bL_switcher_activation_lock); -} -EXPORT_SYMBOL_GPL(bL_switcher_put_enabled); - -/* - * Veto any CPU hotplug operation on those CPUs we've removed - * while the switcher is active. - * We're just not ready to deal with that given the trickery involved. - */ -static int bL_switcher_hotplug_callback(struct notifier_block *nfb, - unsigned long action, void *hcpu) -{ - if (bL_switcher_active) { - int pairing = bL_switcher_cpu_pairing[(unsigned long)hcpu]; - switch (action & 0xf) { - case CPU_UP_PREPARE: - case CPU_DOWN_PREPARE: - if (pairing == -1) - return NOTIFY_BAD; - } - } - return NOTIFY_DONE; -} - -static bool no_bL_switcher; -core_param(no_bL_switcher, no_bL_switcher, bool, 0644); - -static int __init bL_switcher_init(void) -{ - int ret; - - if (MAX_NR_CLUSTERS != 2) { - pr_err("%s: only dual cluster systems are supported\n", __func__); - return -EINVAL; - } - - cpu_notifier(bL_switcher_hotplug_callback, 0); - - if (!no_bL_switcher) { - ret = bL_switcher_enable(); - if (ret) - return ret; - } - -#ifdef CONFIG_SYSFS - ret = bL_switcher_sysfs_init(); - if (ret) - pr_err("%s: unable to create sysfs entry\n", __func__); -#endif - - return 0; -} - -late_initcall(bL_switcher_init); diff --git a/arch/arm/common/bL_switcher_dummy_if.c b/arch/arm/common/bL_switcher_dummy_if.c deleted file mode 100644 index 3f47f12..0000000 --- a/arch/arm/common/bL_switcher_dummy_if.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * arch/arm/common/bL_switcher_dummy_if.c -- b.L switcher dummy interface - * - * Created by: Nicolas Pitre, November 2012 - * Copyright: (C) 2012-2013 Linaro Limited - * - * Dummy interface to user space for debugging purpose only. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/fs.h> -#include <linux/miscdevice.h> -#include <asm/uaccess.h> -#include <asm/bL_switcher.h> - -static ssize_t bL_switcher_write(struct file *file, const char __user *buf, - size_t len, loff_t *pos) -{ - unsigned char val[3]; - unsigned int cpu, cluster; - int ret; - - pr_debug("%s\n", __func__); - - if (len < 3) - return -EINVAL; - - if (copy_from_user(val, buf, 3)) - return -EFAULT; - - /* format: <cpu#>,<cluster#> */ - if (val[0] < '0' || val[0] > '9' || - val[1] != ',' || - val[2] < '0' || val[2] > '1') - return -EINVAL; - - cpu = val[0] - '0'; - cluster = val[2] - '0'; - ret = bL_switch_request(cpu, cluster); - - return ret ? : len; -} - -static const struct file_operations bL_switcher_fops = { - .write = bL_switcher_write, - .owner = THIS_MODULE, -}; - -static struct miscdevice bL_switcher_device = { - MISC_DYNAMIC_MINOR, - "b.L_switcher", - &bL_switcher_fops -}; - -static int __init bL_switcher_dummy_if_init(void) -{ - return misc_register(&bL_switcher_device); -} - -static void __exit bL_switcher_dummy_if_exit(void) -{ - misc_deregister(&bL_switcher_device); -} - -module_init(bL_switcher_dummy_if_init); -module_exit(bL_switcher_dummy_if_exit); diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 41bca32..8e1a024 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -404,7 +404,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) BIT(slot)); if (edma_cc[ctlr]->intr_data[channel].callback) edma_cc[ctlr]->intr_data[channel].callback( - channel, EDMA_DMA_COMPLETE, + channel, DMA_COMPLETE, edma_cc[ctlr]->intr_data[channel].data); } } while (sh_ipr); @@ -459,7 +459,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) callback) { edma_cc[ctlr]->intr_data[k]. callback(k, - EDMA_DMA_CC_ERROR, + DMA_CC_ERROR, edma_cc[ctlr]->intr_data [k].data); } diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index 26020a0..9902509 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -27,18 +27,6 @@ void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr) sync_cache_w(&mcpm_entry_vectors[cluster][cpu]); } -extern unsigned long mcpm_entry_early_pokes[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER][2]; - -void mcpm_set_early_poke(unsigned cpu, unsigned cluster, - unsigned long poke_phys_addr, unsigned long poke_val) -{ - unsigned long *poke = &mcpm_entry_early_pokes[cluster][cpu][0]; - poke[0] = poke_phys_addr; - poke[1] = poke_val; - __cpuc_flush_dcache_area((void *)poke, 8); - outer_clean_range(__pa(poke), __pa(poke + 2)); -} - static const struct mcpm_platform_ops *platform_ops; int __init mcpm_platform_register(const struct mcpm_platform_ops *ops) @@ -102,21 +90,6 @@ void mcpm_cpu_power_down(void) BUG(); } -int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster) -{ - int ret; - - if (WARN_ON_ONCE(!platform_ops || !platform_ops->power_down_finish)) - return -EUNATCH; - - ret = platform_ops->power_down_finish(cpu, cluster); - if (ret) - pr_warn("%s: cpu %u, cluster %u failed to power down (%d)\n", - __func__, cpu, cluster, ret); - - return ret; -} - void mcpm_cpu_suspend(u64 expected_residency) { phys_reset_t phys_reset; diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S index e02db4b..39c96df 100644 --- a/arch/arm/common/mcpm_head.S +++ b/arch/arm/common/mcpm_head.S @@ -15,7 +15,6 @@ #include <linux/linkage.h> #include <asm/mcpm.h> -#include <asm/assembler.h> #include "vlock.h" @@ -48,7 +47,6 @@ ENTRY(mcpm_entry_point) - ARM_BE8(setend be) THUMB( adr r12, BSYM(1f) ) THUMB( bx r12 ) THUMB( .thumb ) @@ -73,19 +71,12 @@ ENTRY(mcpm_entry_point) * position independent way. */ adr r5, 3f - ldmia r5, {r0, r6, r7, r8, r11} - add r0, r5, r0 @ r0 = mcpm_entry_early_pokes + ldmia r5, {r6, r7, r8, r11} add r6, r5, r6 @ r6 = mcpm_entry_vectors ldr r7, [r5, r7] @ r7 = mcpm_power_up_setup_phys add r8, r5, r8 @ r8 = mcpm_sync add r11, r5, r11 @ r11 = first_man_locks - @ Perform an early poke, if any - add r0, r0, r4, lsl #3 - ldmia r0, {r0, r1} - teq r0, #0 - strne r1, [r0] - mov r0, #MCPM_SYNC_CLUSTER_SIZE mla r8, r0, r10, r8 @ r8 = sync cluster base @@ -204,8 +195,7 @@ mcpm_entry_gated: .align 2 -3: .word mcpm_entry_early_pokes - . - .word mcpm_entry_vectors - 3b +3: .word mcpm_entry_vectors - . .word mcpm_power_up_setup_phys - 3b .word mcpm_sync - 3b .word first_man_locks - 3b @@ -224,10 +214,6 @@ first_man_locks: ENTRY(mcpm_entry_vectors) .space 4 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER - .type mcpm_entry_early_pokes, #object -ENTRY(mcpm_entry_early_pokes) - .space 8 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER - .type mcpm_power_up_setup_phys, #object ENTRY(mcpm_power_up_setup_phys) .space 4 @ set by mcpm_sync_init() diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c index 177251a..1bc34c7 100644 --- a/arch/arm/common/mcpm_platsmp.c +++ b/arch/arm/common/mcpm_platsmp.c @@ -19,23 +19,14 @@ #include <asm/smp.h> #include <asm/smp_plat.h> -static void cpu_to_pcpu(unsigned int cpu, - unsigned int *pcpu, unsigned int *pcluster) -{ - unsigned int mpidr; - - mpidr = cpu_logical_map(cpu); - *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); - *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); -} - static int mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned int pcpu, pcluster, ret; + unsigned int mpidr, pcpu, pcluster, ret; extern void secondary_startup(void); - cpu_to_pcpu(cpu, &pcpu, &pcluster); - + mpidr = cpu_logical_map(cpu); + pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); pr_debug("%s: logical CPU %d is physical CPU %d cluster %d\n", __func__, cpu, pcpu, pcluster); @@ -56,15 +47,6 @@ static void mcpm_secondary_init(unsigned int cpu) #ifdef CONFIG_HOTPLUG_CPU -static int mcpm_cpu_kill(unsigned int cpu) -{ - unsigned int pcpu, pcluster; - - cpu_to_pcpu(cpu, &pcpu, &pcluster); - - return !mcpm_cpu_power_down_finish(pcpu, pcluster); -} - static int mcpm_cpu_disable(unsigned int cpu) { /* @@ -91,7 +73,6 @@ static struct smp_operations __initdata mcpm_smp_ops = { .smp_boot_secondary = mcpm_boot_secondary, .smp_secondary_init = mcpm_secondary_init, #ifdef CONFIG_HOTPLUG_CPU - .cpu_kill = mcpm_cpu_kill, .cpu_disable = mcpm_cpu_disable, .cpu_die = mcpm_cpu_die, #endif diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index ce922d0..e901d0f 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c @@ -175,7 +175,7 @@ static struct clock_event_device sp804_clockevent = { static struct irqaction sp804_timer_irq = { .name = "timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = sp804_timer_interrupt, .dev_id = &sp804_clockevent, }; diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c new file mode 100644 index 0000000..6cb362e --- /dev/null +++ b/arch/arm/common/via82c505.c @@ -0,0 +1,83 @@ +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/io.h> + + +#include <asm/mach/pci.h> + +#define MAX_SLOTS 7 + +#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) + +static int +via82c505_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + outl(CONFIG_CMD(bus,devfn,where),0xCF8); + switch (size) { + case 1: + *value=inb(0xCFC + (where&3)); + break; + case 2: + *value=inw(0xCFC + (where&2)); + break; + case 4: + *value=inl(0xCFC); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static int +via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + outl(CONFIG_CMD(bus,devfn,where),0xCF8); + switch (size) { + case 1: + outb(value, 0xCFC + (where&3)); + break; + case 2: + outw(value, 0xCFC + (where&2)); + break; + case 4: + outl(value, 0xCFC); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops via82c505_ops = { + .read = via82c505_read_config, + .write = via82c505_write_config, +}; + +void __init via82c505_preinit(void) +{ + printk(KERN_DEBUG "PCI: VIA 82c505\n"); + if (!request_region(0xA8,2,"via config")) { + printk(KERN_WARNING"VIA 82c505: Unable to request region 0xA8\n"); + return; + } + if (!request_region(0xCF8,8,"pci config")) { + printk(KERN_WARNING"VIA 82c505: Unable to request region 0xCF8\n"); + release_region(0xA8, 2); + return; + } + + /* Enable compatible Mode */ + outb(0x96,0xA8); + outb(0x18,0xA9); + outb(0x93,0xA8); + outb(0xd0,0xA9); + +} + +int __init via82c505_setup(int nr, struct pci_sys_data *sys) +{ + return (nr == 0); +} diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 287ac1d..6e49310 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -1,3 +1,4 @@ +CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y @@ -24,9 +25,10 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y CONFIG_ARCH_BCM=y -CONFIG_ARCH_BCM_MOBILE=y CONFIG_ARM_THUMBEE=y +CONFIG_ARM_ERRATA_743622=y CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set @@ -48,6 +50,7 @@ CONFIG_UNIX_DIAG=y CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y +CONFIG_ARPD=y CONFIG_SYN_COOKIES=y CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y @@ -92,6 +95,7 @@ CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_TEST=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_BCM_KONA=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -113,12 +117,12 @@ CONFIG_CONFIGFS_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y +CONFIG_DEBUG_INFO=y # CONFIG_FTRACE is not set CONFIG_CRC_CCITT=y CONFIG_CRC_T10DIF=y diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig index b38cd10..e7e9494 100644 --- a/arch/arm/configs/bockw_defconfig +++ b/arch/arm/configs/bockw_defconfig @@ -91,10 +91,6 @@ CONFIG_VIDEO_RCAR_VIN=y CONFIG_VIDEO_ML86V7667=y CONFIG_SPI=y CONFIG_SPI_SH_HSPI=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_RCAR=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_EHCI_HCD=y diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig index 6ac5ea7..806005a 100644 --- a/arch/arm/configs/ep93xx_defconfig +++ b/arch/arm/configs/ep93xx_defconfig @@ -1,14 +1,15 @@ +CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_EXPERT=y CONFIG_SLAB=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_EP93XX=y CONFIG_CRUNCH=y @@ -46,8 +47,11 @@ CONFIG_IPV6=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -63,14 +67,15 @@ CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y CONFIG_EP93XX_ETH=y CONFIG_USB_RTL8150=y # CONFIG_INPUT is not set # CONFIG_SERIO is not set # CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL010=y CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -81,9 +86,9 @@ CONFIG_WATCHDOG=y CONFIG_EP93XX_WATCHDOG=y CONFIG_USB=y CONFIG_USB_DEBUG=y +CONFIG_USB_DEVICEFS=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_CONSOLE=y @@ -95,18 +100,24 @@ CONFIG_RTC_DRV_EP93XX=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set +CONFIG_INOTIFY=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SLAB=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig index 0142ec3..317960f 100644 --- a/arch/arm/configs/h3600_defconfig +++ b/arch/arm/configs/h3600_defconfig @@ -1,6 +1,5 @@ +CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_MODULES=y @@ -12,11 +11,11 @@ CONFIG_ARCH_SA1100=y CONFIG_SA1100_H3600=y CONFIG_PCCARD=y CONFIG_PCMCIA_SA1100=y -CONFIG_PREEMPT=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 # CONFIG_CPU_FREQ_STAT is not set CONFIG_FPE_NWFPE=y +CONFIG_PM=y CONFIG_NET=y CONFIG_UNIX=y CONFIG_INET=y @@ -25,10 +24,13 @@ CONFIG_IRDA=m CONFIG_IRLAN=m CONFIG_IRNET=m CONFIG_IRCOMM=m +CONFIG_SA1100_FIR=m # CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y @@ -39,15 +41,19 @@ CONFIG_MTD_SA1100=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_MISC_DEVICES is not set CONFIG_IDE=y CONFIG_BLK_DEV_IDECS=y CONFIG_NETDEVICES=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_NET_PCMCIA=y CONFIG_PCMCIA_PCNET=y CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m CONFIG_PPP_ASYNC=m -# CONFIG_WLAN is not set +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set @@ -58,6 +64,8 @@ CONFIG_SERIAL_SA1100_CONSOLE=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_SA1100=y +# CONFIG_VGA_CONSOLE is not set +# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_MSDOS_FS=m @@ -66,4 +74,6 @@ CONFIG_JFFS2_FS=y CONFIG_CRAMFS=m CONFIG_NFS_FS=y CONFIG_NFSD=m +CONFIG_SMB_FS=m CONFIG_NLS=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 8d0c5a0..5d488c2 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -132,6 +132,7 @@ CONFIG_TOUCHSCREEN_MC13783=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MMA8450=y CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_SERIAL_IMX=y @@ -187,33 +188,22 @@ CONFIG_SND_SOC_PHYCORE_AC97=y CONFIG_SND_SOC_EUKREA_TLV320=y CONFIG_SND_SOC_IMX_WM8962=y CONFIG_SND_SOC_IMX_SGTL5000=y -CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_MC13783=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_MC13XXX=y @@ -256,6 +246,7 @@ CONFIG_UDF_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=m CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y CONFIG_NFS_FS=y @@ -270,7 +261,6 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set -CONFIG_PROVE_LOCKING=y # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_FTRACE is not set # CONFIG_ARM_UNWIND is not set diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig index 5bae195..a8314c3 100644 --- a/arch/arm/configs/integrator_defconfig +++ b/arch/arm/configs/integrator_defconfig @@ -1,17 +1,15 @@ +CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y +CONFIG_TINY_RCU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_ARCH_INTEGRATOR_CP=y -CONFIG_INTEGRATOR_IMPD1=y CONFIG_CPU_ARM720T=y CONFIG_CPU_ARM920T=y CONFIG_CPU_ARM922T=y @@ -20,9 +18,12 @@ CONFIG_CPU_ARM1020=y CONFIG_CPU_ARM1022=y CONFIG_CPU_ARM1026=y CONFIG_PCI=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y -# CONFIG_ATAGS is not set +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp" @@ -43,20 +44,24 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_AFS_PARTS=y +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_PHYSMAP=y -CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_NET_PCI=y CONFIG_E100=y CONFIG_SMC91X=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_SERIO_SERPORT is not set +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_ARMCLCD=y @@ -66,23 +71,19 @@ CONFIG_FB_MATROX_MYSTIQUE=y # CONFIG_VGA_CONSOLE is not set CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL030=y -CONFIG_COMMON_CLK_DEBUG=y CONFIG_EXT2_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_CRAMFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y CONFIG_NFSD_V3=y +CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_MAGIC_SYSRQ=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 9943e5d..1f36b82 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -123,9 +123,7 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_I2C=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y -CONFIG_I2C_DAVINCI=y CONFIG_SPI=y -CONFIG_SPI_DAVINCI=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig deleted file mode 100644 index 825c16d..0000000 --- a/arch/arm/configs/koelsch_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y -# CONFIG_BLOCK is not set -CONFIG_ARCH_SHMOBILE=y -CONFIG_ARCH_R8A7791=y -CONFIG_MACH_KOELSCH=y -# CONFIG_SWP_EMULATE is not set -CONFIG_CPU_BPREDICT_DISABLE=y -CONFIG_PL310_ERRATA_588369=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_NR_CPUS=8 -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_KEXEC=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_VFP=y -CONFIG_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM_RUNTIME=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=20 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HWMON is not set -CONFIG_THERMAL=y -CONFIG_RCAR_THERMAL=y -# CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -# CONFIG_IOMMU_SUPPORT is not set -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=y -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig index 35bff5e..e777ef2 100644 --- a/arch/arm/configs/lager_defconfig +++ b/arch/arm/configs/lager_defconfig @@ -89,8 +89,6 @@ CONFIG_THERMAL=y CONFIG_RCAR_THERMAL=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_DRM=y -CONFIG_DRM_RCAR_DU=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_SDHI=y diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index 5cc6360..000e920 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig @@ -92,8 +92,6 @@ CONFIG_SOC_CAMERA=y CONFIG_VIDEO_RCAR_VIN=y # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=y -CONFIG_DRM=y -CONFIG_DRM_RCAR_DU=y CONFIG_USB=y CONFIG_USB_RCAR_PHY=y CONFIG_MMC=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index c1df4e9..119fc37 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -6,7 +6,6 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_BCM=y -CONFIG_ARCH_BCM_MOBILE=y CONFIG_GPIO_PCA953X=y CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_KEYSTONE=y @@ -69,7 +68,6 @@ CONFIG_KS8851=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y CONFIG_MDIO_SUN4I=y -CONFIG_TI_CPSW=y CONFIG_KEYBOARD_SPEAR=y CONFIG_SERIO_AMBAKMI=y CONFIG_SERIAL_8250=y @@ -134,14 +132,12 @@ CONFIG_USB_GPIO_VBUS=y CONFIG_USB_ISP1301=y CONFIG_USB_MXS_PHY=y CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_TEGRA=y CONFIG_MMC_SDHCI_SPEAR=y -CONFIG_MMC_SDHCI_BCM_KONA=y CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y CONFIG_EDAC=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 6150108..4555c02 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -76,6 +76,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_TSC2007=m # CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_DEVPTS_MULTIPLE_INSTANCES=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set @@ -90,6 +91,7 @@ CONFIG_I2C_MXS=y CONFIG_SPI=y CONFIG_SPI_GPIO=m CONFIG_SPI_MXS=y +CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y @@ -113,12 +115,9 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y CONFIG_USB_MXS_PHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_MXS=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index bfa80a1..254cf05 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -1,13 +1,14 @@ +CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=y @@ -19,21 +20,22 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_MULTI_V6=y -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX_DEBUG=y +CONFIG_ARCH_OMAP2PLUS=y CONFIG_ARCH_OMAP2=y CONFIG_ARCH_OMAP3=y CONFIG_ARCH_OMAP4=y -CONFIG_SOC_OMAP5=y CONFIG_SOC_AM33XX=y -CONFIG_SOC_DRA7XX=y +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_MUX_DEBUG=y +CONFIG_ARCH_VEXPRESS_CA9X4=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_ERRATA_411920=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y CONFIG_NR_CPUS=2 -CONFIG_CMA=y +CONFIG_LEDS=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y @@ -59,6 +61,8 @@ CONFIG_IP_PNP_RARP=y # CONFIG_IPV6 is not set CONFIG_NETFILTER=y CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m CONFIG_BT=m @@ -73,13 +77,14 @@ CONFIG_MAC80211=m CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CMA=y CONFIG_DMA_CMA=y -CONFIG_OMAP_OCP2SCP=y CONFIG_CONNECTOR=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_OOPS=y CONFIG_MTD_CFI=y @@ -93,40 +98,32 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_SENSORS_LIS3LV02D=m CONFIG_SENSORS_TSL2550=m -CONFIG_BMP085_I2C=m CONFIG_SENSORS_LIS3_I2C=m +CONFIG_BMP085_I2C=m CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_MD=y CONFIG_NETDEVICES=y -CONFIG_KS8851=y -CONFIG_KS8851_MLL=y +CONFIG_SMSC_PHY=y +CONFIG_NET_ETHERNET=y CONFIG_SMC91X=y CONFIG_SMSC911X=y -CONFIG_TI_CPSW=y -CONFIG_AT803X_PHY=y -CONFIG_SMSC_PHY=y +CONFIG_KS8851=y +CONFIG_KS8851_MLL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_DEBUG=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_EPSON2888=y CONFIG_USB_KC2190=y -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_LIBERTAS_DEBUG=y -CONFIG_WL_TI=y -CONFIG_WL12XX=m -CONFIG_WL18XX=m -CONFIG_WLCORE_SPI=m -CONFIG_WLCORE_SDIO=m -CONFIG_MWIFIEX=m -CONFIG_MWIFIEX_SDIO=m -CONFIG_MWIFIEX_USB=m CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y @@ -136,6 +133,7 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=y CONFIG_INPUT_MISC=y CONFIG_INPUT_TWL4030_PWRBUTTON=y +CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y @@ -145,7 +143,8 @@ CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_OMAP=y CONFIG_SERIAL_OMAP_CONSOLE=y CONFIG_HW_RANDOM=y @@ -159,32 +158,31 @@ CONFIG_GPIO_TWL4030=y CONFIG_W1=y CONFIG_POWER_SUPPLY=y CONFIG_SENSORS_LM75=m +CONFIG_WATCHDOG=y CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_TI_SOC_THERMAL=y -CONFIG_OMAP4_THERMAL=y -CONFIG_OMAP5_THERMAL=y -CONFIG_DRA752_THERMAL=y -CONFIG_WATCHDOG=y +CONFIG_CPU_THERMAL=y CONFIG_OMAP_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y -CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65910=y CONFIG_TWL6040_CORE=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65910=y -CONFIG_REGULATOR_TWL4030=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y +CONFIG_FB_OMAP_LCD_VGA=y CONFIG_OMAP2_DSS=m +CONFIG_OMAP2_DSS_RFBI=y CONFIG_OMAP2_DSS_SDI=y CONFIG_OMAP2_DSS_DSI=y CONFIG_FB_OMAP2=m @@ -196,8 +194,12 @@ CONFIG_DISPLAY_PANEL_DPI=m CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y +CONFIG_DISPLAY_SUPPORT=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y CONFIG_LOGO=y CONFIG_SOUND=m CONFIG_SND=m @@ -214,14 +216,14 @@ CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y CONFIG_USB_MON=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y -CONFIG_USB_DWC3=m +CONFIG_USB_LIBUSUAL=y CONFIG_USB_TEST=y +CONFIG_USB_PHY=y CONFIG_NOP_USB_XCEIV=y -CONFIG_OMAP_USB2=y -CONFIG_OMAP_USB3=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_DEBUG_FILES=y @@ -230,6 +232,7 @@ CONFIG_USB_ZERO=m CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y CONFIG_SDIO_UART=y +CONFIG_MMC_ARMMMCI=y CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y CONFIG_NEW_LEDS=y @@ -249,8 +252,11 @@ CONFIG_RTC_DRV_OMAP=y CONFIG_DMADEVICES=y CONFIG_TI_EDMA=y CONFIG_DMA_OMAP=y -CONFIG_EXTCON=y -CONFIG_EXTCON_PALMAS=y +CONFIG_TI_SOC_THERMAL=y +CONFIG_TI_THERMAL=y +CONFIG_OMAP4_THERMAL=y +CONFIG_OMAP5_THERMAL=y +CONFIG_DRA752_THERMAL=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set @@ -269,18 +275,23 @@ CONFIG_JFFS2_RUBIN=y CONFIG_UBIFS_FS=y CONFIG_CRAMFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y # CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SECURITY=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_ANSI_CPRNG is not set @@ -289,6 +300,9 @@ CONFIG_CRC_T10DIF=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_LIBCRC32C=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y +CONFIG_SOC_OMAP5=y +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_DAVINCI_CPDMA=y +CONFIG_TI_CPSW=y +CONFIG_AT803X_PHY=y +CONFIG_SOC_DRA7XX=y diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig index 23591db..002a1ce 100644 --- a/arch/arm/configs/prima2_defconfig +++ b/arch/arm/configs/prima2_defconfig @@ -39,7 +39,6 @@ CONFIG_SPI=y CONFIG_SPI_SIRF=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y CONFIG_USB_GADGET=y CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig new file mode 100644 index 0000000..e319b2c --- /dev/null +++ b/arch/arm/configs/shark_defconfig @@ -0,0 +1,80 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_SHARK=y +CONFIG_LEDS=y +CONFIG_LEDS_TIMER=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_FPE_NWFPE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_IDE=y +CONFIG_BLK_DEV_IDECD=m +CONFIG_SCSI=m +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_NET_PCI=y +CONFIG_CS89x0=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_PRINTER=m +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FB_CYBER2000=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=m +CONFIG_SOUND_PRIME=m +CONFIG_SOUND_OSS=m +CONFIG_SOUND_SB=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_CMOS=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFSD=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_ISO8859_1=m +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig deleted file mode 100644 index 3e2259b..0000000 --- a/arch/arm/configs/sunxi_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_SUNXI=y -CONFIG_SMP=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_NETDEVICES=y -CONFIG_SUN4I_EMAC=y -# CONFIG_NET_CADENCE is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_WLAN is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=8 -CONFIG_SERIAL_8250_RUNTIME_UARTS=8 -CONFIG_SERIAL_8250_DW=y -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_SUNXI_WATCHDOG=y -# CONFIG_USB_SUPPORT is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_COMMON_CLK_DEBUG=y -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS=y -CONFIG_PRINTK_TIME=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 4934295..ea042e8 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -27,7 +27,6 @@ CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y -CONFIG_ARCH_TEGRA_124_SOC=y CONFIG_TEGRA_EMC_SCALING_ENABLE=y CONFIG_PCI=y CONFIG_PCI_MSI=y @@ -42,11 +41,9 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_KEXEC=y CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_IDLE=y CONFIG_VFP=y -CONFIG_NEON=y CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_PACKET=y @@ -132,7 +129,6 @@ CONFIG_SPI=y CONFIG_SPI_TEGRA114=y CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y -CONFIG_PINCTRL_PALMAS=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TPS6586X=y @@ -227,7 +223,6 @@ CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y CONFIG_NVEC_PAZ00=y -CONFIG_COMMON_CLK_DEBUG=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_MEMORY=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index c6ebc18..a0025dc 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -1,3 +1,4 @@ +CONFIG_HIGHMEM=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_NO_HZ=y @@ -15,14 +16,10 @@ CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_IDLE=y -CONFIG_ARM_U8500_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_PM_RUNTIME=y @@ -71,8 +68,8 @@ CONFIG_CPU_THERMAL=y CONFIG_WATCHDOG=y CONFIG_MFD_STMPE=y CONFIG_MFD_TC3589X=y -CONFIG_REGULATOR_AB8500=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_AB8500=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y @@ -81,8 +78,10 @@ CONFIG_SND_SOC_UX500_MACH_MOP500=y CONFIG_USB=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_UX500=y +CONFIG_USB_PHY=y CONFIG_AB8500_USB=y CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MUSB_HDRC=y CONFIG_USB_ETH=m CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y @@ -110,8 +109,6 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_MISC_FILESYSTEMS is not set @@ -119,12 +116,12 @@ CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y CONFIG_CRYPTO_DEV_UX500=y diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index f489fda..f2de51f 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -1,3 +1,4 @@ +CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y @@ -7,9 +8,11 @@ CONFIG_CGROUPS=y CONFIG_CPUSETS=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set # CONFIG_PID_NS is not set # CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_PROFILING=y CONFIG_OPROFILE=y CONFIG_MODULES=y @@ -20,22 +23,14 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_VEXPRESS_CA9X4=y -CONFIG_ARCH_VEXPRESS_DCSCB=y -CONFIG_ARCH_VEXPRESS_TC2_PM=y # CONFIG_SWP_EMULATE is not set CONFIG_SMP=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_MCPM=y CONFIG_VMSPLIT_2G=y -CONFIG_NR_CPUS=8 -CONFIG_ARM_PSCI=y +CONFIG_HOTPLUG_CPU=y CONFIG_AEABI=y -CONFIG_CMA=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyAMA0" -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M" CONFIG_VFP=y CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -49,46 +44,37 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set # CONFIG_WIRELESS is not set -CONFIG_NET_9P=y -CONFIG_NET_9P_VIRTIO=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_MTD_PLATRAM=y -CONFIG_MTD_UBI=y -CONFIG_PROC_DEVICETREE=y -CONFIG_VIRTIO_BLK=y +CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MISC_DEVICES=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_VIRTIO=y +# CONFIG_SCSI_LOWLEVEL is not set CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_NETDEVICES=y -CONFIG_VIRTIO_NET=y -CONFIG_SMC91X=y +CONFIG_NET_ETHERNET=y CONFIG_SMSC911X=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set CONFIG_INPUT_EVDEV=y # CONFIG_SERIO_SERPORT is not set CONFIG_SERIO_AMBAKMI=y -CONFIG_LEGACY_PTY_COUNT=16 CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_I2C=y -CONFIG_I2C_VERSATILE=y -CONFIG_SENSORS_VEXPRESS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_VEXPRESS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -117,45 +103,38 @@ CONFIG_HID_THRUSTMASTER=y CONFIG_HID_ZEROPLUS=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_MON=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL031=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_MMIO=y -CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y -CONFIG_UBIFS_FS=y CONFIG_CRAMFS=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_LZO=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y -CONFIG_9P_FS=y +# CONFIG_RPCSEC_GSS_KRB5 is not set CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y # CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/vt8500_v6_v7_defconfig b/arch/arm/configs/vt8500_v6_v7_defconfig deleted file mode 100644 index f052017..0000000 --- a/arch/arm/configs/vt8500_v6_v7_defconfig +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_IRQ_DOMAIN_DEBUG=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_WM8750=y -CONFIG_ARCH_WM8850=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_PROC_DEVICETREE=y -CONFIG_EEPROM_93CX6=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -# CONFIG_NET_CADENCE is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -CONFIG_VIA_VELOCITY=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_PHYLIB=y -CONFIG_INPUT_MATRIXKMAP=y -CONFIG_SERIAL_VT8500=y -CONFIG_SERIAL_VT8500_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_WMT=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_PINCTRL_WM8750=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_RESET=y -CONFIG_MFD_SYSCON=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_ULPI=y -CONFIG_MMC=y -CONFIG_MMC_DEBUG=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_VT8500=y -CONFIG_DMADEVICES=y -CONFIG_COMMON_CLK_DEBUG=y -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_PWM=y -CONFIG_PWM_VT8500=y -CONFIG_RESET_CONTROLLER=y -CONFIG_GENERIC_PHY=y -CONFIG_EXT4_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_KERNEL=y -CONFIG_LOCKUP_DETECTOR=y diff --git a/arch/arm/crypto/.gitignore b/arch/arm/crypto/.gitignore deleted file mode 100644 index 6231d36..0000000 --- a/arch/arm/crypto/.gitignore +++ /dev/null @@ -1 +0,0 @@ -aesbs-core.S diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile index 81cda39..a2c8385 100644 --- a/arch/arm/crypto/Makefile +++ b/arch/arm/crypto/Makefile @@ -3,17 +3,7 @@ # obj-$(CONFIG_CRYPTO_AES_ARM) += aes-arm.o -obj-$(CONFIG_CRYPTO_AES_ARM_BS) += aes-arm-bs.o obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o -aes-arm-y := aes-armv4.o aes_glue.o -aes-arm-bs-y := aesbs-core.o aesbs-glue.o -sha1-arm-y := sha1-armv4-large.o sha1_glue.o - -quiet_cmd_perl = PERL $@ - cmd_perl = $(PERL) $(<) > $(@) - -$(src)/aesbs-core.S_shipped: $(src)/bsaes-armv7.pl - $(call cmd,perl) - -.PRECIOUS: $(obj)/aesbs-core.S +aes-arm-y := aes-armv4.o aes_glue.o +sha1-arm-y := sha1-armv4-large.o sha1_glue.o diff --git a/arch/arm/crypto/aes_glue.c b/arch/arm/crypto/aes_glue.c index 3003fa1..59f7877 100644 --- a/arch/arm/crypto/aes_glue.c +++ b/arch/arm/crypto/aes_glue.c @@ -6,12 +6,22 @@ #include <linux/crypto.h> #include <crypto/aes.h> -#include "aes_glue.h" +#define AES_MAXNR 14 -EXPORT_SYMBOL(AES_encrypt); -EXPORT_SYMBOL(AES_decrypt); -EXPORT_SYMBOL(private_AES_set_encrypt_key); -EXPORT_SYMBOL(private_AES_set_decrypt_key); +typedef struct { + unsigned int rd_key[4 *(AES_MAXNR + 1)]; + int rounds; +} AES_KEY; + +struct AES_CTX { + AES_KEY enc_key; + AES_KEY dec_key; +}; + +asmlinkage void AES_encrypt(const u8 *in, u8 *out, AES_KEY *ctx); +asmlinkage void AES_decrypt(const u8 *in, u8 *out, AES_KEY *ctx); +asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key); +asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, const int bits, AES_KEY *key); static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src) { @@ -71,7 +81,7 @@ static struct crypto_alg aes_alg = { .cipher = { .cia_min_keysize = AES_MIN_KEY_SIZE, .cia_max_keysize = AES_MAX_KEY_SIZE, - .cia_setkey = aes_set_key, + .cia_setkey = aes_set_key, .cia_encrypt = aes_encrypt, .cia_decrypt = aes_decrypt } diff --git a/arch/arm/crypto/aes_glue.h b/arch/arm/crypto/aes_glue.h deleted file mode 100644 index cca3e51..0000000 --- a/arch/arm/crypto/aes_glue.h +++ /dev/null @@ -1,19 +0,0 @@ - -#define AES_MAXNR 14 - -struct AES_KEY { - unsigned int rd_key[4 * (AES_MAXNR + 1)]; - int rounds; -}; - -struct AES_CTX { - struct AES_KEY enc_key; - struct AES_KEY dec_key; -}; - -asmlinkage void AES_encrypt(const u8 *in, u8 *out, struct AES_KEY *ctx); -asmlinkage void AES_decrypt(const u8 *in, u8 *out, struct AES_KEY *ctx); -asmlinkage int private_AES_set_decrypt_key(const unsigned char *userKey, - const int bits, struct AES_KEY *key); -asmlinkage int private_AES_set_encrypt_key(const unsigned char *userKey, - const int bits, struct AES_KEY *key); diff --git a/arch/arm/crypto/aesbs-core.S_shipped b/arch/arm/crypto/aesbs-core.S_shipped deleted file mode 100644 index 64205d4..0000000 --- a/arch/arm/crypto/aesbs-core.S_shipped +++ /dev/null @@ -1,2544 +0,0 @@ - -@ ==================================================================== -@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL -@ project. The module is, however, dual licensed under OpenSSL and -@ CRYPTOGAMS licenses depending on where you obtain it. For further -@ details see http://www.openssl.org/~appro/cryptogams/. -@ -@ Specific modes and adaptation for Linux kernel by Ard Biesheuvel -@ <ard.biesheuvel@linaro.org>. Permission to use under GPL terms is -@ granted. -@ ==================================================================== - -@ Bit-sliced AES for ARM NEON -@ -@ February 2012. -@ -@ This implementation is direct adaptation of bsaes-x86_64 module for -@ ARM NEON. Except that this module is endian-neutral [in sense that -@ it can be compiled for either endianness] by courtesy of vld1.8's -@ neutrality. Initial version doesn't implement interface to OpenSSL, -@ only low-level primitives and unsupported entry points, just enough -@ to collect performance results, which for Cortex-A8 core are: -@ -@ encrypt 19.5 cycles per byte processed with 128-bit key -@ decrypt 22.1 cycles per byte processed with 128-bit key -@ key conv. 440 cycles per 128-bit key/0.18 of 8x block -@ -@ Snapdragon S4 encrypts byte in 17.6 cycles and decrypts in 19.7, -@ which is [much] worse than anticipated (for further details see -@ http://www.openssl.org/~appro/Snapdragon-S4.html). -@ -@ Cortex-A15 manages in 14.2/16.1 cycles [when integer-only code -@ manages in 20.0 cycles]. -@ -@ When comparing to x86_64 results keep in mind that NEON unit is -@ [mostly] single-issue and thus can't [fully] benefit from -@ instruction-level parallelism. And when comparing to aes-armv4 -@ results keep in mind key schedule conversion overhead (see -@ bsaes-x86_64.pl for further details)... -@ -@ <appro@openssl.org> - -@ April-August 2013 -@ -@ Add CBC, CTR and XTS subroutines, adapt for kernel use. -@ -@ <ard.biesheuvel@linaro.org> - -#ifndef __KERNEL__ -# include "arm_arch.h" - -# define VFP_ABI_PUSH vstmdb sp!,{d8-d15} -# define VFP_ABI_POP vldmia sp!,{d8-d15} -# define VFP_ABI_FRAME 0x40 -#else -# define VFP_ABI_PUSH -# define VFP_ABI_POP -# define VFP_ABI_FRAME 0 -# define BSAES_ASM_EXTENDED_KEY -# define XTS_CHAIN_TWEAK -# define __ARM_ARCH__ __LINUX_ARM_ARCH__ -#endif - -#ifdef __thumb__ -# define adrl adr -#endif - -#if __ARM_ARCH__>=7 -.text -.syntax unified @ ARMv7-capable assembler is expected to handle this -#ifdef __thumb2__ -.thumb -#else -.code 32 -#endif - -.fpu neon - -.type _bsaes_decrypt8,%function -.align 4 -_bsaes_decrypt8: - adr r6,_bsaes_decrypt8 - vldmia r4!, {q9} @ round 0 key - add r6,r6,#.LM0ISR-_bsaes_decrypt8 - - vldmia r6!, {q8} @ .LM0ISR - veor q10, q0, q9 @ xor with round0 key - veor q11, q1, q9 - vtbl.8 d0, {q10}, d16 - vtbl.8 d1, {q10}, d17 - veor q12, q2, q9 - vtbl.8 d2, {q11}, d16 - vtbl.8 d3, {q11}, d17 - veor q13, q3, q9 - vtbl.8 d4, {q12}, d16 - vtbl.8 d5, {q12}, d17 - veor q14, q4, q9 - vtbl.8 d6, {q13}, d16 - vtbl.8 d7, {q13}, d17 - veor q15, q5, q9 - vtbl.8 d8, {q14}, d16 - vtbl.8 d9, {q14}, d17 - veor q10, q6, q9 - vtbl.8 d10, {q15}, d16 - vtbl.8 d11, {q15}, d17 - veor q11, q7, q9 - vtbl.8 d12, {q10}, d16 - vtbl.8 d13, {q10}, d17 - vtbl.8 d14, {q11}, d16 - vtbl.8 d15, {q11}, d17 - vmov.i8 q8,#0x55 @ compose .LBS0 - vmov.i8 q9,#0x33 @ compose .LBS1 - vshr.u64 q10, q6, #1 - vshr.u64 q11, q4, #1 - veor q10, q10, q7 - veor q11, q11, q5 - vand q10, q10, q8 - vand q11, q11, q8 - veor q7, q7, q10 - vshl.u64 q10, q10, #1 - veor q5, q5, q11 - vshl.u64 q11, q11, #1 - veor q6, q6, q10 - veor q4, q4, q11 - vshr.u64 q10, q2, #1 - vshr.u64 q11, q0, #1 - veor q10, q10, q3 - veor q11, q11, q1 - vand q10, q10, q8 - vand q11, q11, q8 - veor q3, q3, q10 - vshl.u64 q10, q10, #1 - veor q1, q1, q11 - vshl.u64 q11, q11, #1 - veor q2, q2, q10 - veor q0, q0, q11 - vmov.i8 q8,#0x0f @ compose .LBS2 - vshr.u64 q10, q5, #2 - vshr.u64 q11, q4, #2 - veor q10, q10, q7 - veor q11, q11, q6 - vand q10, q10, q9 - vand q11, q11, q9 - veor q7, q7, q10 - vshl.u64 q10, q10, #2 - veor q6, q6, q11 - vshl.u64 q11, q11, #2 - veor q5, q5, q10 - veor q4, q4, q11 - vshr.u64 q10, q1, #2 - vshr.u64 q11, q0, #2 - veor q10, q10, q3 - veor q11, q11, q2 - vand q10, q10, q9 - vand q11, q11, q9 - veor q3, q3, q10 - vshl.u64 q10, q10, #2 - veor q2, q2, q11 - vshl.u64 q11, q11, #2 - veor q1, q1, q10 - veor q0, q0, q11 - vshr.u64 q10, q3, #4 - vshr.u64 q11, q2, #4 - veor q10, q10, q7 - veor q11, q11, q6 - vand q10, q10, q8 - vand q11, q11, q8 - veor q7, q7, q10 - vshl.u64 q10, q10, #4 - veor q6, q6, q11 - vshl.u64 q11, q11, #4 - veor q3, q3, q10 - veor q2, q2, q11 - vshr.u64 q10, q1, #4 - vshr.u64 q11, q0, #4 - veor q10, q10, q5 - veor q11, q11, q4 - vand q10, q10, q8 - vand q11, q11, q8 - veor q5, q5, q10 - vshl.u64 q10, q10, #4 - veor q4, q4, q11 - vshl.u64 q11, q11, #4 - veor q1, q1, q10 - veor q0, q0, q11 - sub r5,r5,#1 - b .Ldec_sbox -.align 4 -.Ldec_loop: - vldmia r4!, {q8-q11} - veor q8, q8, q0 - veor q9, q9, q1 - vtbl.8 d0, {q8}, d24 - vtbl.8 d1, {q8}, d25 - vldmia r4!, {q8} - veor q10, q10, q2 - vtbl.8 d2, {q9}, d24 - vtbl.8 d3, {q9}, d25 - vldmia r4!, {q9} - veor q11, q11, q3 - vtbl.8 d4, {q10}, d24 - vtbl.8 d5, {q10}, d25 - vldmia r4!, {q10} - vtbl.8 d6, {q11}, d24 - vtbl.8 d7, {q11}, d25 - vldmia r4!, {q11} - veor q8, q8, q4 - veor q9, q9, q5 - vtbl.8 d8, {q8}, d24 - vtbl.8 d9, {q8}, d25 - veor q10, q10, q6 - vtbl.8 d10, {q9}, d24 - vtbl.8 d11, {q9}, d25 - veor q11, q11, q7 - vtbl.8 d12, {q10}, d24 - vtbl.8 d13, {q10}, d25 - vtbl.8 d14, {q11}, d24 - vtbl.8 d15, {q11}, d25 -.Ldec_sbox: - veor q1, q1, q4 - veor q3, q3, q4 - - veor q4, q4, q7 - veor q1, q1, q6 - veor q2, q2, q7 - veor q6, q6, q4 - - veor q0, q0, q1 - veor q2, q2, q5 - veor q7, q7, q6 - veor q3, q3, q0 - veor q5, q5, q0 - veor q1, q1, q3 - veor q11, q3, q0 - veor q10, q7, q4 - veor q9, q1, q6 - veor q13, q4, q0 - vmov q8, q10 - veor q12, q5, q2 - - vorr q10, q10, q9 - veor q15, q11, q8 - vand q14, q11, q12 - vorr q11, q11, q12 - veor q12, q12, q9 - vand q8, q8, q9 - veor q9, q6, q2 - vand q15, q15, q12 - vand q13, q13, q9 - veor q9, q3, q7 - veor q12, q1, q5 - veor q11, q11, q13 - veor q10, q10, q13 - vand q13, q9, q12 - vorr q9, q9, q12 - veor q11, q11, q15 - veor q8, q8, q13 - veor q10, q10, q14 - veor q9, q9, q15 - veor q8, q8, q14 - vand q12, q4, q6 - veor q9, q9, q14 - vand q13, q0, q2 - vand q14, q7, q1 - vorr q15, q3, q5 - veor q11, q11, q12 - veor q9, q9, q14 - veor q8, q8, q15 - veor q10, q10, q13 - - @ Inv_GF16 0, 1, 2, 3, s0, s1, s2, s3 - - @ new smaller inversion - - vand q14, q11, q9 - vmov q12, q8 - - veor q13, q10, q14 - veor q15, q8, q14 - veor q14, q8, q14 @ q14=q15 - - vbsl q13, q9, q8 - vbsl q15, q11, q10 - veor q11, q11, q10 - - vbsl q12, q13, q14 - vbsl q8, q14, q13 - - vand q14, q12, q15 - veor q9, q9, q8 - - veor q14, q14, q11 - veor q12, q5, q2 - veor q8, q1, q6 - veor q10, q15, q14 - vand q10, q10, q5 - veor q5, q5, q1 - vand q11, q1, q15 - vand q5, q5, q14 - veor q1, q11, q10 - veor q5, q5, q11 - veor q15, q15, q13 - veor q14, q14, q9 - veor q11, q15, q14 - veor q10, q13, q9 - vand q11, q11, q12 - vand q10, q10, q2 - veor q12, q12, q8 - veor q2, q2, q6 - vand q8, q8, q15 - vand q6, q6, q13 - vand q12, q12, q14 - vand q2, q2, q9 - veor q8, q8, q12 - veor q2, q2, q6 - veor q12, q12, q11 - veor q6, q6, q10 - veor q5, q5, q12 - veor q2, q2, q12 - veor q1, q1, q8 - veor q6, q6, q8 - - veor q12, q3, q0 - veor q8, q7, q4 - veor q11, q15, q14 - veor q10, q13, q9 - vand q11, q11, q12 - vand q10, q10, q0 - veor q12, q12, q8 - veor q0, q0, q4 - vand q8, q8, q15 - vand q4, q4, q13 - vand q12, q12, q14 - vand q0, q0, q9 - veor q8, q8, q12 - veor q0, q0, q4 - veor q12, q12, q11 - veor q4, q4, q10 - veor q15, q15, q13 - veor q14, q14, q9 - veor q10, q15, q14 - vand q10, q10, q3 - veor q3, q3, q7 - vand q11, q7, q15 - vand q3, q3, q14 - veor q7, q11, q10 - veor q3, q3, q11 - veor q3, q3, q12 - veor q0, q0, q12 - veor q7, q7, q8 - veor q4, q4, q8 - veor q1, q1, q7 - veor q6, q6, q5 - - veor q4, q4, q1 - veor q2, q2, q7 - veor q5, q5, q7 - veor q4, q4, q2 - veor q7, q7, q0 - veor q4, q4, q5 - veor q3, q3, q6 - veor q6, q6, q1 - veor q3, q3, q4 - - veor q4, q4, q0 - veor q7, q7, q3 - subs r5,r5,#1 - bcc .Ldec_done - @ multiplication by 0x05-0x00-0x04-0x00 - vext.8 q8, q0, q0, #8 - vext.8 q14, q3, q3, #8 - vext.8 q15, q5, q5, #8 - veor q8, q8, q0 - vext.8 q9, q1, q1, #8 - veor q14, q14, q3 - vext.8 q10, q6, q6, #8 - veor q15, q15, q5 - vext.8 q11, q4, q4, #8 - veor q9, q9, q1 - vext.8 q12, q2, q2, #8 - veor q10, q10, q6 - vext.8 q13, q7, q7, #8 - veor q11, q11, q4 - veor q12, q12, q2 - veor q13, q13, q7 - - veor q0, q0, q14 - veor q1, q1, q14 - veor q6, q6, q8 - veor q2, q2, q10 - veor q4, q4, q9 - veor q1, q1, q15 - veor q6, q6, q15 - veor q2, q2, q14 - veor q7, q7, q11 - veor q4, q4, q14 - veor q3, q3, q12 - veor q2, q2, q15 - veor q7, q7, q15 - veor q5, q5, q13 - vext.8 q8, q0, q0, #12 @ x0 <<< 32 - vext.8 q9, q1, q1, #12 - veor q0, q0, q8 @ x0 ^ (x0 <<< 32) - vext.8 q10, q6, q6, #12 - veor q1, q1, q9 - vext.8 q11, q4, q4, #12 - veor q6, q6, q10 - vext.8 q12, q2, q2, #12 - veor q4, q4, q11 - vext.8 q13, q7, q7, #12 - veor q2, q2, q12 - vext.8 q14, q3, q3, #12 - veor q7, q7, q13 - vext.8 q15, q5, q5, #12 - veor q3, q3, q14 - - veor q9, q9, q0 - veor q5, q5, q15 - vext.8 q0, q0, q0, #8 @ (x0 ^ (x0 <<< 32)) <<< 64) - veor q10, q10, q1 - veor q8, q8, q5 - veor q9, q9, q5 - vext.8 q1, q1, q1, #8 - veor q13, q13, q2 - veor q0, q0, q8 - veor q14, q14, q7 - veor q1, q1, q9 - vext.8 q8, q2, q2, #8 - veor q12, q12, q4 - vext.8 q9, q7, q7, #8 - veor q15, q15, q3 - vext.8 q2, q4, q4, #8 - veor q11, q11, q6 - vext.8 q7, q5, q5, #8 - veor q12, q12, q5 - vext.8 q4, q3, q3, #8 - veor q11, q11, q5 - vext.8 q3, q6, q6, #8 - veor q5, q9, q13 - veor q11, q11, q2 - veor q7, q7, q15 - veor q6, q4, q14 - veor q4, q8, q12 - veor q2, q3, q10 - vmov q3, q11 - @ vmov q5, q9 - vldmia r6, {q12} @ .LISR - ite eq @ Thumb2 thing, sanity check in ARM - addeq r6,r6,#0x10 - bne .Ldec_loop - vldmia r6, {q12} @ .LISRM0 - b .Ldec_loop -.align 4 -.Ldec_done: - vmov.i8 q8,#0x55 @ compose .LBS0 - vmov.i8 q9,#0x33 @ compose .LBS1 - vshr.u64 q10, q3, #1 - vshr.u64 q11, q2, #1 - veor q10, q10, q5 - veor q11, q11, q7 - vand q10, q10, q8 - vand q11, q11, q8 - veor q5, q5, q10 - vshl.u64 q10, q10, #1 - veor q7, q7, q11 - vshl.u64 q11, q11, #1 - veor q3, q3, q10 - veor q2, q2, q11 - vshr.u64 q10, q6, #1 - vshr.u64 q11, q0, #1 - veor q10, q10, q4 - veor q11, q11, q1 - vand q10, q10, q8 - vand q11, q11, q8 - veor q4, q4, q10 - vshl.u64 q10, q10, #1 - veor q1, q1, q11 - vshl.u64 q11, q11, #1 - veor q6, q6, q10 - veor q0, q0, q11 - vmov.i8 q8,#0x0f @ compose .LBS2 - vshr.u64 q10, q7, #2 - vshr.u64 q11, q2, #2 - veor q10, q10, q5 - veor q11, q11, q3 - vand q10, q10, q9 - vand q11, q11, q9 - veor q5, q5, q10 - vshl.u64 q10, q10, #2 - veor q3, q3, q11 - vshl.u64 q11, q11, #2 - veor q7, q7, q10 - veor q2, q2, q11 - vshr.u64 q10, q1, #2 - vshr.u64 q11, q0, #2 - veor q10, q10, q4 - veor q11, q11, q6 - vand q10, q10, q9 - vand q11, q11, q9 - veor q4, q4, q10 - vshl.u64 q10, q10, #2 - veor q6, q6, q11 - vshl.u64 q11, q11, #2 - veor q1, q1, q10 - veor q0, q0, q11 - vshr.u64 q10, q4, #4 - vshr.u64 q11, q6, #4 - veor q10, q10, q5 - veor q11, q11, q3 - vand q10, q10, q8 - vand q11, q11, q8 - veor q5, q5, q10 - vshl.u64 q10, q10, #4 - veor q3, q3, q11 - vshl.u64 q11, q11, #4 - veor q4, q4, q10 - veor q6, q6, q11 - vshr.u64 q10, q1, #4 - vshr.u64 q11, q0, #4 - veor q10, q10, q7 - veor q11, q11, q2 - vand q10, q10, q8 - vand q11, q11, q8 - veor q7, q7, q10 - vshl.u64 q10, q10, #4 - veor q2, q2, q11 - vshl.u64 q11, q11, #4 - veor q1, q1, q10 - veor q0, q0, q11 - vldmia r4, {q8} @ last round key - veor q6, q6, q8 - veor q4, q4, q8 - veor q2, q2, q8 - veor q7, q7, q8 - veor q3, q3, q8 - veor q5, q5, q8 - veor q0, q0, q8 - veor q1, q1, q8 - bx lr -.size _bsaes_decrypt8,.-_bsaes_decrypt8 - -.type _bsaes_const,%object -.align 6 -_bsaes_const: -.LM0ISR: @ InvShiftRows constants - .quad 0x0a0e0206070b0f03, 0x0004080c0d010509 -.LISR: - .quad 0x0504070602010003, 0x0f0e0d0c080b0a09 -.LISRM0: - .quad 0x01040b0e0205080f, 0x0306090c00070a0d -.LM0SR: @ ShiftRows constants - .quad 0x0a0e02060f03070b, 0x0004080c05090d01 -.LSR: - .quad 0x0504070600030201, 0x0f0e0d0c0a09080b -.LSRM0: - .quad 0x0304090e00050a0f, 0x01060b0c0207080d -.LM0: - .quad 0x02060a0e03070b0f, 0x0004080c0105090d -.LREVM0SR: - .quad 0x090d01050c000408, 0x03070b0f060a0e02 -.asciz "Bit-sliced AES for NEON, CRYPTOGAMS by <appro@openssl.org>" -.align 6 -.size _bsaes_const,.-_bsaes_const - -.type _bsaes_encrypt8,%function -.align 4 -_bsaes_encrypt8: - adr r6,_bsaes_encrypt8 - vldmia r4!, {q9} @ round 0 key - sub r6,r6,#_bsaes_encrypt8-.LM0SR - - vldmia r6!, {q8} @ .LM0SR -_bsaes_encrypt8_alt: - veor q10, q0, q9 @ xor with round0 key - veor q11, q1, q9 - vtbl.8 d0, {q10}, d16 - vtbl.8 d1, {q10}, d17 - veor q12, q2, q9 - vtbl.8 d2, {q11}, d16 - vtbl.8 d3, {q11}, d17 - veor q13, q3, q9 - vtbl.8 d4, {q12}, d16 - vtbl.8 d5, {q12}, d17 - veor q14, q4, q9 - vtbl.8 d6, {q13}, d16 - vtbl.8 d7, {q13}, d17 - veor q15, q5, q9 - vtbl.8 d8, {q14}, d16 - vtbl.8 d9, {q14}, d17 - veor q10, q6, q9 - vtbl.8 d10, {q15}, d16 - vtbl.8 d11, {q15}, d17 - veor q11, q7, q9 - vtbl.8 d12, {q10}, d16 - vtbl.8 d13, {q10}, d17 - vtbl.8 d14, {q11}, d16 - vtbl.8 d15, {q11}, d17 -_bsaes_encrypt8_bitslice: - vmov.i8 q8,#0x55 @ compose .LBS0 - vmov.i8 q9,#0x33 @ compose .LBS1 - vshr.u64 q10, q6, #1 - vshr.u64 q11, q4, #1 - veor q10, q10, q7 - veor q11, q11, q5 - vand q10, q10, q8 - vand q11, q11, q8 - veor q7, q7, q10 - vshl.u64 q10, q10, #1 - veor q5, q5, q11 - vshl.u64 q11, q11, #1 - veor q6, q6, q10 - veor q4, q4, q11 - vshr.u64 q10, q2, #1 - vshr.u64 q11, q0, #1 - veor q10, q10, q3 - veor q11, q11, q1 - vand q10, q10, q8 - vand q11, q11, q8 - veor q3, q3, q10 - vshl.u64 q10, q10, #1 - veor q1, q1, q11 - vshl.u64 q11, q11, #1 - veor q2, q2, q10 - veor q0, q0, q11 - vmov.i8 q8,#0x0f @ compose .LBS2 - vshr.u64 q10, q5, #2 - vshr.u64 q11, q4, #2 - veor q10, q10, q7 - veor q11, q11, q6 - vand q10, q10, q9 - vand q11, q11, q9 - veor q7, q7, q10 - vshl.u64 q10, q10, #2 - veor q6, q6, q11 - vshl.u64 q11, q11, #2 - veor q5, q5, q10 - veor q4, q4, q11 - vshr.u64 q10, q1, #2 - vshr.u64 q11, q0, #2 - veor q10, q10, q3 - veor q11, q11, q2 - vand q10, q10, q9 - vand q11, q11, q9 - veor q3, q3, q10 - vshl.u64 q10, q10, #2 - veor q2, q2, q11 - vshl.u64 q11, q11, #2 - veor q1, q1, q10 - veor q0, q0, q11 - vshr.u64 q10, q3, #4 - vshr.u64 q11, q2, #4 - veor q10, q10, q7 - veor q11, q11, q6 - vand q10, q10, q8 - vand q11, q11, q8 - veor q7, q7, q10 - vshl.u64 q10, q10, #4 - veor q6, q6, q11 - vshl.u64 q11, q11, #4 - veor q3, q3, q10 - veor q2, q2, q11 - vshr.u64 q10, q1, #4 - vshr.u64 q11, q0, #4 - veor q10, q10, q5 - veor q11, q11, q4 - vand q10, q10, q8 - vand q11, q11, q8 - veor q5, q5, q10 - vshl.u64 q10, q10, #4 - veor q4, q4, q11 - vshl.u64 q11, q11, #4 - veor q1, q1, q10 - veor q0, q0, q11 - sub r5,r5,#1 - b .Lenc_sbox -.align 4 -.Lenc_loop: - vldmia r4!, {q8-q11} - veor q8, q8, q0 - veor q9, q9, q1 - vtbl.8 d0, {q8}, d24 - vtbl.8 d1, {q8}, d25 - vldmia r4!, {q8} - veor q10, q10, q2 - vtbl.8 d2, {q9}, d24 - vtbl.8 d3, {q9}, d25 - vldmia r4!, {q9} - veor q11, q11, q3 - vtbl.8 d4, {q10}, d24 - vtbl.8 d5, {q10}, d25 - vldmia r4!, {q10} - vtbl.8 d6, {q11}, d24 - vtbl.8 d7, {q11}, d25 - vldmia r4!, {q11} - veor q8, q8, q4 - veor q9, q9, q5 - vtbl.8 d8, {q8}, d24 - vtbl.8 d9, {q8}, d25 - veor q10, q10, q6 - vtbl.8 d10, {q9}, d24 - vtbl.8 d11, {q9}, d25 - veor q11, q11, q7 - vtbl.8 d12, {q10}, d24 - vtbl.8 d13, {q10}, d25 - vtbl.8 d14, {q11}, d24 - vtbl.8 d15, {q11}, d25 -.Lenc_sbox: - veor q2, q2, q1 - veor q5, q5, q6 - veor q3, q3, q0 - veor q6, q6, q2 - veor q5, q5, q0 - - veor q6, q6, q3 - veor q3, q3, q7 - veor q7, q7, q5 - veor q3, q3, q4 - veor q4, q4, q5 - - veor q2, q2, q7 - veor q3, q3, q1 - veor q1, q1, q5 - veor q11, q7, q4 - veor q10, q1, q2 - veor q9, q5, q3 - veor q13, q2, q4 - vmov q8, q10 - veor q12, q6, q0 - - vorr q10, q10, q9 - veor q15, q11, q8 - vand q14, q11, q12 - vorr q11, q11, q12 - veor q12, q12, q9 - vand q8, q8, q9 - veor q9, q3, q0 - vand q15, q15, q12 - vand q13, q13, q9 - veor q9, q7, q1 - veor q12, q5, q6 - veor q11, q11, q13 - veor q10, q10, q13 - vand q13, q9, q12 - vorr q9, q9, q12 - veor q11, q11, q15 - veor q8, q8, q13 - veor q10, q10, q14 - veor q9, q9, q15 - veor q8, q8, q14 - vand q12, q2, q3 - veor q9, q9, q14 - vand q13, q4, q0 - vand q14, q1, q5 - vorr q15, q7, q6 - veor q11, q11, q12 - veor q9, q9, q14 - veor q8, q8, q15 - veor q10, q10, q13 - - @ Inv_GF16 0, 1, 2, 3, s0, s1, s2, s3 - - @ new smaller inversion - - vand q14, q11, q9 - vmov q12, q8 - - veor q13, q10, q14 - veor q15, q8, q14 - veor q14, q8, q14 @ q14=q15 - - vbsl q13, q9, q8 - vbsl q15, q11, q10 - veor q11, q11, q10 - - vbsl q12, q13, q14 - vbsl q8, q14, q13 - - vand q14, q12, q15 - veor q9, q9, q8 - - veor q14, q14, q11 - veor q12, q6, q0 - veor q8, q5, q3 - veor q10, q15, q14 - vand q10, q10, q6 - veor q6, q6, q5 - vand q11, q5, q15 - vand q6, q6, q14 - veor q5, q11, q10 - veor q6, q6, q11 - veor q15, q15, q13 - veor q14, q14, q9 - veor q11, q15, q14 - veor q10, q13, q9 - vand q11, q11, q12 - vand q10, q10, q0 - veor q12, q12, q8 - veor q0, q0, q3 - vand q8, q8, q15 - vand q3, q3, q13 - vand q12, q12, q14 - vand q0, q0, q9 - veor q8, q8, q12 - veor q0, q0, q3 - veor q12, q12, q11 - veor q3, q3, q10 - veor q6, q6, q12 - veor q0, q0, q12 - veor q5, q5, q8 - veor q3, q3, q8 - - veor q12, q7, q4 - veor q8, q1, q2 - veor q11, q15, q14 - veor q10, q13, q9 - vand q11, q11, q12 - vand q10, q10, q4 - veor q12, q12, q8 - veor q4, q4, q2 - vand q8, q8, q15 - vand q2, q2, q13 - vand q12, q12, q14 - vand q4, q4, q9 - veor q8, q8, q12 - veor q4, q4, q2 - veor q12, q12, q11 - veor q2, q2, q10 - veor q15, q15, q13 - veor q14, q14, q9 - veor q10, q15, q14 - vand q10, q10, q7 - veor q7, q7, q1 - vand q11, q1, q15 - vand q7, q7, q14 - veor q1, q11, q10 - veor q7, q7, q11 - veor q7, q7, q12 - veor q4, q4, q12 - veor q1, q1, q8 - veor q2, q2, q8 - veor q7, q7, q0 - veor q1, q1, q6 - veor q6, q6, q0 - veor q4, q4, q7 - veor q0, q0, q1 - - veor q1, q1, q5 - veor q5, q5, q2 - veor q2, q2, q3 - veor q3, q3, q5 - veor q4, q4, q5 - - veor q6, q6, q3 - subs r5,r5,#1 - bcc .Lenc_done - vext.8 q8, q0, q0, #12 @ x0 <<< 32 - vext.8 q9, q1, q1, #12 - veor q0, q0, q8 @ x0 ^ (x0 <<< 32) - vext.8 q10, q4, q4, #12 - veor q1, q1, q9 - vext.8 q11, q6, q6, #12 - veor q4, q4, q10 - vext.8 q12, q3, q3, #12 - veor q6, q6, q11 - vext.8 q13, q7, q7, #12 - veor q3, q3, q12 - vext.8 q14, q2, q2, #12 - veor q7, q7, q13 - vext.8 q15, q5, q5, #12 - veor q2, q2, q14 - - veor q9, q9, q0 - veor q5, q5, q15 - vext.8 q0, q0, q0, #8 @ (x0 ^ (x0 <<< 32)) <<< 64) - veor q10, q10, q1 - veor q8, q8, q5 - veor q9, q9, q5 - vext.8 q1, q1, q1, #8 - veor q13, q13, q3 - veor q0, q0, q8 - veor q14, q14, q7 - veor q1, q1, q9 - vext.8 q8, q3, q3, #8 - veor q12, q12, q6 - vext.8 q9, q7, q7, #8 - veor q15, q15, q2 - vext.8 q3, q6, q6, #8 - veor q11, q11, q4 - vext.8 q7, q5, q5, #8 - veor q12, q12, q5 - vext.8 q6, q2, q2, #8 - veor q11, q11, q5 - vext.8 q2, q4, q4, #8 - veor q5, q9, q13 - veor q4, q8, q12 - veor q3, q3, q11 - veor q7, q7, q15 - veor q6, q6, q14 - @ vmov q4, q8 - veor q2, q2, q10 - @ vmov q5, q9 - vldmia r6, {q12} @ .LSR - ite eq @ Thumb2 thing, samity check in ARM - addeq r6,r6,#0x10 - bne .Lenc_loop - vldmia r6, {q12} @ .LSRM0 - b .Lenc_loop -.align 4 -.Lenc_done: - vmov.i8 q8,#0x55 @ compose .LBS0 - vmov.i8 q9,#0x33 @ compose .LBS1 - vshr.u64 q10, q2, #1 - vshr.u64 q11, q3, #1 - veor q10, q10, q5 - veor q11, q11, q7 - vand q10, q10, q8 - vand q11, q11, q8 - veor q5, q5, q10 - vshl.u64 q10, q10, #1 - veor q7, q7, q11 - vshl.u64 q11, q11, #1 - veor q2, q2, q10 - veor q3, q3, q11 - vshr.u64 q10, q4, #1 - vshr.u64 q11, q0, #1 - veor q10, q10, q6 - veor q11, q11, q1 - vand q10, q10, q8 - vand q11, q11, q8 - veor q6, q6, q10 - vshl.u64 q10, q10, #1 - veor q1, q1, q11 - vshl.u64 q11, q11, #1 - veor q4, q4, q10 - veor q0, q0, q11 - vmov.i8 q8,#0x0f @ compose .LBS2 - vshr.u64 q10, q7, #2 - vshr.u64 q11, q3, #2 - veor q10, q10, q5 - veor q11, q11, q2 - vand q10, q10, q9 - vand q11, q11, q9 - veor q5, q5, q10 - vshl.u64 q10, q10, #2 - veor q2, q2, q11 - vshl.u64 q11, q11, #2 - veor q7, q7, q10 - veor q3, q3, q11 - vshr.u64 q10, q1, #2 - vshr.u64 q11, q0, #2 - veor q10, q10, q6 - veor q11, q11, q4 - vand q10, q10, q9 - vand q11, q11, q9 - veor q6, q6, q10 - vshl.u64 q10, q10, #2 - veor q4, q4, q11 - vshl.u64 q11, q11, #2 - veor q1, q1, q10 - veor q0, q0, q11 - vshr.u64 q10, q6, #4 - vshr.u64 q11, q4, #4 - veor q10, q10, q5 - veor q11, q11, q2 - vand q10, q10, q8 - vand q11, q11, q8 - veor q5, q5, q10 - vshl.u64 q10, q10, #4 - veor q2, q2, q11 - vshl.u64 q11, q11, #4 - veor q6, q6, q10 - veor q4, q4, q11 - vshr.u64 q10, q1, #4 - vshr.u64 q11, q0, #4 - veor q10, q10, q7 - veor q11, q11, q3 - vand q10, q10, q8 - vand q11, q11, q8 - veor q7, q7, q10 - vshl.u64 q10, q10, #4 - veor q3, q3, q11 - vshl.u64 q11, q11, #4 - veor q1, q1, q10 - veor q0, q0, q11 - vldmia r4, {q8} @ last round key - veor q4, q4, q8 - veor q6, q6, q8 - veor q3, q3, q8 - veor q7, q7, q8 - veor q2, q2, q8 - veor q5, q5, q8 - veor q0, q0, q8 - veor q1, q1, q8 - bx lr -.size _bsaes_encrypt8,.-_bsaes_encrypt8 -.type _bsaes_key_convert,%function -.align 4 -_bsaes_key_convert: - adr r6,_bsaes_key_convert - vld1.8 {q7}, [r4]! @ load round 0 key - sub r6,r6,#_bsaes_key_convert-.LM0 - vld1.8 {q15}, [r4]! @ load round 1 key - - vmov.i8 q8, #0x01 @ bit masks - vmov.i8 q9, #0x02 - vmov.i8 q10, #0x04 - vmov.i8 q11, #0x08 - vmov.i8 q12, #0x10 - vmov.i8 q13, #0x20 - vldmia r6, {q14} @ .LM0 - -#ifdef __ARMEL__ - vrev32.8 q7, q7 - vrev32.8 q15, q15 -#endif - sub r5,r5,#1 - vstmia r12!, {q7} @ save round 0 key - b .Lkey_loop - -.align 4 -.Lkey_loop: - vtbl.8 d14,{q15},d28 - vtbl.8 d15,{q15},d29 - vmov.i8 q6, #0x40 - vmov.i8 q15, #0x80 - - vtst.8 q0, q7, q8 - vtst.8 q1, q7, q9 - vtst.8 q2, q7, q10 - vtst.8 q3, q7, q11 - vtst.8 q4, q7, q12 - vtst.8 q5, q7, q13 - vtst.8 q6, q7, q6 - vtst.8 q7, q7, q15 - vld1.8 {q15}, [r4]! @ load next round key - vmvn q0, q0 @ "pnot" - vmvn q1, q1 - vmvn q5, q5 - vmvn q6, q6 -#ifdef __ARMEL__ - vrev32.8 q15, q15 -#endif - subs r5,r5,#1 - vstmia r12!,{q0-q7} @ write bit-sliced round key - bne .Lkey_loop - - vmov.i8 q7,#0x63 @ compose .L63 - @ don't save last round key - bx lr -.size _bsaes_key_convert,.-_bsaes_key_convert -.extern AES_cbc_encrypt -.extern AES_decrypt - -.global bsaes_cbc_encrypt -.type bsaes_cbc_encrypt,%function -.align 5 -bsaes_cbc_encrypt: -#ifndef __KERNEL__ - cmp r2, #128 -#ifndef __thumb__ - blo AES_cbc_encrypt -#else - bhs 1f - b AES_cbc_encrypt -1: -#endif -#endif - - @ it is up to the caller to make sure we are called with enc == 0 - - mov ip, sp - stmdb sp!, {r4-r10, lr} - VFP_ABI_PUSH - ldr r8, [ip] @ IV is 1st arg on the stack - mov r2, r2, lsr#4 @ len in 16 byte blocks - sub sp, #0x10 @ scratch space to carry over the IV - mov r9, sp @ save sp - - ldr r10, [r3, #240] @ get # of rounds -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, r10, lsl#7 @ 128 bytes per inner round key - add r12, #96 @ sifze of bit-slices key schedule - - @ populate the key schedule - mov r4, r3 @ pass key - mov r5, r10 @ pass # of rounds - mov sp, r12 @ sp is sp - bl _bsaes_key_convert - vldmia sp, {q6} - vstmia r12, {q15} @ save last round key - veor q7, q7, q6 @ fix up round 0 key - vstmia sp, {q7} -#else - ldr r12, [r3, #244] - eors r12, #1 - beq 0f - - @ populate the key schedule - str r12, [r3, #244] - mov r4, r3 @ pass key - mov r5, r10 @ pass # of rounds - add r12, r3, #248 @ pass key schedule - bl _bsaes_key_convert - add r4, r3, #248 - vldmia r4, {q6} - vstmia r12, {q15} @ save last round key - veor q7, q7, q6 @ fix up round 0 key - vstmia r4, {q7} - -.align 2 -0: -#endif - - vld1.8 {q15}, [r8] @ load IV - b .Lcbc_dec_loop - -.align 4 -.Lcbc_dec_loop: - subs r2, r2, #0x8 - bmi .Lcbc_dec_loop_finish - - vld1.8 {q0-q1}, [r0]! @ load input - vld1.8 {q2-q3}, [r0]! -#ifndef BSAES_ASM_EXTENDED_KEY - mov r4, sp @ pass the key -#else - add r4, r3, #248 -#endif - vld1.8 {q4-q5}, [r0]! - mov r5, r10 - vld1.8 {q6-q7}, [r0] - sub r0, r0, #0x60 - vstmia r9, {q15} @ put aside IV - - bl _bsaes_decrypt8 - - vldmia r9, {q14} @ reload IV - vld1.8 {q8-q9}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q10-q11}, [r0]! - veor q1, q1, q8 - veor q6, q6, q9 - vld1.8 {q12-q13}, [r0]! - veor q4, q4, q10 - veor q2, q2, q11 - vld1.8 {q14-q15}, [r0]! - veor q7, q7, q12 - vst1.8 {q0-q1}, [r1]! @ write output - veor q3, q3, q13 - vst1.8 {q6}, [r1]! - veor q5, q5, q14 - vst1.8 {q4}, [r1]! - vst1.8 {q2}, [r1]! - vst1.8 {q7}, [r1]! - vst1.8 {q3}, [r1]! - vst1.8 {q5}, [r1]! - - b .Lcbc_dec_loop - -.Lcbc_dec_loop_finish: - adds r2, r2, #8 - beq .Lcbc_dec_done - - vld1.8 {q0}, [r0]! @ load input - cmp r2, #2 - blo .Lcbc_dec_one - vld1.8 {q1}, [r0]! -#ifndef BSAES_ASM_EXTENDED_KEY - mov r4, sp @ pass the key -#else - add r4, r3, #248 -#endif - mov r5, r10 - vstmia r9, {q15} @ put aside IV - beq .Lcbc_dec_two - vld1.8 {q2}, [r0]! - cmp r2, #4 - blo .Lcbc_dec_three - vld1.8 {q3}, [r0]! - beq .Lcbc_dec_four - vld1.8 {q4}, [r0]! - cmp r2, #6 - blo .Lcbc_dec_five - vld1.8 {q5}, [r0]! - beq .Lcbc_dec_six - vld1.8 {q6}, [r0]! - sub r0, r0, #0x70 - - bl _bsaes_decrypt8 - - vldmia r9, {q14} @ reload IV - vld1.8 {q8-q9}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q10-q11}, [r0]! - veor q1, q1, q8 - veor q6, q6, q9 - vld1.8 {q12-q13}, [r0]! - veor q4, q4, q10 - veor q2, q2, q11 - vld1.8 {q15}, [r0]! - veor q7, q7, q12 - vst1.8 {q0-q1}, [r1]! @ write output - veor q3, q3, q13 - vst1.8 {q6}, [r1]! - vst1.8 {q4}, [r1]! - vst1.8 {q2}, [r1]! - vst1.8 {q7}, [r1]! - vst1.8 {q3}, [r1]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_six: - sub r0, r0, #0x60 - bl _bsaes_decrypt8 - vldmia r9,{q14} @ reload IV - vld1.8 {q8-q9}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q10-q11}, [r0]! - veor q1, q1, q8 - veor q6, q6, q9 - vld1.8 {q12}, [r0]! - veor q4, q4, q10 - veor q2, q2, q11 - vld1.8 {q15}, [r0]! - veor q7, q7, q12 - vst1.8 {q0-q1}, [r1]! @ write output - vst1.8 {q6}, [r1]! - vst1.8 {q4}, [r1]! - vst1.8 {q2}, [r1]! - vst1.8 {q7}, [r1]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_five: - sub r0, r0, #0x50 - bl _bsaes_decrypt8 - vldmia r9, {q14} @ reload IV - vld1.8 {q8-q9}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q10-q11}, [r0]! - veor q1, q1, q8 - veor q6, q6, q9 - vld1.8 {q15}, [r0]! - veor q4, q4, q10 - vst1.8 {q0-q1}, [r1]! @ write output - veor q2, q2, q11 - vst1.8 {q6}, [r1]! - vst1.8 {q4}, [r1]! - vst1.8 {q2}, [r1]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_four: - sub r0, r0, #0x40 - bl _bsaes_decrypt8 - vldmia r9, {q14} @ reload IV - vld1.8 {q8-q9}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q10}, [r0]! - veor q1, q1, q8 - veor q6, q6, q9 - vld1.8 {q15}, [r0]! - veor q4, q4, q10 - vst1.8 {q0-q1}, [r1]! @ write output - vst1.8 {q6}, [r1]! - vst1.8 {q4}, [r1]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_three: - sub r0, r0, #0x30 - bl _bsaes_decrypt8 - vldmia r9, {q14} @ reload IV - vld1.8 {q8-q9}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q15}, [r0]! - veor q1, q1, q8 - veor q6, q6, q9 - vst1.8 {q0-q1}, [r1]! @ write output - vst1.8 {q6}, [r1]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_two: - sub r0, r0, #0x20 - bl _bsaes_decrypt8 - vldmia r9, {q14} @ reload IV - vld1.8 {q8}, [r0]! @ reload input - veor q0, q0, q14 @ ^= IV - vld1.8 {q15}, [r0]! @ reload input - veor q1, q1, q8 - vst1.8 {q0-q1}, [r1]! @ write output - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_one: - sub r0, r0, #0x10 - mov r10, r1 @ save original out pointer - mov r1, r9 @ use the iv scratch space as out buffer - mov r2, r3 - vmov q4,q15 @ just in case ensure that IV - vmov q5,q0 @ and input are preserved - bl AES_decrypt - vld1.8 {q0}, [r9,:64] @ load result - veor q0, q0, q4 @ ^= IV - vmov q15, q5 @ q5 holds input - vst1.8 {q0}, [r10] @ write output - -.Lcbc_dec_done: -#ifndef BSAES_ASM_EXTENDED_KEY - vmov.i32 q0, #0 - vmov.i32 q1, #0 -.Lcbc_dec_bzero: @ wipe key schedule [if any] - vstmia sp!, {q0-q1} - cmp sp, r9 - bne .Lcbc_dec_bzero -#endif - - mov sp, r9 - add sp, #0x10 @ add sp,r9,#0x10 is no good for thumb - vst1.8 {q15}, [r8] @ return IV - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} -.size bsaes_cbc_encrypt,.-bsaes_cbc_encrypt -.extern AES_encrypt -.global bsaes_ctr32_encrypt_blocks -.type bsaes_ctr32_encrypt_blocks,%function -.align 5 -bsaes_ctr32_encrypt_blocks: - cmp r2, #8 @ use plain AES for - blo .Lctr_enc_short @ small sizes - - mov ip, sp - stmdb sp!, {r4-r10, lr} - VFP_ABI_PUSH - ldr r8, [ip] @ ctr is 1st arg on the stack - sub sp, sp, #0x10 @ scratch space to carry over the ctr - mov r9, sp @ save sp - - ldr r10, [r3, #240] @ get # of rounds -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, r10, lsl#7 @ 128 bytes per inner round key - add r12, #96 @ size of bit-sliced key schedule - - @ populate the key schedule - mov r4, r3 @ pass key - mov r5, r10 @ pass # of rounds - mov sp, r12 @ sp is sp - bl _bsaes_key_convert - veor q7,q7,q15 @ fix up last round key - vstmia r12, {q7} @ save last round key - - vld1.8 {q0}, [r8] @ load counter - add r8, r6, #.LREVM0SR-.LM0 @ borrow r8 - vldmia sp, {q4} @ load round0 key -#else - ldr r12, [r3, #244] - eors r12, #1 - beq 0f - - @ populate the key schedule - str r12, [r3, #244] - mov r4, r3 @ pass key - mov r5, r10 @ pass # of rounds - add r12, r3, #248 @ pass key schedule - bl _bsaes_key_convert - veor q7,q7,q15 @ fix up last round key - vstmia r12, {q7} @ save last round key - -.align 2 -0: add r12, r3, #248 - vld1.8 {q0}, [r8] @ load counter - adrl r8, .LREVM0SR @ borrow r8 - vldmia r12, {q4} @ load round0 key - sub sp, #0x10 @ place for adjusted round0 key -#endif - - vmov.i32 q8,#1 @ compose 1<<96 - veor q9,q9,q9 - vrev32.8 q0,q0 - vext.8 q8,q9,q8,#4 - vrev32.8 q4,q4 - vadd.u32 q9,q8,q8 @ compose 2<<96 - vstmia sp, {q4} @ save adjusted round0 key - b .Lctr_enc_loop - -.align 4 -.Lctr_enc_loop: - vadd.u32 q10, q8, q9 @ compose 3<<96 - vadd.u32 q1, q0, q8 @ +1 - vadd.u32 q2, q0, q9 @ +2 - vadd.u32 q3, q0, q10 @ +3 - vadd.u32 q4, q1, q10 - vadd.u32 q5, q2, q10 - vadd.u32 q6, q3, q10 - vadd.u32 q7, q4, q10 - vadd.u32 q10, q5, q10 @ next counter - - @ Borrow prologue from _bsaes_encrypt8 to use the opportunity - @ to flip byte order in 32-bit counter - - vldmia sp, {q9} @ load round0 key -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x10 @ pass next round key -#else - add r4, r3, #264 -#endif - vldmia r8, {q8} @ .LREVM0SR - mov r5, r10 @ pass rounds - vstmia r9, {q10} @ save next counter - sub r6, r8, #.LREVM0SR-.LSR @ pass constants - - bl _bsaes_encrypt8_alt - - subs r2, r2, #8 - blo .Lctr_enc_loop_done - - vld1.8 {q8-q9}, [r0]! @ load input - vld1.8 {q10-q11}, [r0]! - veor q0, q8 - veor q1, q9 - vld1.8 {q12-q13}, [r0]! - veor q4, q10 - veor q6, q11 - vld1.8 {q14-q15}, [r0]! - veor q3, q12 - vst1.8 {q0-q1}, [r1]! @ write output - veor q7, q13 - veor q2, q14 - vst1.8 {q4}, [r1]! - veor q5, q15 - vst1.8 {q6}, [r1]! - vmov.i32 q8, #1 @ compose 1<<96 - vst1.8 {q3}, [r1]! - veor q9, q9, q9 - vst1.8 {q7}, [r1]! - vext.8 q8, q9, q8, #4 - vst1.8 {q2}, [r1]! - vadd.u32 q9,q8,q8 @ compose 2<<96 - vst1.8 {q5}, [r1]! - vldmia r9, {q0} @ load counter - - bne .Lctr_enc_loop - b .Lctr_enc_done - -.align 4 -.Lctr_enc_loop_done: - add r2, r2, #8 - vld1.8 {q8}, [r0]! @ load input - veor q0, q8 - vst1.8 {q0}, [r1]! @ write output - cmp r2, #2 - blo .Lctr_enc_done - vld1.8 {q9}, [r0]! - veor q1, q9 - vst1.8 {q1}, [r1]! - beq .Lctr_enc_done - vld1.8 {q10}, [r0]! - veor q4, q10 - vst1.8 {q4}, [r1]! - cmp r2, #4 - blo .Lctr_enc_done - vld1.8 {q11}, [r0]! - veor q6, q11 - vst1.8 {q6}, [r1]! - beq .Lctr_enc_done - vld1.8 {q12}, [r0]! - veor q3, q12 - vst1.8 {q3}, [r1]! - cmp r2, #6 - blo .Lctr_enc_done - vld1.8 {q13}, [r0]! - veor q7, q13 - vst1.8 {q7}, [r1]! - beq .Lctr_enc_done - vld1.8 {q14}, [r0] - veor q2, q14 - vst1.8 {q2}, [r1]! - -.Lctr_enc_done: - vmov.i32 q0, #0 - vmov.i32 q1, #0 -#ifndef BSAES_ASM_EXTENDED_KEY -.Lctr_enc_bzero: @ wipe key schedule [if any] - vstmia sp!, {q0-q1} - cmp sp, r9 - bne .Lctr_enc_bzero -#else - vstmia sp, {q0-q1} -#endif - - mov sp, r9 - add sp, #0x10 @ add sp,r9,#0x10 is no good for thumb - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} @ return - -.align 4 -.Lctr_enc_short: - ldr ip, [sp] @ ctr pointer is passed on stack - stmdb sp!, {r4-r8, lr} - - mov r4, r0 @ copy arguments - mov r5, r1 - mov r6, r2 - mov r7, r3 - ldr r8, [ip, #12] @ load counter LSW - vld1.8 {q1}, [ip] @ load whole counter value -#ifdef __ARMEL__ - rev r8, r8 -#endif - sub sp, sp, #0x10 - vst1.8 {q1}, [sp,:64] @ copy counter value - sub sp, sp, #0x10 - -.Lctr_enc_short_loop: - add r0, sp, #0x10 @ input counter value - mov r1, sp @ output on the stack - mov r2, r7 @ key - - bl AES_encrypt - - vld1.8 {q0}, [r4]! @ load input - vld1.8 {q1}, [sp,:64] @ load encrypted counter - add r8, r8, #1 -#ifdef __ARMEL__ - rev r0, r8 - str r0, [sp, #0x1c] @ next counter value -#else - str r8, [sp, #0x1c] @ next counter value -#endif - veor q0,q0,q1 - vst1.8 {q0}, [r5]! @ store output - subs r6, r6, #1 - bne .Lctr_enc_short_loop - - vmov.i32 q0, #0 - vmov.i32 q1, #0 - vstmia sp!, {q0-q1} - - ldmia sp!, {r4-r8, pc} -.size bsaes_ctr32_encrypt_blocks,.-bsaes_ctr32_encrypt_blocks -.globl bsaes_xts_encrypt -.type bsaes_xts_encrypt,%function -.align 4 -bsaes_xts_encrypt: - mov ip, sp - stmdb sp!, {r4-r10, lr} @ 0x20 - VFP_ABI_PUSH - mov r6, sp @ future r3 - - mov r7, r0 - mov r8, r1 - mov r9, r2 - mov r10, r3 - - sub r0, sp, #0x10 @ 0x10 - bic r0, #0xf @ align at 16 bytes - mov sp, r0 - -#ifdef XTS_CHAIN_TWEAK - ldr r0, [ip] @ pointer to input tweak -#else - @ generate initial tweak - ldr r0, [ip, #4] @ iv[] - mov r1, sp - ldr r2, [ip, #0] @ key2 - bl AES_encrypt - mov r0,sp @ pointer to initial tweak -#endif - - ldr r1, [r10, #240] @ get # of rounds - mov r3, r6 -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, r1, lsl#7 @ 128 bytes per inner round key - @ add r12, #96 @ size of bit-sliced key schedule - sub r12, #48 @ place for tweak[9] - - @ populate the key schedule - mov r4, r10 @ pass key - mov r5, r1 @ pass # of rounds - mov sp, r12 - add r12, #0x90 @ pass key schedule - bl _bsaes_key_convert - veor q7, q7, q15 @ fix up last round key - vstmia r12, {q7} @ save last round key -#else - ldr r12, [r10, #244] - eors r12, #1 - beq 0f - - str r12, [r10, #244] - mov r4, r10 @ pass key - mov r5, r1 @ pass # of rounds - add r12, r10, #248 @ pass key schedule - bl _bsaes_key_convert - veor q7, q7, q15 @ fix up last round key - vstmia r12, {q7} - -.align 2 -0: sub sp, #0x90 @ place for tweak[9] -#endif - - vld1.8 {q8}, [r0] @ initial tweak - adr r2, .Lxts_magic - - subs r9, #0x80 - blo .Lxts_enc_short - b .Lxts_enc_loop - -.align 4 -.Lxts_enc_loop: - vldmia r2, {q5} @ load XTS magic - vshr.s64 q6, q8, #63 - mov r0, sp - vand q6, q6, q5 - vadd.u64 q9, q8, q8 - vst1.64 {q8}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q9, #63 - veor q9, q9, q6 - vand q7, q7, q5 - vadd.u64 q10, q9, q9 - vst1.64 {q9}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q10, #63 - veor q10, q10, q7 - vand q6, q6, q5 - vld1.8 {q0}, [r7]! - vadd.u64 q11, q10, q10 - vst1.64 {q10}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q11, #63 - veor q11, q11, q6 - vand q7, q7, q5 - vld1.8 {q1}, [r7]! - veor q0, q0, q8 - vadd.u64 q12, q11, q11 - vst1.64 {q11}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q12, #63 - veor q12, q12, q7 - vand q6, q6, q5 - vld1.8 {q2}, [r7]! - veor q1, q1, q9 - vadd.u64 q13, q12, q12 - vst1.64 {q12}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q13, #63 - veor q13, q13, q6 - vand q7, q7, q5 - vld1.8 {q3}, [r7]! - veor q2, q2, q10 - vadd.u64 q14, q13, q13 - vst1.64 {q13}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q14, #63 - veor q14, q14, q7 - vand q6, q6, q5 - vld1.8 {q4}, [r7]! - veor q3, q3, q11 - vadd.u64 q15, q14, q14 - vst1.64 {q14}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q15, #63 - veor q15, q15, q6 - vand q7, q7, q5 - vld1.8 {q5}, [r7]! - veor q4, q4, q12 - vadd.u64 q8, q15, q15 - vst1.64 {q15}, [r0,:128]! - vswp d15,d14 - veor q8, q8, q7 - vst1.64 {q8}, [r0,:128] @ next round tweak - - vld1.8 {q6-q7}, [r7]! - veor q5, q5, q13 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q6, q6, q14 - mov r5, r1 @ pass rounds - veor q7, q7, q15 - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12-q13}, [r0,:128]! - veor q1, q1, q9 - veor q8, q4, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q6, q11 - vld1.64 {q14-q15}, [r0,:128]! - veor q10, q3, q12 - vst1.8 {q8-q9}, [r8]! - veor q11, q7, q13 - veor q12, q2, q14 - vst1.8 {q10-q11}, [r8]! - veor q13, q5, q15 - vst1.8 {q12-q13}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - - subs r9, #0x80 - bpl .Lxts_enc_loop - -.Lxts_enc_short: - adds r9, #0x70 - bmi .Lxts_enc_done - - vldmia r2, {q5} @ load XTS magic - vshr.s64 q7, q8, #63 - mov r0, sp - vand q7, q7, q5 - vadd.u64 q9, q8, q8 - vst1.64 {q8}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q9, #63 - veor q9, q9, q7 - vand q6, q6, q5 - vadd.u64 q10, q9, q9 - vst1.64 {q9}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q10, #63 - veor q10, q10, q6 - vand q7, q7, q5 - vld1.8 {q0}, [r7]! - subs r9, #0x10 - bmi .Lxts_enc_1 - vadd.u64 q11, q10, q10 - vst1.64 {q10}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q11, #63 - veor q11, q11, q7 - vand q6, q6, q5 - vld1.8 {q1}, [r7]! - subs r9, #0x10 - bmi .Lxts_enc_2 - veor q0, q0, q8 - vadd.u64 q12, q11, q11 - vst1.64 {q11}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q12, #63 - veor q12, q12, q6 - vand q7, q7, q5 - vld1.8 {q2}, [r7]! - subs r9, #0x10 - bmi .Lxts_enc_3 - veor q1, q1, q9 - vadd.u64 q13, q12, q12 - vst1.64 {q12}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q13, #63 - veor q13, q13, q7 - vand q6, q6, q5 - vld1.8 {q3}, [r7]! - subs r9, #0x10 - bmi .Lxts_enc_4 - veor q2, q2, q10 - vadd.u64 q14, q13, q13 - vst1.64 {q13}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q14, #63 - veor q14, q14, q6 - vand q7, q7, q5 - vld1.8 {q4}, [r7]! - subs r9, #0x10 - bmi .Lxts_enc_5 - veor q3, q3, q11 - vadd.u64 q15, q14, q14 - vst1.64 {q14}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q15, #63 - veor q15, q15, q7 - vand q6, q6, q5 - vld1.8 {q5}, [r7]! - subs r9, #0x10 - bmi .Lxts_enc_6 - veor q4, q4, q12 - sub r9, #0x10 - vst1.64 {q15}, [r0,:128] @ next round tweak - - vld1.8 {q6}, [r7]! - veor q5, q5, q13 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q6, q6, q14 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12-q13}, [r0,:128]! - veor q1, q1, q9 - veor q8, q4, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q6, q11 - vld1.64 {q14}, [r0,:128]! - veor q10, q3, q12 - vst1.8 {q8-q9}, [r8]! - veor q11, q7, q13 - veor q12, q2, q14 - vst1.8 {q10-q11}, [r8]! - vst1.8 {q12}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_6: - vst1.64 {q14}, [r0,:128] @ next round tweak - - veor q4, q4, q12 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q5, q5, q13 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12-q13}, [r0,:128]! - veor q1, q1, q9 - veor q8, q4, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q6, q11 - veor q10, q3, q12 - vst1.8 {q8-q9}, [r8]! - veor q11, q7, q13 - vst1.8 {q10-q11}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_enc_done - -@ put this in range for both ARM and Thumb mode adr instructions -.align 5 -.Lxts_magic: - .quad 1, 0x87 - -.align 5 -.Lxts_enc_5: - vst1.64 {q13}, [r0,:128] @ next round tweak - - veor q3, q3, q11 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q4, q4, q12 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12}, [r0,:128]! - veor q1, q1, q9 - veor q8, q4, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q6, q11 - veor q10, q3, q12 - vst1.8 {q8-q9}, [r8]! - vst1.8 {q10}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_4: - vst1.64 {q12}, [r0,:128] @ next round tweak - - veor q2, q2, q10 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q3, q3, q11 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - veor q1, q1, q9 - veor q8, q4, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q6, q11 - vst1.8 {q8-q9}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_3: - vst1.64 {q11}, [r0,:128] @ next round tweak - - veor q1, q1, q9 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q2, q2, q10 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10}, [r0,:128]! - veor q0, q0, q8 - veor q1, q1, q9 - veor q8, q4, q10 - vst1.8 {q0-q1}, [r8]! - vst1.8 {q8}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_2: - vst1.64 {q10}, [r0,:128] @ next round tweak - - veor q0, q0, q8 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q1, q1, q9 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - veor q0, q0, q8 - veor q1, q1, q9 - vst1.8 {q0-q1}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_1: - mov r0, sp - veor q0, q8 - mov r1, sp - vst1.8 {q0}, [sp,:128] - mov r2, r10 - mov r4, r3 @ preserve fp - - bl AES_encrypt - - vld1.8 {q0}, [sp,:128] - veor q0, q0, q8 - vst1.8 {q0}, [r8]! - mov r3, r4 - - vmov q8, q9 @ next round tweak - -.Lxts_enc_done: -#ifndef XTS_CHAIN_TWEAK - adds r9, #0x10 - beq .Lxts_enc_ret - sub r6, r8, #0x10 - -.Lxts_enc_steal: - ldrb r0, [r7], #1 - ldrb r1, [r8, #-0x10] - strb r0, [r8, #-0x10] - strb r1, [r8], #1 - - subs r9, #1 - bhi .Lxts_enc_steal - - vld1.8 {q0}, [r6] - mov r0, sp - veor q0, q0, q8 - mov r1, sp - vst1.8 {q0}, [sp,:128] - mov r2, r10 - mov r4, r3 @ preserve fp - - bl AES_encrypt - - vld1.8 {q0}, [sp,:128] - veor q0, q0, q8 - vst1.8 {q0}, [r6] - mov r3, r4 -#endif - -.Lxts_enc_ret: - bic r0, r3, #0xf - vmov.i32 q0, #0 - vmov.i32 q1, #0 -#ifdef XTS_CHAIN_TWEAK - ldr r1, [r3, #0x20+VFP_ABI_FRAME] @ chain tweak -#endif -.Lxts_enc_bzero: @ wipe key schedule [if any] - vstmia sp!, {q0-q1} - cmp sp, r0 - bne .Lxts_enc_bzero - - mov sp, r3 -#ifdef XTS_CHAIN_TWEAK - vst1.8 {q8}, [r1] -#endif - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} @ return - -.size bsaes_xts_encrypt,.-bsaes_xts_encrypt - -.globl bsaes_xts_decrypt -.type bsaes_xts_decrypt,%function -.align 4 -bsaes_xts_decrypt: - mov ip, sp - stmdb sp!, {r4-r10, lr} @ 0x20 - VFP_ABI_PUSH - mov r6, sp @ future r3 - - mov r7, r0 - mov r8, r1 - mov r9, r2 - mov r10, r3 - - sub r0, sp, #0x10 @ 0x10 - bic r0, #0xf @ align at 16 bytes - mov sp, r0 - -#ifdef XTS_CHAIN_TWEAK - ldr r0, [ip] @ pointer to input tweak -#else - @ generate initial tweak - ldr r0, [ip, #4] @ iv[] - mov r1, sp - ldr r2, [ip, #0] @ key2 - bl AES_encrypt - mov r0, sp @ pointer to initial tweak -#endif - - ldr r1, [r10, #240] @ get # of rounds - mov r3, r6 -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, r1, lsl#7 @ 128 bytes per inner round key - @ add r12, #96 @ size of bit-sliced key schedule - sub r12, #48 @ place for tweak[9] - - @ populate the key schedule - mov r4, r10 @ pass key - mov r5, r1 @ pass # of rounds - mov sp, r12 - add r12, #0x90 @ pass key schedule - bl _bsaes_key_convert - add r4, sp, #0x90 - vldmia r4, {q6} - vstmia r12, {q15} @ save last round key - veor q7, q7, q6 @ fix up round 0 key - vstmia r4, {q7} -#else - ldr r12, [r10, #244] - eors r12, #1 - beq 0f - - str r12, [r10, #244] - mov r4, r10 @ pass key - mov r5, r1 @ pass # of rounds - add r12, r10, #248 @ pass key schedule - bl _bsaes_key_convert - add r4, r10, #248 - vldmia r4, {q6} - vstmia r12, {q15} @ save last round key - veor q7, q7, q6 @ fix up round 0 key - vstmia r4, {q7} - -.align 2 -0: sub sp, #0x90 @ place for tweak[9] -#endif - vld1.8 {q8}, [r0] @ initial tweak - adr r2, .Lxts_magic - - tst r9, #0xf @ if not multiple of 16 - it ne @ Thumb2 thing, sanity check in ARM - subne r9, #0x10 @ subtract another 16 bytes - subs r9, #0x80 - - blo .Lxts_dec_short - b .Lxts_dec_loop - -.align 4 -.Lxts_dec_loop: - vldmia r2, {q5} @ load XTS magic - vshr.s64 q6, q8, #63 - mov r0, sp - vand q6, q6, q5 - vadd.u64 q9, q8, q8 - vst1.64 {q8}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q9, #63 - veor q9, q9, q6 - vand q7, q7, q5 - vadd.u64 q10, q9, q9 - vst1.64 {q9}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q10, #63 - veor q10, q10, q7 - vand q6, q6, q5 - vld1.8 {q0}, [r7]! - vadd.u64 q11, q10, q10 - vst1.64 {q10}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q11, #63 - veor q11, q11, q6 - vand q7, q7, q5 - vld1.8 {q1}, [r7]! - veor q0, q0, q8 - vadd.u64 q12, q11, q11 - vst1.64 {q11}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q12, #63 - veor q12, q12, q7 - vand q6, q6, q5 - vld1.8 {q2}, [r7]! - veor q1, q1, q9 - vadd.u64 q13, q12, q12 - vst1.64 {q12}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q13, #63 - veor q13, q13, q6 - vand q7, q7, q5 - vld1.8 {q3}, [r7]! - veor q2, q2, q10 - vadd.u64 q14, q13, q13 - vst1.64 {q13}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q14, #63 - veor q14, q14, q7 - vand q6, q6, q5 - vld1.8 {q4}, [r7]! - veor q3, q3, q11 - vadd.u64 q15, q14, q14 - vst1.64 {q14}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q15, #63 - veor q15, q15, q6 - vand q7, q7, q5 - vld1.8 {q5}, [r7]! - veor q4, q4, q12 - vadd.u64 q8, q15, q15 - vst1.64 {q15}, [r0,:128]! - vswp d15,d14 - veor q8, q8, q7 - vst1.64 {q8}, [r0,:128] @ next round tweak - - vld1.8 {q6-q7}, [r7]! - veor q5, q5, q13 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q6, q6, q14 - mov r5, r1 @ pass rounds - veor q7, q7, q15 - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12-q13}, [r0,:128]! - veor q1, q1, q9 - veor q8, q6, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q4, q11 - vld1.64 {q14-q15}, [r0,:128]! - veor q10, q2, q12 - vst1.8 {q8-q9}, [r8]! - veor q11, q7, q13 - veor q12, q3, q14 - vst1.8 {q10-q11}, [r8]! - veor q13, q5, q15 - vst1.8 {q12-q13}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - - subs r9, #0x80 - bpl .Lxts_dec_loop - -.Lxts_dec_short: - adds r9, #0x70 - bmi .Lxts_dec_done - - vldmia r2, {q5} @ load XTS magic - vshr.s64 q7, q8, #63 - mov r0, sp - vand q7, q7, q5 - vadd.u64 q9, q8, q8 - vst1.64 {q8}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q9, #63 - veor q9, q9, q7 - vand q6, q6, q5 - vadd.u64 q10, q9, q9 - vst1.64 {q9}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q10, #63 - veor q10, q10, q6 - vand q7, q7, q5 - vld1.8 {q0}, [r7]! - subs r9, #0x10 - bmi .Lxts_dec_1 - vadd.u64 q11, q10, q10 - vst1.64 {q10}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q11, #63 - veor q11, q11, q7 - vand q6, q6, q5 - vld1.8 {q1}, [r7]! - subs r9, #0x10 - bmi .Lxts_dec_2 - veor q0, q0, q8 - vadd.u64 q12, q11, q11 - vst1.64 {q11}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q12, #63 - veor q12, q12, q6 - vand q7, q7, q5 - vld1.8 {q2}, [r7]! - subs r9, #0x10 - bmi .Lxts_dec_3 - veor q1, q1, q9 - vadd.u64 q13, q12, q12 - vst1.64 {q12}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q13, #63 - veor q13, q13, q7 - vand q6, q6, q5 - vld1.8 {q3}, [r7]! - subs r9, #0x10 - bmi .Lxts_dec_4 - veor q2, q2, q10 - vadd.u64 q14, q13, q13 - vst1.64 {q13}, [r0,:128]! - vswp d13,d12 - vshr.s64 q7, q14, #63 - veor q14, q14, q6 - vand q7, q7, q5 - vld1.8 {q4}, [r7]! - subs r9, #0x10 - bmi .Lxts_dec_5 - veor q3, q3, q11 - vadd.u64 q15, q14, q14 - vst1.64 {q14}, [r0,:128]! - vswp d15,d14 - vshr.s64 q6, q15, #63 - veor q15, q15, q7 - vand q6, q6, q5 - vld1.8 {q5}, [r7]! - subs r9, #0x10 - bmi .Lxts_dec_6 - veor q4, q4, q12 - sub r9, #0x10 - vst1.64 {q15}, [r0,:128] @ next round tweak - - vld1.8 {q6}, [r7]! - veor q5, q5, q13 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q6, q6, q14 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12-q13}, [r0,:128]! - veor q1, q1, q9 - veor q8, q6, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q4, q11 - vld1.64 {q14}, [r0,:128]! - veor q10, q2, q12 - vst1.8 {q8-q9}, [r8]! - veor q11, q7, q13 - veor q12, q3, q14 - vst1.8 {q10-q11}, [r8]! - vst1.8 {q12}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_6: - vst1.64 {q14}, [r0,:128] @ next round tweak - - veor q4, q4, q12 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q5, q5, q13 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12-q13}, [r0,:128]! - veor q1, q1, q9 - veor q8, q6, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q4, q11 - veor q10, q2, q12 - vst1.8 {q8-q9}, [r8]! - veor q11, q7, q13 - vst1.8 {q10-q11}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_5: - vst1.64 {q13}, [r0,:128] @ next round tweak - - veor q3, q3, q11 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q4, q4, q12 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - vld1.64 {q12}, [r0,:128]! - veor q1, q1, q9 - veor q8, q6, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q4, q11 - veor q10, q2, q12 - vst1.8 {q8-q9}, [r8]! - vst1.8 {q10}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_4: - vst1.64 {q12}, [r0,:128] @ next round tweak - - veor q2, q2, q10 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q3, q3, q11 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10-q11}, [r0,:128]! - veor q0, q0, q8 - veor q1, q1, q9 - veor q8, q6, q10 - vst1.8 {q0-q1}, [r8]! - veor q9, q4, q11 - vst1.8 {q8-q9}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_3: - vst1.64 {q11}, [r0,:128] @ next round tweak - - veor q1, q1, q9 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q2, q2, q10 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - vld1.64 {q10}, [r0,:128]! - veor q0, q0, q8 - veor q1, q1, q9 - veor q8, q6, q10 - vst1.8 {q0-q1}, [r8]! - vst1.8 {q8}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_2: - vst1.64 {q10}, [r0,:128] @ next round tweak - - veor q0, q0, q8 -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, r10, #248 @ pass key schedule -#endif - veor q1, q1, q9 - mov r5, r1 @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {q8-q9}, [r0,:128]! - veor q0, q0, q8 - veor q1, q1, q9 - vst1.8 {q0-q1}, [r8]! - - vld1.64 {q8}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_1: - mov r0, sp - veor q0, q8 - mov r1, sp - vst1.8 {q0}, [sp,:128] - mov r2, r10 - mov r4, r3 @ preserve fp - mov r5, r2 @ preserve magic - - bl AES_decrypt - - vld1.8 {q0}, [sp,:128] - veor q0, q0, q8 - vst1.8 {q0}, [r8]! - mov r3, r4 - mov r2, r5 - - vmov q8, q9 @ next round tweak - -.Lxts_dec_done: -#ifndef XTS_CHAIN_TWEAK - adds r9, #0x10 - beq .Lxts_dec_ret - - @ calculate one round of extra tweak for the stolen ciphertext - vldmia r2, {q5} - vshr.s64 q6, q8, #63 - vand q6, q6, q5 - vadd.u64 q9, q8, q8 - vswp d13,d12 - veor q9, q9, q6 - - @ perform the final decryption with the last tweak value - vld1.8 {q0}, [r7]! - mov r0, sp - veor q0, q0, q9 - mov r1, sp - vst1.8 {q0}, [sp,:128] - mov r2, r10 - mov r4, r3 @ preserve fp - - bl AES_decrypt - - vld1.8 {q0}, [sp,:128] - veor q0, q0, q9 - vst1.8 {q0}, [r8] - - mov r6, r8 -.Lxts_dec_steal: - ldrb r1, [r8] - ldrb r0, [r7], #1 - strb r1, [r8, #0x10] - strb r0, [r8], #1 - - subs r9, #1 - bhi .Lxts_dec_steal - - vld1.8 {q0}, [r6] - mov r0, sp - veor q0, q8 - mov r1, sp - vst1.8 {q0}, [sp,:128] - mov r2, r10 - - bl AES_decrypt - - vld1.8 {q0}, [sp,:128] - veor q0, q0, q8 - vst1.8 {q0}, [r6] - mov r3, r4 -#endif - -.Lxts_dec_ret: - bic r0, r3, #0xf - vmov.i32 q0, #0 - vmov.i32 q1, #0 -#ifdef XTS_CHAIN_TWEAK - ldr r1, [r3, #0x20+VFP_ABI_FRAME] @ chain tweak -#endif -.Lxts_dec_bzero: @ wipe key schedule [if any] - vstmia sp!, {q0-q1} - cmp sp, r0 - bne .Lxts_dec_bzero - - mov sp, r3 -#ifdef XTS_CHAIN_TWEAK - vst1.8 {q8}, [r1] -#endif - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} @ return - -.size bsaes_xts_decrypt,.-bsaes_xts_decrypt -#endif diff --git a/arch/arm/crypto/aesbs-glue.c b/arch/arm/crypto/aesbs-glue.c deleted file mode 100644 index 4522366..0000000 --- a/arch/arm/crypto/aesbs-glue.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * linux/arch/arm/crypto/aesbs-glue.c - glue code for NEON bit sliced AES - * - * Copyright (C) 2013 Linaro Ltd <ard.biesheuvel@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <asm/neon.h> -#include <crypto/aes.h> -#include <crypto/ablk_helper.h> -#include <crypto/algapi.h> -#include <linux/module.h> - -#include "aes_glue.h" - -#define BIT_SLICED_KEY_MAXSIZE (128 * (AES_MAXNR - 1) + 2 * AES_BLOCK_SIZE) - -struct BS_KEY { - struct AES_KEY rk; - int converted; - u8 __aligned(8) bs[BIT_SLICED_KEY_MAXSIZE]; -} __aligned(8); - -asmlinkage void bsaes_enc_key_convert(u8 out[], struct AES_KEY const *in); -asmlinkage void bsaes_dec_key_convert(u8 out[], struct AES_KEY const *in); - -asmlinkage void bsaes_cbc_encrypt(u8 const in[], u8 out[], u32 bytes, - struct BS_KEY *key, u8 iv[]); - -asmlinkage void bsaes_ctr32_encrypt_blocks(u8 const in[], u8 out[], u32 blocks, - struct BS_KEY *key, u8 const iv[]); - -asmlinkage void bsaes_xts_encrypt(u8 const in[], u8 out[], u32 bytes, - struct BS_KEY *key, u8 tweak[]); - -asmlinkage void bsaes_xts_decrypt(u8 const in[], u8 out[], u32 bytes, - struct BS_KEY *key, u8 tweak[]); - -struct aesbs_cbc_ctx { - struct AES_KEY enc; - struct BS_KEY dec; -}; - -struct aesbs_ctr_ctx { - struct BS_KEY enc; -}; - -struct aesbs_xts_ctx { - struct BS_KEY enc; - struct BS_KEY dec; - struct AES_KEY twkey; -}; - -static int aesbs_cbc_set_key(struct crypto_tfm *tfm, const u8 *in_key, - unsigned int key_len) -{ - struct aesbs_cbc_ctx *ctx = crypto_tfm_ctx(tfm); - int bits = key_len * 8; - - if (private_AES_set_encrypt_key(in_key, bits, &ctx->enc)) { - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; - return -EINVAL; - } - ctx->dec.rk = ctx->enc; - private_AES_set_decrypt_key(in_key, bits, &ctx->dec.rk); - ctx->dec.converted = 0; - return 0; -} - -static int aesbs_ctr_set_key(struct crypto_tfm *tfm, const u8 *in_key, - unsigned int key_len) -{ - struct aesbs_ctr_ctx *ctx = crypto_tfm_ctx(tfm); - int bits = key_len * 8; - - if (private_AES_set_encrypt_key(in_key, bits, &ctx->enc.rk)) { - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; - return -EINVAL; - } - ctx->enc.converted = 0; - return 0; -} - -static int aesbs_xts_set_key(struct crypto_tfm *tfm, const u8 *in_key, - unsigned int key_len) -{ - struct aesbs_xts_ctx *ctx = crypto_tfm_ctx(tfm); - int bits = key_len * 4; - - if (private_AES_set_encrypt_key(in_key, bits, &ctx->enc.rk)) { - tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; - return -EINVAL; - } - ctx->dec.rk = ctx->enc.rk; - private_AES_set_decrypt_key(in_key, bits, &ctx->dec.rk); - private_AES_set_encrypt_key(in_key + key_len / 2, bits, &ctx->twkey); - ctx->enc.converted = ctx->dec.converted = 0; - return 0; -} - -static int aesbs_cbc_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) -{ - struct aesbs_cbc_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; - int err; - - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt(desc, &walk); - - while (walk.nbytes) { - u32 blocks = walk.nbytes / AES_BLOCK_SIZE; - u8 *src = walk.src.virt.addr; - - if (walk.dst.virt.addr == walk.src.virt.addr) { - u8 *iv = walk.iv; - - do { - crypto_xor(src, iv, AES_BLOCK_SIZE); - AES_encrypt(src, src, &ctx->enc); - iv = src; - src += AES_BLOCK_SIZE; - } while (--blocks); - memcpy(walk.iv, iv, AES_BLOCK_SIZE); - } else { - u8 *dst = walk.dst.virt.addr; - - do { - crypto_xor(walk.iv, src, AES_BLOCK_SIZE); - AES_encrypt(walk.iv, dst, &ctx->enc); - memcpy(walk.iv, dst, AES_BLOCK_SIZE); - src += AES_BLOCK_SIZE; - dst += AES_BLOCK_SIZE; - } while (--blocks); - } - err = blkcipher_walk_done(desc, &walk, 0); - } - return err; -} - -static int aesbs_cbc_decrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) -{ - struct aesbs_cbc_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; - int err; - - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); - - while ((walk.nbytes / AES_BLOCK_SIZE) >= 8) { - kernel_neon_begin(); - bsaes_cbc_encrypt(walk.src.virt.addr, walk.dst.virt.addr, - walk.nbytes, &ctx->dec, walk.iv); - kernel_neon_end(); - err = blkcipher_walk_done(desc, &walk, 0); - } - while (walk.nbytes) { - u32 blocks = walk.nbytes / AES_BLOCK_SIZE; - u8 *dst = walk.dst.virt.addr; - u8 *src = walk.src.virt.addr; - u8 bk[2][AES_BLOCK_SIZE]; - u8 *iv = walk.iv; - - do { - if (walk.dst.virt.addr == walk.src.virt.addr) - memcpy(bk[blocks & 1], src, AES_BLOCK_SIZE); - - AES_decrypt(src, dst, &ctx->dec.rk); - crypto_xor(dst, iv, AES_BLOCK_SIZE); - - if (walk.dst.virt.addr == walk.src.virt.addr) - iv = bk[blocks & 1]; - else - iv = src; - - dst += AES_BLOCK_SIZE; - src += AES_BLOCK_SIZE; - } while (--blocks); - err = blkcipher_walk_done(desc, &walk, 0); - } - return err; -} - -static void inc_be128_ctr(__be32 ctr[], u32 addend) -{ - int i; - - for (i = 3; i >= 0; i--, addend = 1) { - u32 n = be32_to_cpu(ctr[i]) + addend; - - ctr[i] = cpu_to_be32(n); - if (n >= addend) - break; - } -} - -static int aesbs_ctr_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, struct scatterlist *src, - unsigned int nbytes) -{ - struct aesbs_ctr_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; - u32 blocks; - int err; - - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); - - while ((blocks = walk.nbytes / AES_BLOCK_SIZE)) { - u32 tail = walk.nbytes % AES_BLOCK_SIZE; - __be32 *ctr = (__be32 *)walk.iv; - u32 headroom = UINT_MAX - be32_to_cpu(ctr[3]); - - /* avoid 32 bit counter overflow in the NEON code */ - if (unlikely(headroom < blocks)) { - blocks = headroom + 1; - tail = walk.nbytes - blocks * AES_BLOCK_SIZE; - } - kernel_neon_begin(); - bsaes_ctr32_encrypt_blocks(walk.src.virt.addr, - walk.dst.virt.addr, blocks, - &ctx->enc, walk.iv); - kernel_neon_end(); - inc_be128_ctr(ctr, blocks); - - nbytes -= blocks * AES_BLOCK_SIZE; - if (nbytes && nbytes == tail && nbytes <= AES_BLOCK_SIZE) - break; - - err = blkcipher_walk_done(desc, &walk, tail); - } - if (walk.nbytes) { - u8 *tdst = walk.dst.virt.addr + blocks * AES_BLOCK_SIZE; - u8 *tsrc = walk.src.virt.addr + blocks * AES_BLOCK_SIZE; - u8 ks[AES_BLOCK_SIZE]; - - AES_encrypt(walk.iv, ks, &ctx->enc.rk); - if (tdst != tsrc) - memcpy(tdst, tsrc, nbytes); - crypto_xor(tdst, ks, nbytes); - err = blkcipher_walk_done(desc, &walk, 0); - } - return err; -} - -static int aesbs_xts_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) -{ - struct aesbs_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; - int err; - - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); - - /* generate the initial tweak */ - AES_encrypt(walk.iv, walk.iv, &ctx->twkey); - - while (walk.nbytes) { - kernel_neon_begin(); - bsaes_xts_encrypt(walk.src.virt.addr, walk.dst.virt.addr, - walk.nbytes, &ctx->enc, walk.iv); - kernel_neon_end(); - err = blkcipher_walk_done(desc, &walk, 0); - } - return err; -} - -static int aesbs_xts_decrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, - struct scatterlist *src, unsigned int nbytes) -{ - struct aesbs_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); - struct blkcipher_walk walk; - int err; - - blkcipher_walk_init(&walk, dst, src, nbytes); - err = blkcipher_walk_virt_block(desc, &walk, 8 * AES_BLOCK_SIZE); - - /* generate the initial tweak */ - AES_encrypt(walk.iv, walk.iv, &ctx->twkey); - - while (walk.nbytes) { - kernel_neon_begin(); - bsaes_xts_decrypt(walk.src.virt.addr, walk.dst.virt.addr, - walk.nbytes, &ctx->dec, walk.iv); - kernel_neon_end(); - err = blkcipher_walk_done(desc, &walk, 0); - } - return err; -} - -static struct crypto_alg aesbs_algs[] = { { - .cra_name = "__cbc-aes-neonbs", - .cra_driver_name = "__driver-cbc-aes-neonbs", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct aesbs_cbc_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = aesbs_cbc_set_key, - .encrypt = aesbs_cbc_encrypt, - .decrypt = aesbs_cbc_decrypt, - }, -}, { - .cra_name = "__ctr-aes-neonbs", - .cra_driver_name = "__driver-ctr-aes-neonbs", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER, - .cra_blocksize = 1, - .cra_ctxsize = sizeof(struct aesbs_ctr_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = aesbs_ctr_set_key, - .encrypt = aesbs_ctr_encrypt, - .decrypt = aesbs_ctr_encrypt, - }, -}, { - .cra_name = "__xts-aes-neonbs", - .cra_driver_name = "__driver-xts-aes-neonbs", - .cra_priority = 0, - .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct aesbs_xts_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_blkcipher_type, - .cra_module = THIS_MODULE, - .cra_blkcipher = { - .min_keysize = 2 * AES_MIN_KEY_SIZE, - .max_keysize = 2 * AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = aesbs_xts_set_key, - .encrypt = aesbs_xts_encrypt, - .decrypt = aesbs_xts_decrypt, - }, -}, { - .cra_name = "cbc(aes)", - .cra_driver_name = "cbc-aes-neonbs", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = __ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "ctr(aes)", - .cra_driver_name = "ctr-aes-neonbs", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = 1, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } -}, { - .cra_name = "xts(aes)", - .cra_driver_name = "xts-aes-neonbs", - .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC, - .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct async_helper_ctx), - .cra_alignmask = 7, - .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = ablk_init, - .cra_exit = ablk_exit, - .cra_ablkcipher = { - .min_keysize = 2 * AES_MIN_KEY_SIZE, - .max_keysize = 2 * AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, - .setkey = ablk_set_key, - .encrypt = ablk_encrypt, - .decrypt = ablk_decrypt, - } -} }; - -static int __init aesbs_mod_init(void) -{ - if (!cpu_has_neon()) - return -ENODEV; - - return crypto_register_algs(aesbs_algs, ARRAY_SIZE(aesbs_algs)); -} - -static void __exit aesbs_mod_exit(void) -{ - crypto_unregister_algs(aesbs_algs, ARRAY_SIZE(aesbs_algs)); -} - -module_init(aesbs_mod_init); -module_exit(aesbs_mod_exit); - -MODULE_DESCRIPTION("Bit sliced AES in CBC/CTR/XTS modes using NEON"); -MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/crypto/bsaes-armv7.pl b/arch/arm/crypto/bsaes-armv7.pl deleted file mode 100644 index f3d96d9..0000000 --- a/arch/arm/crypto/bsaes-armv7.pl +++ /dev/null @@ -1,2467 +0,0 @@ -#!/usr/bin/env perl - -# ==================================================================== -# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL -# project. The module is, however, dual licensed under OpenSSL and -# CRYPTOGAMS licenses depending on where you obtain it. For further -# details see http://www.openssl.org/~appro/cryptogams/. -# -# Specific modes and adaptation for Linux kernel by Ard Biesheuvel -# <ard.biesheuvel@linaro.org>. Permission to use under GPL terms is -# granted. -# ==================================================================== - -# Bit-sliced AES for ARM NEON -# -# February 2012. -# -# This implementation is direct adaptation of bsaes-x86_64 module for -# ARM NEON. Except that this module is endian-neutral [in sense that -# it can be compiled for either endianness] by courtesy of vld1.8's -# neutrality. Initial version doesn't implement interface to OpenSSL, -# only low-level primitives and unsupported entry points, just enough -# to collect performance results, which for Cortex-A8 core are: -# -# encrypt 19.5 cycles per byte processed with 128-bit key -# decrypt 22.1 cycles per byte processed with 128-bit key -# key conv. 440 cycles per 128-bit key/0.18 of 8x block -# -# Snapdragon S4 encrypts byte in 17.6 cycles and decrypts in 19.7, -# which is [much] worse than anticipated (for further details see -# http://www.openssl.org/~appro/Snapdragon-S4.html). -# -# Cortex-A15 manages in 14.2/16.1 cycles [when integer-only code -# manages in 20.0 cycles]. -# -# When comparing to x86_64 results keep in mind that NEON unit is -# [mostly] single-issue and thus can't [fully] benefit from -# instruction-level parallelism. And when comparing to aes-armv4 -# results keep in mind key schedule conversion overhead (see -# bsaes-x86_64.pl for further details)... -# -# <appro@openssl.org> - -# April-August 2013 -# -# Add CBC, CTR and XTS subroutines, adapt for kernel use. -# -# <ard.biesheuvel@linaro.org> - -while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {} -open STDOUT,">$output"; - -my ($inp,$out,$len,$key)=("r0","r1","r2","r3"); -my @XMM=map("q$_",(0..15)); - -{ -my ($key,$rounds,$const)=("r4","r5","r6"); - -sub Dlo() { shift=~m|q([1]?[0-9])|?"d".($1*2):""; } -sub Dhi() { shift=~m|q([1]?[0-9])|?"d".($1*2+1):""; } - -sub Sbox { -# input in lsb > [b0, b1, b2, b3, b4, b5, b6, b7] < msb -# output in lsb > [b0, b1, b4, b6, b3, b7, b2, b5] < msb -my @b=@_[0..7]; -my @t=@_[8..11]; -my @s=@_[12..15]; - &InBasisChange (@b); - &Inv_GF256 (@b[6,5,0,3,7,1,4,2],@t,@s); - &OutBasisChange (@b[7,1,4,2,6,5,0,3]); -} - -sub InBasisChange { -# input in lsb > [b0, b1, b2, b3, b4, b5, b6, b7] < msb -# output in lsb > [b6, b5, b0, b3, b7, b1, b4, b2] < msb -my @b=@_[0..7]; -$code.=<<___; - veor @b[2], @b[2], @b[1] - veor @b[5], @b[5], @b[6] - veor @b[3], @b[3], @b[0] - veor @b[6], @b[6], @b[2] - veor @b[5], @b[5], @b[0] - - veor @b[6], @b[6], @b[3] - veor @b[3], @b[3], @b[7] - veor @b[7], @b[7], @b[5] - veor @b[3], @b[3], @b[4] - veor @b[4], @b[4], @b[5] - - veor @b[2], @b[2], @b[7] - veor @b[3], @b[3], @b[1] - veor @b[1], @b[1], @b[5] -___ -} - -sub OutBasisChange { -# input in lsb > [b0, b1, b2, b3, b4, b5, b6, b7] < msb -# output in lsb > [b6, b1, b2, b4, b7, b0, b3, b5] < msb -my @b=@_[0..7]; -$code.=<<___; - veor @b[0], @b[0], @b[6] - veor @b[1], @b[1], @b[4] - veor @b[4], @b[4], @b[6] - veor @b[2], @b[2], @b[0] - veor @b[6], @b[6], @b[1] - - veor @b[1], @b[1], @b[5] - veor @b[5], @b[5], @b[3] - veor @b[3], @b[3], @b[7] - veor @b[7], @b[7], @b[5] - veor @b[2], @b[2], @b[5] - - veor @b[4], @b[4], @b[7] -___ -} - -sub InvSbox { -# input in lsb > [b0, b1, b2, b3, b4, b5, b6, b7] < msb -# output in lsb > [b0, b1, b6, b4, b2, b7, b3, b5] < msb -my @b=@_[0..7]; -my @t=@_[8..11]; -my @s=@_[12..15]; - &InvInBasisChange (@b); - &Inv_GF256 (@b[5,1,2,6,3,7,0,4],@t,@s); - &InvOutBasisChange (@b[3,7,0,4,5,1,2,6]); -} - -sub InvInBasisChange { # OutBasisChange in reverse (with twist) -my @b=@_[5,1,2,6,3,7,0,4]; -$code.=<<___ - veor @b[1], @b[1], @b[7] - veor @b[4], @b[4], @b[7] - - veor @b[7], @b[7], @b[5] - veor @b[1], @b[1], @b[3] - veor @b[2], @b[2], @b[5] - veor @b[3], @b[3], @b[7] - - veor @b[6], @b[6], @b[1] - veor @b[2], @b[2], @b[0] - veor @b[5], @b[5], @b[3] - veor @b[4], @b[4], @b[6] - veor @b[0], @b[0], @b[6] - veor @b[1], @b[1], @b[4] -___ -} - -sub InvOutBasisChange { # InBasisChange in reverse -my @b=@_[2,5,7,3,6,1,0,4]; -$code.=<<___; - veor @b[1], @b[1], @b[5] - veor @b[2], @b[2], @b[7] - - veor @b[3], @b[3], @b[1] - veor @b[4], @b[4], @b[5] - veor @b[7], @b[7], @b[5] - veor @b[3], @b[3], @b[4] - veor @b[5], @b[5], @b[0] - veor @b[3], @b[3], @b[7] - veor @b[6], @b[6], @b[2] - veor @b[2], @b[2], @b[1] - veor @b[6], @b[6], @b[3] - - veor @b[3], @b[3], @b[0] - veor @b[5], @b[5], @b[6] -___ -} - -sub Mul_GF4 { -#;************************************************************* -#;* Mul_GF4: Input x0-x1,y0-y1 Output x0-x1 Temp t0 (8) * -#;************************************************************* -my ($x0,$x1,$y0,$y1,$t0,$t1)=@_; -$code.=<<___; - veor $t0, $y0, $y1 - vand $t0, $t0, $x0 - veor $x0, $x0, $x1 - vand $t1, $x1, $y0 - vand $x0, $x0, $y1 - veor $x1, $t1, $t0 - veor $x0, $x0, $t1 -___ -} - -sub Mul_GF4_N { # not used, see next subroutine -# multiply and scale by N -my ($x0,$x1,$y0,$y1,$t0)=@_; -$code.=<<___; - veor $t0, $y0, $y1 - vand $t0, $t0, $x0 - veor $x0, $x0, $x1 - vand $x1, $x1, $y0 - vand $x0, $x0, $y1 - veor $x1, $x1, $x0 - veor $x0, $x0, $t0 -___ -} - -sub Mul_GF4_N_GF4 { -# interleaved Mul_GF4_N and Mul_GF4 -my ($x0,$x1,$y0,$y1,$t0, - $x2,$x3,$y2,$y3,$t1)=@_; -$code.=<<___; - veor $t0, $y0, $y1 - veor $t1, $y2, $y3 - vand $t0, $t0, $x0 - vand $t1, $t1, $x2 - veor $x0, $x0, $x1 - veor $x2, $x2, $x3 - vand $x1, $x1, $y0 - vand $x3, $x3, $y2 - vand $x0, $x0, $y1 - vand $x2, $x2, $y3 - veor $x1, $x1, $x0 - veor $x2, $x2, $x3 - veor $x0, $x0, $t0 - veor $x3, $x3, $t1 -___ -} -sub Mul_GF16_2 { -my @x=@_[0..7]; -my @y=@_[8..11]; -my @t=@_[12..15]; -$code.=<<___; - veor @t[0], @x[0], @x[2] - veor @t[1], @x[1], @x[3] -___ - &Mul_GF4 (@x[0], @x[1], @y[0], @y[1], @t[2..3]); -$code.=<<___; - veor @y[0], @y[0], @y[2] - veor @y[1], @y[1], @y[3] -___ - Mul_GF4_N_GF4 (@t[0], @t[1], @y[0], @y[1], @t[3], - @x[2], @x[3], @y[2], @y[3], @t[2]); -$code.=<<___; - veor @x[0], @x[0], @t[0] - veor @x[2], @x[2], @t[0] - veor @x[1], @x[1], @t[1] - veor @x[3], @x[3], @t[1] - - veor @t[0], @x[4], @x[6] - veor @t[1], @x[5], @x[7] -___ - &Mul_GF4_N_GF4 (@t[0], @t[1], @y[0], @y[1], @t[3], - @x[6], @x[7], @y[2], @y[3], @t[2]); -$code.=<<___; - veor @y[0], @y[0], @y[2] - veor @y[1], @y[1], @y[3] -___ - &Mul_GF4 (@x[4], @x[5], @y[0], @y[1], @t[2..3]); -$code.=<<___; - veor @x[4], @x[4], @t[0] - veor @x[6], @x[6], @t[0] - veor @x[5], @x[5], @t[1] - veor @x[7], @x[7], @t[1] -___ -} -sub Inv_GF256 { -#;******************************************************************** -#;* Inv_GF256: Input x0-x7 Output x0-x7 Temp t0-t3,s0-s3 (144) * -#;******************************************************************** -my @x=@_[0..7]; -my @t=@_[8..11]; -my @s=@_[12..15]; -# direct optimizations from hardware -$code.=<<___; - veor @t[3], @x[4], @x[6] - veor @t[2], @x[5], @x[7] - veor @t[1], @x[1], @x[3] - veor @s[1], @x[7], @x[6] - vmov @t[0], @t[2] - veor @s[0], @x[0], @x[2] - - vorr @t[2], @t[2], @t[1] - veor @s[3], @t[3], @t[0] - vand @s[2], @t[3], @s[0] - vorr @t[3], @t[3], @s[0] - veor @s[0], @s[0], @t[1] - vand @t[0], @t[0], @t[1] - veor @t[1], @x[3], @x[2] - vand @s[3], @s[3], @s[0] - vand @s[1], @s[1], @t[1] - veor @t[1], @x[4], @x[5] - veor @s[0], @x[1], @x[0] - veor @t[3], @t[3], @s[1] - veor @t[2], @t[2], @s[1] - vand @s[1], @t[1], @s[0] - vorr @t[1], @t[1], @s[0] - veor @t[3], @t[3], @s[3] - veor @t[0], @t[0], @s[1] - veor @t[2], @t[2], @s[2] - veor @t[1], @t[1], @s[3] - veor @t[0], @t[0], @s[2] - vand @s[0], @x[7], @x[3] - veor @t[1], @t[1], @s[2] - vand @s[1], @x[6], @x[2] - vand @s[2], @x[5], @x[1] - vorr @s[3], @x[4], @x[0] - veor @t[3], @t[3], @s[0] - veor @t[1], @t[1], @s[2] - veor @t[0], @t[0], @s[3] - veor @t[2], @t[2], @s[1] - - @ Inv_GF16 \t0, \t1, \t2, \t3, \s0, \s1, \s2, \s3 - - @ new smaller inversion - - vand @s[2], @t[3], @t[1] - vmov @s[0], @t[0] - - veor @s[1], @t[2], @s[2] - veor @s[3], @t[0], @s[2] - veor @s[2], @t[0], @s[2] @ @s[2]=@s[3] - - vbsl @s[1], @t[1], @t[0] - vbsl @s[3], @t[3], @t[2] - veor @t[3], @t[3], @t[2] - - vbsl @s[0], @s[1], @s[2] - vbsl @t[0], @s[2], @s[1] - - vand @s[2], @s[0], @s[3] - veor @t[1], @t[1], @t[0] - - veor @s[2], @s[2], @t[3] -___ -# output in s3, s2, s1, t1 - -# Mul_GF16_2 \x0, \x1, \x2, \x3, \x4, \x5, \x6, \x7, \t2, \t3, \t0, \t1, \s0, \s1, \s2, \s3 - -# Mul_GF16_2 \x0, \x1, \x2, \x3, \x4, \x5, \x6, \x7, \s3, \s2, \s1, \t1, \s0, \t0, \t2, \t3 - &Mul_GF16_2(@x,@s[3,2,1],@t[1],@s[0],@t[0,2,3]); - -### output msb > [x3,x2,x1,x0,x7,x6,x5,x4] < lsb -} - -# AES linear components - -sub ShiftRows { -my @x=@_[0..7]; -my @t=@_[8..11]; -my $mask=pop; -$code.=<<___; - vldmia $key!, {@t[0]-@t[3]} - veor @t[0], @t[0], @x[0] - veor @t[1], @t[1], @x[1] - vtbl.8 `&Dlo(@x[0])`, {@t[0]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[0])`, {@t[0]}, `&Dhi($mask)` - vldmia $key!, {@t[0]} - veor @t[2], @t[2], @x[2] - vtbl.8 `&Dlo(@x[1])`, {@t[1]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[1])`, {@t[1]}, `&Dhi($mask)` - vldmia $key!, {@t[1]} - veor @t[3], @t[3], @x[3] - vtbl.8 `&Dlo(@x[2])`, {@t[2]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[2])`, {@t[2]}, `&Dhi($mask)` - vldmia $key!, {@t[2]} - vtbl.8 `&Dlo(@x[3])`, {@t[3]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[3])`, {@t[3]}, `&Dhi($mask)` - vldmia $key!, {@t[3]} - veor @t[0], @t[0], @x[4] - veor @t[1], @t[1], @x[5] - vtbl.8 `&Dlo(@x[4])`, {@t[0]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[4])`, {@t[0]}, `&Dhi($mask)` - veor @t[2], @t[2], @x[6] - vtbl.8 `&Dlo(@x[5])`, {@t[1]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[5])`, {@t[1]}, `&Dhi($mask)` - veor @t[3], @t[3], @x[7] - vtbl.8 `&Dlo(@x[6])`, {@t[2]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[6])`, {@t[2]}, `&Dhi($mask)` - vtbl.8 `&Dlo(@x[7])`, {@t[3]}, `&Dlo($mask)` - vtbl.8 `&Dhi(@x[7])`, {@t[3]}, `&Dhi($mask)` -___ -} - -sub MixColumns { -# modified to emit output in order suitable for feeding back to aesenc[last] -my @x=@_[0..7]; -my @t=@_[8..15]; -my $inv=@_[16]; # optional -$code.=<<___; - vext.8 @t[0], @x[0], @x[0], #12 @ x0 <<< 32 - vext.8 @t[1], @x[1], @x[1], #12 - veor @x[0], @x[0], @t[0] @ x0 ^ (x0 <<< 32) - vext.8 @t[2], @x[2], @x[2], #12 - veor @x[1], @x[1], @t[1] - vext.8 @t[3], @x[3], @x[3], #12 - veor @x[2], @x[2], @t[2] - vext.8 @t[4], @x[4], @x[4], #12 - veor @x[3], @x[3], @t[3] - vext.8 @t[5], @x[5], @x[5], #12 - veor @x[4], @x[4], @t[4] - vext.8 @t[6], @x[6], @x[6], #12 - veor @x[5], @x[5], @t[5] - vext.8 @t[7], @x[7], @x[7], #12 - veor @x[6], @x[6], @t[6] - - veor @t[1], @t[1], @x[0] - veor @x[7], @x[7], @t[7] - vext.8 @x[0], @x[0], @x[0], #8 @ (x0 ^ (x0 <<< 32)) <<< 64) - veor @t[2], @t[2], @x[1] - veor @t[0], @t[0], @x[7] - veor @t[1], @t[1], @x[7] - vext.8 @x[1], @x[1], @x[1], #8 - veor @t[5], @t[5], @x[4] - veor @x[0], @x[0], @t[0] - veor @t[6], @t[6], @x[5] - veor @x[1], @x[1], @t[1] - vext.8 @t[0], @x[4], @x[4], #8 - veor @t[4], @t[4], @x[3] - vext.8 @t[1], @x[5], @x[5], #8 - veor @t[7], @t[7], @x[6] - vext.8 @x[4], @x[3], @x[3], #8 - veor @t[3], @t[3], @x[2] - vext.8 @x[5], @x[7], @x[7], #8 - veor @t[4], @t[4], @x[7] - vext.8 @x[3], @x[6], @x[6], #8 - veor @t[3], @t[3], @x[7] - vext.8 @x[6], @x[2], @x[2], #8 - veor @x[7], @t[1], @t[5] -___ -$code.=<<___ if (!$inv); - veor @x[2], @t[0], @t[4] - veor @x[4], @x[4], @t[3] - veor @x[5], @x[5], @t[7] - veor @x[3], @x[3], @t[6] - @ vmov @x[2], @t[0] - veor @x[6], @x[6], @t[2] - @ vmov @x[7], @t[1] -___ -$code.=<<___ if ($inv); - veor @t[3], @t[3], @x[4] - veor @x[5], @x[5], @t[7] - veor @x[2], @x[3], @t[6] - veor @x[3], @t[0], @t[4] - veor @x[4], @x[6], @t[2] - vmov @x[6], @t[3] - @ vmov @x[7], @t[1] -___ -} - -sub InvMixColumns_orig { -my @x=@_[0..7]; -my @t=@_[8..15]; - -$code.=<<___; - @ multiplication by 0x0e - vext.8 @t[7], @x[7], @x[7], #12 - vmov @t[2], @x[2] - veor @x[2], @x[2], @x[5] @ 2 5 - veor @x[7], @x[7], @x[5] @ 7 5 - vext.8 @t[0], @x[0], @x[0], #12 - vmov @t[5], @x[5] - veor @x[5], @x[5], @x[0] @ 5 0 [1] - veor @x[0], @x[0], @x[1] @ 0 1 - vext.8 @t[1], @x[1], @x[1], #12 - veor @x[1], @x[1], @x[2] @ 1 25 - veor @x[0], @x[0], @x[6] @ 01 6 [2] - vext.8 @t[3], @x[3], @x[3], #12 - veor @x[1], @x[1], @x[3] @ 125 3 [4] - veor @x[2], @x[2], @x[0] @ 25 016 [3] - veor @x[3], @x[3], @x[7] @ 3 75 - veor @x[7], @x[7], @x[6] @ 75 6 [0] - vext.8 @t[6], @x[6], @x[6], #12 - vmov @t[4], @x[4] - veor @x[6], @x[6], @x[4] @ 6 4 - veor @x[4], @x[4], @x[3] @ 4 375 [6] - veor @x[3], @x[3], @x[7] @ 375 756=36 - veor @x[6], @x[6], @t[5] @ 64 5 [7] - veor @x[3], @x[3], @t[2] @ 36 2 - vext.8 @t[5], @t[5], @t[5], #12 - veor @x[3], @x[3], @t[4] @ 362 4 [5] -___ - my @y = @x[7,5,0,2,1,3,4,6]; -$code.=<<___; - @ multiplication by 0x0b - veor @y[1], @y[1], @y[0] - veor @y[0], @y[0], @t[0] - vext.8 @t[2], @t[2], @t[2], #12 - veor @y[1], @y[1], @t[1] - veor @y[0], @y[0], @t[5] - vext.8 @t[4], @t[4], @t[4], #12 - veor @y[1], @y[1], @t[6] - veor @y[0], @y[0], @t[7] - veor @t[7], @t[7], @t[6] @ clobber t[7] - - veor @y[3], @y[3], @t[0] - veor @y[1], @y[1], @y[0] - vext.8 @t[0], @t[0], @t[0], #12 - veor @y[2], @y[2], @t[1] - veor @y[4], @y[4], @t[1] - vext.8 @t[1], @t[1], @t[1], #12 - veor @y[2], @y[2], @t[2] - veor @y[3], @y[3], @t[2] - veor @y[5], @y[5], @t[2] - veor @y[2], @y[2], @t[7] - vext.8 @t[2], @t[2], @t[2], #12 - veor @y[3], @y[3], @t[3] - veor @y[6], @y[6], @t[3] - veor @y[4], @y[4], @t[3] - veor @y[7], @y[7], @t[4] - vext.8 @t[3], @t[3], @t[3], #12 - veor @y[5], @y[5], @t[4] - veor @y[7], @y[7], @t[7] - veor @t[7], @t[7], @t[5] @ clobber t[7] even more - veor @y[3], @y[3], @t[5] - veor @y[4], @y[4], @t[4] - - veor @y[5], @y[5], @t[7] - vext.8 @t[4], @t[4], @t[4], #12 - veor @y[6], @y[6], @t[7] - veor @y[4], @y[4], @t[7] - - veor @t[7], @t[7], @t[5] - vext.8 @t[5], @t[5], @t[5], #12 - - @ multiplication by 0x0d - veor @y[4], @y[4], @y[7] - veor @t[7], @t[7], @t[6] @ restore t[7] - veor @y[7], @y[7], @t[4] - vext.8 @t[6], @t[6], @t[6], #12 - veor @y[2], @y[2], @t[0] - veor @y[7], @y[7], @t[5] - vext.8 @t[7], @t[7], @t[7], #12 - veor @y[2], @y[2], @t[2] - - veor @y[3], @y[3], @y[1] - veor @y[1], @y[1], @t[1] - veor @y[0], @y[0], @t[0] - veor @y[3], @y[3], @t[0] - veor @y[1], @y[1], @t[5] - veor @y[0], @y[0], @t[5] - vext.8 @t[0], @t[0], @t[0], #12 - veor @y[1], @y[1], @t[7] - veor @y[0], @y[0], @t[6] - veor @y[3], @y[3], @y[1] - veor @y[4], @y[4], @t[1] - vext.8 @t[1], @t[1], @t[1], #12 - - veor @y[7], @y[7], @t[7] - veor @y[4], @y[4], @t[2] - veor @y[5], @y[5], @t[2] - veor @y[2], @y[2], @t[6] - veor @t[6], @t[6], @t[3] @ clobber t[6] - vext.8 @t[2], @t[2], @t[2], #12 - veor @y[4], @y[4], @y[7] - veor @y[3], @y[3], @t[6] - - veor @y[6], @y[6], @t[6] - veor @y[5], @y[5], @t[5] - vext.8 @t[5], @t[5], @t[5], #12 - veor @y[6], @y[6], @t[4] - vext.8 @t[4], @t[4], @t[4], #12 - veor @y[5], @y[5], @t[6] - veor @y[6], @y[6], @t[7] - vext.8 @t[7], @t[7], @t[7], #12 - veor @t[6], @t[6], @t[3] @ restore t[6] - vext.8 @t[3], @t[3], @t[3], #12 - - @ multiplication by 0x09 - veor @y[4], @y[4], @y[1] - veor @t[1], @t[1], @y[1] @ t[1]=y[1] - veor @t[0], @t[0], @t[5] @ clobber t[0] - vext.8 @t[6], @t[6], @t[6], #12 - veor @t[1], @t[1], @t[5] - veor @y[3], @y[3], @t[0] - veor @t[0], @t[0], @y[0] @ t[0]=y[0] - veor @t[1], @t[1], @t[6] - veor @t[6], @t[6], @t[7] @ clobber t[6] - veor @y[4], @y[4], @t[1] - veor @y[7], @y[7], @t[4] - veor @y[6], @y[6], @t[3] - veor @y[5], @y[5], @t[2] - veor @t[4], @t[4], @y[4] @ t[4]=y[4] - veor @t[3], @t[3], @y[3] @ t[3]=y[3] - veor @t[5], @t[5], @y[5] @ t[5]=y[5] - veor @t[2], @t[2], @y[2] @ t[2]=y[2] - veor @t[3], @t[3], @t[7] - veor @XMM[5], @t[5], @t[6] - veor @XMM[6], @t[6], @y[6] @ t[6]=y[6] - veor @XMM[2], @t[2], @t[6] - veor @XMM[7], @t[7], @y[7] @ t[7]=y[7] - - vmov @XMM[0], @t[0] - vmov @XMM[1], @t[1] - @ vmov @XMM[2], @t[2] - vmov @XMM[3], @t[3] - vmov @XMM[4], @t[4] - @ vmov @XMM[5], @t[5] - @ vmov @XMM[6], @t[6] - @ vmov @XMM[7], @t[7] -___ -} - -sub InvMixColumns { -my @x=@_[0..7]; -my @t=@_[8..15]; - -# Thanks to Jussi Kivilinna for providing pointer to -# -# | 0e 0b 0d 09 | | 02 03 01 01 | | 05 00 04 00 | -# | 09 0e 0b 0d | = | 01 02 03 01 | x | 00 05 00 04 | -# | 0d 09 0e 0b | | 01 01 02 03 | | 04 00 05 00 | -# | 0b 0d 09 0e | | 03 01 01 02 | | 00 04 00 05 | - -$code.=<<___; - @ multiplication by 0x05-0x00-0x04-0x00 - vext.8 @t[0], @x[0], @x[0], #8 - vext.8 @t[6], @x[6], @x[6], #8 - vext.8 @t[7], @x[7], @x[7], #8 - veor @t[0], @t[0], @x[0] - vext.8 @t[1], @x[1], @x[1], #8 - veor @t[6], @t[6], @x[6] - vext.8 @t[2], @x[2], @x[2], #8 - veor @t[7], @t[7], @x[7] - vext.8 @t[3], @x[3], @x[3], #8 - veor @t[1], @t[1], @x[1] - vext.8 @t[4], @x[4], @x[4], #8 - veor @t[2], @t[2], @x[2] - vext.8 @t[5], @x[5], @x[5], #8 - veor @t[3], @t[3], @x[3] - veor @t[4], @t[4], @x[4] - veor @t[5], @t[5], @x[5] - - veor @x[0], @x[0], @t[6] - veor @x[1], @x[1], @t[6] - veor @x[2], @x[2], @t[0] - veor @x[4], @x[4], @t[2] - veor @x[3], @x[3], @t[1] - veor @x[1], @x[1], @t[7] - veor @x[2], @x[2], @t[7] - veor @x[4], @x[4], @t[6] - veor @x[5], @x[5], @t[3] - veor @x[3], @x[3], @t[6] - veor @x[6], @x[6], @t[4] - veor @x[4], @x[4], @t[7] - veor @x[5], @x[5], @t[7] - veor @x[7], @x[7], @t[5] -___ - &MixColumns (@x,@t,1); # flipped 2<->3 and 4<->6 -} - -sub swapmove { -my ($a,$b,$n,$mask,$t)=@_; -$code.=<<___; - vshr.u64 $t, $b, #$n - veor $t, $t, $a - vand $t, $t, $mask - veor $a, $a, $t - vshl.u64 $t, $t, #$n - veor $b, $b, $t -___ -} -sub swapmove2x { -my ($a0,$b0,$a1,$b1,$n,$mask,$t0,$t1)=@_; -$code.=<<___; - vshr.u64 $t0, $b0, #$n - vshr.u64 $t1, $b1, #$n - veor $t0, $t0, $a0 - veor $t1, $t1, $a1 - vand $t0, $t0, $mask - vand $t1, $t1, $mask - veor $a0, $a0, $t0 - vshl.u64 $t0, $t0, #$n - veor $a1, $a1, $t1 - vshl.u64 $t1, $t1, #$n - veor $b0, $b0, $t0 - veor $b1, $b1, $t1 -___ -} - -sub bitslice { -my @x=reverse(@_[0..7]); -my ($t0,$t1,$t2,$t3)=@_[8..11]; -$code.=<<___; - vmov.i8 $t0,#0x55 @ compose .LBS0 - vmov.i8 $t1,#0x33 @ compose .LBS1 -___ - &swapmove2x(@x[0,1,2,3],1,$t0,$t2,$t3); - &swapmove2x(@x[4,5,6,7],1,$t0,$t2,$t3); -$code.=<<___; - vmov.i8 $t0,#0x0f @ compose .LBS2 -___ - &swapmove2x(@x[0,2,1,3],2,$t1,$t2,$t3); - &swapmove2x(@x[4,6,5,7],2,$t1,$t2,$t3); - - &swapmove2x(@x[0,4,1,5],4,$t0,$t2,$t3); - &swapmove2x(@x[2,6,3,7],4,$t0,$t2,$t3); -} - -$code.=<<___; -#ifndef __KERNEL__ -# include "arm_arch.h" - -# define VFP_ABI_PUSH vstmdb sp!,{d8-d15} -# define VFP_ABI_POP vldmia sp!,{d8-d15} -# define VFP_ABI_FRAME 0x40 -#else -# define VFP_ABI_PUSH -# define VFP_ABI_POP -# define VFP_ABI_FRAME 0 -# define BSAES_ASM_EXTENDED_KEY -# define XTS_CHAIN_TWEAK -# define __ARM_ARCH__ __LINUX_ARM_ARCH__ -#endif - -#ifdef __thumb__ -# define adrl adr -#endif - -#if __ARM_ARCH__>=7 -.text -.syntax unified @ ARMv7-capable assembler is expected to handle this -#ifdef __thumb2__ -.thumb -#else -.code 32 -#endif - -.fpu neon - -.type _bsaes_decrypt8,%function -.align 4 -_bsaes_decrypt8: - adr $const,_bsaes_decrypt8 - vldmia $key!, {@XMM[9]} @ round 0 key - add $const,$const,#.LM0ISR-_bsaes_decrypt8 - - vldmia $const!, {@XMM[8]} @ .LM0ISR - veor @XMM[10], @XMM[0], @XMM[9] @ xor with round0 key - veor @XMM[11], @XMM[1], @XMM[9] - vtbl.8 `&Dlo(@XMM[0])`, {@XMM[10]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[0])`, {@XMM[10]}, `&Dhi(@XMM[8])` - veor @XMM[12], @XMM[2], @XMM[9] - vtbl.8 `&Dlo(@XMM[1])`, {@XMM[11]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[1])`, {@XMM[11]}, `&Dhi(@XMM[8])` - veor @XMM[13], @XMM[3], @XMM[9] - vtbl.8 `&Dlo(@XMM[2])`, {@XMM[12]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[2])`, {@XMM[12]}, `&Dhi(@XMM[8])` - veor @XMM[14], @XMM[4], @XMM[9] - vtbl.8 `&Dlo(@XMM[3])`, {@XMM[13]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[3])`, {@XMM[13]}, `&Dhi(@XMM[8])` - veor @XMM[15], @XMM[5], @XMM[9] - vtbl.8 `&Dlo(@XMM[4])`, {@XMM[14]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[4])`, {@XMM[14]}, `&Dhi(@XMM[8])` - veor @XMM[10], @XMM[6], @XMM[9] - vtbl.8 `&Dlo(@XMM[5])`, {@XMM[15]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[5])`, {@XMM[15]}, `&Dhi(@XMM[8])` - veor @XMM[11], @XMM[7], @XMM[9] - vtbl.8 `&Dlo(@XMM[6])`, {@XMM[10]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[6])`, {@XMM[10]}, `&Dhi(@XMM[8])` - vtbl.8 `&Dlo(@XMM[7])`, {@XMM[11]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[7])`, {@XMM[11]}, `&Dhi(@XMM[8])` -___ - &bitslice (@XMM[0..7, 8..11]); -$code.=<<___; - sub $rounds,$rounds,#1 - b .Ldec_sbox -.align 4 -.Ldec_loop: -___ - &ShiftRows (@XMM[0..7, 8..12]); -$code.=".Ldec_sbox:\n"; - &InvSbox (@XMM[0..7, 8..15]); -$code.=<<___; - subs $rounds,$rounds,#1 - bcc .Ldec_done -___ - &InvMixColumns (@XMM[0,1,6,4,2,7,3,5, 8..15]); -$code.=<<___; - vldmia $const, {@XMM[12]} @ .LISR - ite eq @ Thumb2 thing, sanity check in ARM - addeq $const,$const,#0x10 - bne .Ldec_loop - vldmia $const, {@XMM[12]} @ .LISRM0 - b .Ldec_loop -.align 4 -.Ldec_done: -___ - &bitslice (@XMM[0,1,6,4,2,7,3,5, 8..11]); -$code.=<<___; - vldmia $key, {@XMM[8]} @ last round key - veor @XMM[6], @XMM[6], @XMM[8] - veor @XMM[4], @XMM[4], @XMM[8] - veor @XMM[2], @XMM[2], @XMM[8] - veor @XMM[7], @XMM[7], @XMM[8] - veor @XMM[3], @XMM[3], @XMM[8] - veor @XMM[5], @XMM[5], @XMM[8] - veor @XMM[0], @XMM[0], @XMM[8] - veor @XMM[1], @XMM[1], @XMM[8] - bx lr -.size _bsaes_decrypt8,.-_bsaes_decrypt8 - -.type _bsaes_const,%object -.align 6 -_bsaes_const: -.LM0ISR: @ InvShiftRows constants - .quad 0x0a0e0206070b0f03, 0x0004080c0d010509 -.LISR: - .quad 0x0504070602010003, 0x0f0e0d0c080b0a09 -.LISRM0: - .quad 0x01040b0e0205080f, 0x0306090c00070a0d -.LM0SR: @ ShiftRows constants - .quad 0x0a0e02060f03070b, 0x0004080c05090d01 -.LSR: - .quad 0x0504070600030201, 0x0f0e0d0c0a09080b -.LSRM0: - .quad 0x0304090e00050a0f, 0x01060b0c0207080d -.LM0: - .quad 0x02060a0e03070b0f, 0x0004080c0105090d -.LREVM0SR: - .quad 0x090d01050c000408, 0x03070b0f060a0e02 -.asciz "Bit-sliced AES for NEON, CRYPTOGAMS by <appro\@openssl.org>" -.align 6 -.size _bsaes_const,.-_bsaes_const - -.type _bsaes_encrypt8,%function -.align 4 -_bsaes_encrypt8: - adr $const,_bsaes_encrypt8 - vldmia $key!, {@XMM[9]} @ round 0 key - sub $const,$const,#_bsaes_encrypt8-.LM0SR - - vldmia $const!, {@XMM[8]} @ .LM0SR -_bsaes_encrypt8_alt: - veor @XMM[10], @XMM[0], @XMM[9] @ xor with round0 key - veor @XMM[11], @XMM[1], @XMM[9] - vtbl.8 `&Dlo(@XMM[0])`, {@XMM[10]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[0])`, {@XMM[10]}, `&Dhi(@XMM[8])` - veor @XMM[12], @XMM[2], @XMM[9] - vtbl.8 `&Dlo(@XMM[1])`, {@XMM[11]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[1])`, {@XMM[11]}, `&Dhi(@XMM[8])` - veor @XMM[13], @XMM[3], @XMM[9] - vtbl.8 `&Dlo(@XMM[2])`, {@XMM[12]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[2])`, {@XMM[12]}, `&Dhi(@XMM[8])` - veor @XMM[14], @XMM[4], @XMM[9] - vtbl.8 `&Dlo(@XMM[3])`, {@XMM[13]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[3])`, {@XMM[13]}, `&Dhi(@XMM[8])` - veor @XMM[15], @XMM[5], @XMM[9] - vtbl.8 `&Dlo(@XMM[4])`, {@XMM[14]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[4])`, {@XMM[14]}, `&Dhi(@XMM[8])` - veor @XMM[10], @XMM[6], @XMM[9] - vtbl.8 `&Dlo(@XMM[5])`, {@XMM[15]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[5])`, {@XMM[15]}, `&Dhi(@XMM[8])` - veor @XMM[11], @XMM[7], @XMM[9] - vtbl.8 `&Dlo(@XMM[6])`, {@XMM[10]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[6])`, {@XMM[10]}, `&Dhi(@XMM[8])` - vtbl.8 `&Dlo(@XMM[7])`, {@XMM[11]}, `&Dlo(@XMM[8])` - vtbl.8 `&Dhi(@XMM[7])`, {@XMM[11]}, `&Dhi(@XMM[8])` -_bsaes_encrypt8_bitslice: -___ - &bitslice (@XMM[0..7, 8..11]); -$code.=<<___; - sub $rounds,$rounds,#1 - b .Lenc_sbox -.align 4 -.Lenc_loop: -___ - &ShiftRows (@XMM[0..7, 8..12]); -$code.=".Lenc_sbox:\n"; - &Sbox (@XMM[0..7, 8..15]); -$code.=<<___; - subs $rounds,$rounds,#1 - bcc .Lenc_done -___ - &MixColumns (@XMM[0,1,4,6,3,7,2,5, 8..15]); -$code.=<<___; - vldmia $const, {@XMM[12]} @ .LSR - ite eq @ Thumb2 thing, samity check in ARM - addeq $const,$const,#0x10 - bne .Lenc_loop - vldmia $const, {@XMM[12]} @ .LSRM0 - b .Lenc_loop -.align 4 -.Lenc_done: -___ - # output in lsb > [t0, t1, t4, t6, t3, t7, t2, t5] < msb - &bitslice (@XMM[0,1,4,6,3,7,2,5, 8..11]); -$code.=<<___; - vldmia $key, {@XMM[8]} @ last round key - veor @XMM[4], @XMM[4], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[8] - veor @XMM[3], @XMM[3], @XMM[8] - veor @XMM[7], @XMM[7], @XMM[8] - veor @XMM[2], @XMM[2], @XMM[8] - veor @XMM[5], @XMM[5], @XMM[8] - veor @XMM[0], @XMM[0], @XMM[8] - veor @XMM[1], @XMM[1], @XMM[8] - bx lr -.size _bsaes_encrypt8,.-_bsaes_encrypt8 -___ -} -{ -my ($out,$inp,$rounds,$const)=("r12","r4","r5","r6"); - -sub bitslice_key { -my @x=reverse(@_[0..7]); -my ($bs0,$bs1,$bs2,$t2,$t3)=@_[8..12]; - - &swapmove (@x[0,1],1,$bs0,$t2,$t3); -$code.=<<___; - @ &swapmove(@x[2,3],1,$t0,$t2,$t3); - vmov @x[2], @x[0] - vmov @x[3], @x[1] -___ - #&swapmove2x(@x[4,5,6,7],1,$t0,$t2,$t3); - - &swapmove2x (@x[0,2,1,3],2,$bs1,$t2,$t3); -$code.=<<___; - @ &swapmove2x(@x[4,6,5,7],2,$t1,$t2,$t3); - vmov @x[4], @x[0] - vmov @x[6], @x[2] - vmov @x[5], @x[1] - vmov @x[7], @x[3] -___ - &swapmove2x (@x[0,4,1,5],4,$bs2,$t2,$t3); - &swapmove2x (@x[2,6,3,7],4,$bs2,$t2,$t3); -} - -$code.=<<___; -.type _bsaes_key_convert,%function -.align 4 -_bsaes_key_convert: - adr $const,_bsaes_key_convert - vld1.8 {@XMM[7]}, [$inp]! @ load round 0 key - sub $const,$const,#_bsaes_key_convert-.LM0 - vld1.8 {@XMM[15]}, [$inp]! @ load round 1 key - - vmov.i8 @XMM[8], #0x01 @ bit masks - vmov.i8 @XMM[9], #0x02 - vmov.i8 @XMM[10], #0x04 - vmov.i8 @XMM[11], #0x08 - vmov.i8 @XMM[12], #0x10 - vmov.i8 @XMM[13], #0x20 - vldmia $const, {@XMM[14]} @ .LM0 - -#ifdef __ARMEL__ - vrev32.8 @XMM[7], @XMM[7] - vrev32.8 @XMM[15], @XMM[15] -#endif - sub $rounds,$rounds,#1 - vstmia $out!, {@XMM[7]} @ save round 0 key - b .Lkey_loop - -.align 4 -.Lkey_loop: - vtbl.8 `&Dlo(@XMM[7])`,{@XMM[15]},`&Dlo(@XMM[14])` - vtbl.8 `&Dhi(@XMM[7])`,{@XMM[15]},`&Dhi(@XMM[14])` - vmov.i8 @XMM[6], #0x40 - vmov.i8 @XMM[15], #0x80 - - vtst.8 @XMM[0], @XMM[7], @XMM[8] - vtst.8 @XMM[1], @XMM[7], @XMM[9] - vtst.8 @XMM[2], @XMM[7], @XMM[10] - vtst.8 @XMM[3], @XMM[7], @XMM[11] - vtst.8 @XMM[4], @XMM[7], @XMM[12] - vtst.8 @XMM[5], @XMM[7], @XMM[13] - vtst.8 @XMM[6], @XMM[7], @XMM[6] - vtst.8 @XMM[7], @XMM[7], @XMM[15] - vld1.8 {@XMM[15]}, [$inp]! @ load next round key - vmvn @XMM[0], @XMM[0] @ "pnot" - vmvn @XMM[1], @XMM[1] - vmvn @XMM[5], @XMM[5] - vmvn @XMM[6], @XMM[6] -#ifdef __ARMEL__ - vrev32.8 @XMM[15], @XMM[15] -#endif - subs $rounds,$rounds,#1 - vstmia $out!,{@XMM[0]-@XMM[7]} @ write bit-sliced round key - bne .Lkey_loop - - vmov.i8 @XMM[7],#0x63 @ compose .L63 - @ don't save last round key - bx lr -.size _bsaes_key_convert,.-_bsaes_key_convert -___ -} - -if (0) { # following four functions are unsupported interface - # used for benchmarking... -$code.=<<___; -.globl bsaes_enc_key_convert -.type bsaes_enc_key_convert,%function -.align 4 -bsaes_enc_key_convert: - stmdb sp!,{r4-r6,lr} - vstmdb sp!,{d8-d15} @ ABI specification says so - - ldr r5,[$inp,#240] @ pass rounds - mov r4,$inp @ pass key - mov r12,$out @ pass key schedule - bl _bsaes_key_convert - veor @XMM[7],@XMM[7],@XMM[15] @ fix up last round key - vstmia r12, {@XMM[7]} @ save last round key - - vldmia sp!,{d8-d15} - ldmia sp!,{r4-r6,pc} -.size bsaes_enc_key_convert,.-bsaes_enc_key_convert - -.globl bsaes_encrypt_128 -.type bsaes_encrypt_128,%function -.align 4 -bsaes_encrypt_128: - stmdb sp!,{r4-r6,lr} - vstmdb sp!,{d8-d15} @ ABI specification says so -.Lenc128_loop: - vld1.8 {@XMM[0]-@XMM[1]}, [$inp]! @ load input - vld1.8 {@XMM[2]-@XMM[3]}, [$inp]! - mov r4,$key @ pass the key - vld1.8 {@XMM[4]-@XMM[5]}, [$inp]! - mov r5,#10 @ pass rounds - vld1.8 {@XMM[6]-@XMM[7]}, [$inp]! - - bl _bsaes_encrypt8 - - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - vst1.8 {@XMM[4]}, [$out]! - vst1.8 {@XMM[6]}, [$out]! - vst1.8 {@XMM[3]}, [$out]! - vst1.8 {@XMM[7]}, [$out]! - vst1.8 {@XMM[2]}, [$out]! - subs $len,$len,#0x80 - vst1.8 {@XMM[5]}, [$out]! - bhi .Lenc128_loop - - vldmia sp!,{d8-d15} - ldmia sp!,{r4-r6,pc} -.size bsaes_encrypt_128,.-bsaes_encrypt_128 - -.globl bsaes_dec_key_convert -.type bsaes_dec_key_convert,%function -.align 4 -bsaes_dec_key_convert: - stmdb sp!,{r4-r6,lr} - vstmdb sp!,{d8-d15} @ ABI specification says so - - ldr r5,[$inp,#240] @ pass rounds - mov r4,$inp @ pass key - mov r12,$out @ pass key schedule - bl _bsaes_key_convert - vldmia $out, {@XMM[6]} - vstmia r12, {@XMM[15]} @ save last round key - veor @XMM[7], @XMM[7], @XMM[6] @ fix up round 0 key - vstmia $out, {@XMM[7]} - - vldmia sp!,{d8-d15} - ldmia sp!,{r4-r6,pc} -.size bsaes_dec_key_convert,.-bsaes_dec_key_convert - -.globl bsaes_decrypt_128 -.type bsaes_decrypt_128,%function -.align 4 -bsaes_decrypt_128: - stmdb sp!,{r4-r6,lr} - vstmdb sp!,{d8-d15} @ ABI specification says so -.Ldec128_loop: - vld1.8 {@XMM[0]-@XMM[1]}, [$inp]! @ load input - vld1.8 {@XMM[2]-@XMM[3]}, [$inp]! - mov r4,$key @ pass the key - vld1.8 {@XMM[4]-@XMM[5]}, [$inp]! - mov r5,#10 @ pass rounds - vld1.8 {@XMM[6]-@XMM[7]}, [$inp]! - - bl _bsaes_decrypt8 - - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - vst1.8 {@XMM[6]}, [$out]! - vst1.8 {@XMM[4]}, [$out]! - vst1.8 {@XMM[2]}, [$out]! - vst1.8 {@XMM[7]}, [$out]! - vst1.8 {@XMM[3]}, [$out]! - subs $len,$len,#0x80 - vst1.8 {@XMM[5]}, [$out]! - bhi .Ldec128_loop - - vldmia sp!,{d8-d15} - ldmia sp!,{r4-r6,pc} -.size bsaes_decrypt_128,.-bsaes_decrypt_128 -___ -} -{ -my ($inp,$out,$len,$key, $ivp,$fp,$rounds)=map("r$_",(0..3,8..10)); -my ($keysched)=("sp"); - -$code.=<<___; -.extern AES_cbc_encrypt -.extern AES_decrypt - -.global bsaes_cbc_encrypt -.type bsaes_cbc_encrypt,%function -.align 5 -bsaes_cbc_encrypt: -#ifndef __KERNEL__ - cmp $len, #128 -#ifndef __thumb__ - blo AES_cbc_encrypt -#else - bhs 1f - b AES_cbc_encrypt -1: -#endif -#endif - - @ it is up to the caller to make sure we are called with enc == 0 - - mov ip, sp - stmdb sp!, {r4-r10, lr} - VFP_ABI_PUSH - ldr $ivp, [ip] @ IV is 1st arg on the stack - mov $len, $len, lsr#4 @ len in 16 byte blocks - sub sp, #0x10 @ scratch space to carry over the IV - mov $fp, sp @ save sp - - ldr $rounds, [$key, #240] @ get # of rounds -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, $rounds, lsl#7 @ 128 bytes per inner round key - add r12, #`128-32` @ sifze of bit-slices key schedule - - @ populate the key schedule - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - mov sp, r12 @ sp is $keysched - bl _bsaes_key_convert - vldmia $keysched, {@XMM[6]} - vstmia r12, {@XMM[15]} @ save last round key - veor @XMM[7], @XMM[7], @XMM[6] @ fix up round 0 key - vstmia $keysched, {@XMM[7]} -#else - ldr r12, [$key, #244] - eors r12, #1 - beq 0f - - @ populate the key schedule - str r12, [$key, #244] - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - add r12, $key, #248 @ pass key schedule - bl _bsaes_key_convert - add r4, $key, #248 - vldmia r4, {@XMM[6]} - vstmia r12, {@XMM[15]} @ save last round key - veor @XMM[7], @XMM[7], @XMM[6] @ fix up round 0 key - vstmia r4, {@XMM[7]} - -.align 2 -0: -#endif - - vld1.8 {@XMM[15]}, [$ivp] @ load IV - b .Lcbc_dec_loop - -.align 4 -.Lcbc_dec_loop: - subs $len, $len, #0x8 - bmi .Lcbc_dec_loop_finish - - vld1.8 {@XMM[0]-@XMM[1]}, [$inp]! @ load input - vld1.8 {@XMM[2]-@XMM[3]}, [$inp]! -#ifndef BSAES_ASM_EXTENDED_KEY - mov r4, $keysched @ pass the key -#else - add r4, $key, #248 -#endif - vld1.8 {@XMM[4]-@XMM[5]}, [$inp]! - mov r5, $rounds - vld1.8 {@XMM[6]-@XMM[7]}, [$inp] - sub $inp, $inp, #0x60 - vstmia $fp, {@XMM[15]} @ put aside IV - - bl _bsaes_decrypt8 - - vldmia $fp, {@XMM[14]} @ reload IV - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[10]-@XMM[11]}, [$inp]! - veor @XMM[1], @XMM[1], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[9] - vld1.8 {@XMM[12]-@XMM[13]}, [$inp]! - veor @XMM[4], @XMM[4], @XMM[10] - veor @XMM[2], @XMM[2], @XMM[11] - vld1.8 {@XMM[14]-@XMM[15]}, [$inp]! - veor @XMM[7], @XMM[7], @XMM[12] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - veor @XMM[3], @XMM[3], @XMM[13] - vst1.8 {@XMM[6]}, [$out]! - veor @XMM[5], @XMM[5], @XMM[14] - vst1.8 {@XMM[4]}, [$out]! - vst1.8 {@XMM[2]}, [$out]! - vst1.8 {@XMM[7]}, [$out]! - vst1.8 {@XMM[3]}, [$out]! - vst1.8 {@XMM[5]}, [$out]! - - b .Lcbc_dec_loop - -.Lcbc_dec_loop_finish: - adds $len, $len, #8 - beq .Lcbc_dec_done - - vld1.8 {@XMM[0]}, [$inp]! @ load input - cmp $len, #2 - blo .Lcbc_dec_one - vld1.8 {@XMM[1]}, [$inp]! -#ifndef BSAES_ASM_EXTENDED_KEY - mov r4, $keysched @ pass the key -#else - add r4, $key, #248 -#endif - mov r5, $rounds - vstmia $fp, {@XMM[15]} @ put aside IV - beq .Lcbc_dec_two - vld1.8 {@XMM[2]}, [$inp]! - cmp $len, #4 - blo .Lcbc_dec_three - vld1.8 {@XMM[3]}, [$inp]! - beq .Lcbc_dec_four - vld1.8 {@XMM[4]}, [$inp]! - cmp $len, #6 - blo .Lcbc_dec_five - vld1.8 {@XMM[5]}, [$inp]! - beq .Lcbc_dec_six - vld1.8 {@XMM[6]}, [$inp]! - sub $inp, $inp, #0x70 - - bl _bsaes_decrypt8 - - vldmia $fp, {@XMM[14]} @ reload IV - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[10]-@XMM[11]}, [$inp]! - veor @XMM[1], @XMM[1], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[9] - vld1.8 {@XMM[12]-@XMM[13]}, [$inp]! - veor @XMM[4], @XMM[4], @XMM[10] - veor @XMM[2], @XMM[2], @XMM[11] - vld1.8 {@XMM[15]}, [$inp]! - veor @XMM[7], @XMM[7], @XMM[12] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - veor @XMM[3], @XMM[3], @XMM[13] - vst1.8 {@XMM[6]}, [$out]! - vst1.8 {@XMM[4]}, [$out]! - vst1.8 {@XMM[2]}, [$out]! - vst1.8 {@XMM[7]}, [$out]! - vst1.8 {@XMM[3]}, [$out]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_six: - sub $inp, $inp, #0x60 - bl _bsaes_decrypt8 - vldmia $fp,{@XMM[14]} @ reload IV - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[10]-@XMM[11]}, [$inp]! - veor @XMM[1], @XMM[1], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[9] - vld1.8 {@XMM[12]}, [$inp]! - veor @XMM[4], @XMM[4], @XMM[10] - veor @XMM[2], @XMM[2], @XMM[11] - vld1.8 {@XMM[15]}, [$inp]! - veor @XMM[7], @XMM[7], @XMM[12] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - vst1.8 {@XMM[6]}, [$out]! - vst1.8 {@XMM[4]}, [$out]! - vst1.8 {@XMM[2]}, [$out]! - vst1.8 {@XMM[7]}, [$out]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_five: - sub $inp, $inp, #0x50 - bl _bsaes_decrypt8 - vldmia $fp, {@XMM[14]} @ reload IV - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[10]-@XMM[11]}, [$inp]! - veor @XMM[1], @XMM[1], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[9] - vld1.8 {@XMM[15]}, [$inp]! - veor @XMM[4], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - veor @XMM[2], @XMM[2], @XMM[11] - vst1.8 {@XMM[6]}, [$out]! - vst1.8 {@XMM[4]}, [$out]! - vst1.8 {@XMM[2]}, [$out]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_four: - sub $inp, $inp, #0x40 - bl _bsaes_decrypt8 - vldmia $fp, {@XMM[14]} @ reload IV - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[10]}, [$inp]! - veor @XMM[1], @XMM[1], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[9] - vld1.8 {@XMM[15]}, [$inp]! - veor @XMM[4], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - vst1.8 {@XMM[6]}, [$out]! - vst1.8 {@XMM[4]}, [$out]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_three: - sub $inp, $inp, #0x30 - bl _bsaes_decrypt8 - vldmia $fp, {@XMM[14]} @ reload IV - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[15]}, [$inp]! - veor @XMM[1], @XMM[1], @XMM[8] - veor @XMM[6], @XMM[6], @XMM[9] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - vst1.8 {@XMM[6]}, [$out]! - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_two: - sub $inp, $inp, #0x20 - bl _bsaes_decrypt8 - vldmia $fp, {@XMM[14]} @ reload IV - vld1.8 {@XMM[8]}, [$inp]! @ reload input - veor @XMM[0], @XMM[0], @XMM[14] @ ^= IV - vld1.8 {@XMM[15]}, [$inp]! @ reload input - veor @XMM[1], @XMM[1], @XMM[8] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - b .Lcbc_dec_done -.align 4 -.Lcbc_dec_one: - sub $inp, $inp, #0x10 - mov $rounds, $out @ save original out pointer - mov $out, $fp @ use the iv scratch space as out buffer - mov r2, $key - vmov @XMM[4],@XMM[15] @ just in case ensure that IV - vmov @XMM[5],@XMM[0] @ and input are preserved - bl AES_decrypt - vld1.8 {@XMM[0]}, [$fp,:64] @ load result - veor @XMM[0], @XMM[0], @XMM[4] @ ^= IV - vmov @XMM[15], @XMM[5] @ @XMM[5] holds input - vst1.8 {@XMM[0]}, [$rounds] @ write output - -.Lcbc_dec_done: -#ifndef BSAES_ASM_EXTENDED_KEY - vmov.i32 q0, #0 - vmov.i32 q1, #0 -.Lcbc_dec_bzero: @ wipe key schedule [if any] - vstmia $keysched!, {q0-q1} - cmp $keysched, $fp - bne .Lcbc_dec_bzero -#endif - - mov sp, $fp - add sp, #0x10 @ add sp,$fp,#0x10 is no good for thumb - vst1.8 {@XMM[15]}, [$ivp] @ return IV - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} -.size bsaes_cbc_encrypt,.-bsaes_cbc_encrypt -___ -} -{ -my ($inp,$out,$len,$key, $ctr,$fp,$rounds)=(map("r$_",(0..3,8..10))); -my $const = "r6"; # shared with _bsaes_encrypt8_alt -my $keysched = "sp"; - -$code.=<<___; -.extern AES_encrypt -.global bsaes_ctr32_encrypt_blocks -.type bsaes_ctr32_encrypt_blocks,%function -.align 5 -bsaes_ctr32_encrypt_blocks: - cmp $len, #8 @ use plain AES for - blo .Lctr_enc_short @ small sizes - - mov ip, sp - stmdb sp!, {r4-r10, lr} - VFP_ABI_PUSH - ldr $ctr, [ip] @ ctr is 1st arg on the stack - sub sp, sp, #0x10 @ scratch space to carry over the ctr - mov $fp, sp @ save sp - - ldr $rounds, [$key, #240] @ get # of rounds -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, $rounds, lsl#7 @ 128 bytes per inner round key - add r12, #`128-32` @ size of bit-sliced key schedule - - @ populate the key schedule - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - mov sp, r12 @ sp is $keysched - bl _bsaes_key_convert - veor @XMM[7],@XMM[7],@XMM[15] @ fix up last round key - vstmia r12, {@XMM[7]} @ save last round key - - vld1.8 {@XMM[0]}, [$ctr] @ load counter - add $ctr, $const, #.LREVM0SR-.LM0 @ borrow $ctr - vldmia $keysched, {@XMM[4]} @ load round0 key -#else - ldr r12, [$key, #244] - eors r12, #1 - beq 0f - - @ populate the key schedule - str r12, [$key, #244] - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - add r12, $key, #248 @ pass key schedule - bl _bsaes_key_convert - veor @XMM[7],@XMM[7],@XMM[15] @ fix up last round key - vstmia r12, {@XMM[7]} @ save last round key - -.align 2 -0: add r12, $key, #248 - vld1.8 {@XMM[0]}, [$ctr] @ load counter - adrl $ctr, .LREVM0SR @ borrow $ctr - vldmia r12, {@XMM[4]} @ load round0 key - sub sp, #0x10 @ place for adjusted round0 key -#endif - - vmov.i32 @XMM[8],#1 @ compose 1<<96 - veor @XMM[9],@XMM[9],@XMM[9] - vrev32.8 @XMM[0],@XMM[0] - vext.8 @XMM[8],@XMM[9],@XMM[8],#4 - vrev32.8 @XMM[4],@XMM[4] - vadd.u32 @XMM[9],@XMM[8],@XMM[8] @ compose 2<<96 - vstmia $keysched, {@XMM[4]} @ save adjusted round0 key - b .Lctr_enc_loop - -.align 4 -.Lctr_enc_loop: - vadd.u32 @XMM[10], @XMM[8], @XMM[9] @ compose 3<<96 - vadd.u32 @XMM[1], @XMM[0], @XMM[8] @ +1 - vadd.u32 @XMM[2], @XMM[0], @XMM[9] @ +2 - vadd.u32 @XMM[3], @XMM[0], @XMM[10] @ +3 - vadd.u32 @XMM[4], @XMM[1], @XMM[10] - vadd.u32 @XMM[5], @XMM[2], @XMM[10] - vadd.u32 @XMM[6], @XMM[3], @XMM[10] - vadd.u32 @XMM[7], @XMM[4], @XMM[10] - vadd.u32 @XMM[10], @XMM[5], @XMM[10] @ next counter - - @ Borrow prologue from _bsaes_encrypt8 to use the opportunity - @ to flip byte order in 32-bit counter - - vldmia $keysched, {@XMM[9]} @ load round0 key -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, $keysched, #0x10 @ pass next round key -#else - add r4, $key, #`248+16` -#endif - vldmia $ctr, {@XMM[8]} @ .LREVM0SR - mov r5, $rounds @ pass rounds - vstmia $fp, {@XMM[10]} @ save next counter - sub $const, $ctr, #.LREVM0SR-.LSR @ pass constants - - bl _bsaes_encrypt8_alt - - subs $len, $len, #8 - blo .Lctr_enc_loop_done - - vld1.8 {@XMM[8]-@XMM[9]}, [$inp]! @ load input - vld1.8 {@XMM[10]-@XMM[11]}, [$inp]! - veor @XMM[0], @XMM[8] - veor @XMM[1], @XMM[9] - vld1.8 {@XMM[12]-@XMM[13]}, [$inp]! - veor @XMM[4], @XMM[10] - veor @XMM[6], @XMM[11] - vld1.8 {@XMM[14]-@XMM[15]}, [$inp]! - veor @XMM[3], @XMM[12] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! @ write output - veor @XMM[7], @XMM[13] - veor @XMM[2], @XMM[14] - vst1.8 {@XMM[4]}, [$out]! - veor @XMM[5], @XMM[15] - vst1.8 {@XMM[6]}, [$out]! - vmov.i32 @XMM[8], #1 @ compose 1<<96 - vst1.8 {@XMM[3]}, [$out]! - veor @XMM[9], @XMM[9], @XMM[9] - vst1.8 {@XMM[7]}, [$out]! - vext.8 @XMM[8], @XMM[9], @XMM[8], #4 - vst1.8 {@XMM[2]}, [$out]! - vadd.u32 @XMM[9],@XMM[8],@XMM[8] @ compose 2<<96 - vst1.8 {@XMM[5]}, [$out]! - vldmia $fp, {@XMM[0]} @ load counter - - bne .Lctr_enc_loop - b .Lctr_enc_done - -.align 4 -.Lctr_enc_loop_done: - add $len, $len, #8 - vld1.8 {@XMM[8]}, [$inp]! @ load input - veor @XMM[0], @XMM[8] - vst1.8 {@XMM[0]}, [$out]! @ write output - cmp $len, #2 - blo .Lctr_enc_done - vld1.8 {@XMM[9]}, [$inp]! - veor @XMM[1], @XMM[9] - vst1.8 {@XMM[1]}, [$out]! - beq .Lctr_enc_done - vld1.8 {@XMM[10]}, [$inp]! - veor @XMM[4], @XMM[10] - vst1.8 {@XMM[4]}, [$out]! - cmp $len, #4 - blo .Lctr_enc_done - vld1.8 {@XMM[11]}, [$inp]! - veor @XMM[6], @XMM[11] - vst1.8 {@XMM[6]}, [$out]! - beq .Lctr_enc_done - vld1.8 {@XMM[12]}, [$inp]! - veor @XMM[3], @XMM[12] - vst1.8 {@XMM[3]}, [$out]! - cmp $len, #6 - blo .Lctr_enc_done - vld1.8 {@XMM[13]}, [$inp]! - veor @XMM[7], @XMM[13] - vst1.8 {@XMM[7]}, [$out]! - beq .Lctr_enc_done - vld1.8 {@XMM[14]}, [$inp] - veor @XMM[2], @XMM[14] - vst1.8 {@XMM[2]}, [$out]! - -.Lctr_enc_done: - vmov.i32 q0, #0 - vmov.i32 q1, #0 -#ifndef BSAES_ASM_EXTENDED_KEY -.Lctr_enc_bzero: @ wipe key schedule [if any] - vstmia $keysched!, {q0-q1} - cmp $keysched, $fp - bne .Lctr_enc_bzero -#else - vstmia $keysched, {q0-q1} -#endif - - mov sp, $fp - add sp, #0x10 @ add sp,$fp,#0x10 is no good for thumb - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} @ return - -.align 4 -.Lctr_enc_short: - ldr ip, [sp] @ ctr pointer is passed on stack - stmdb sp!, {r4-r8, lr} - - mov r4, $inp @ copy arguments - mov r5, $out - mov r6, $len - mov r7, $key - ldr r8, [ip, #12] @ load counter LSW - vld1.8 {@XMM[1]}, [ip] @ load whole counter value -#ifdef __ARMEL__ - rev r8, r8 -#endif - sub sp, sp, #0x10 - vst1.8 {@XMM[1]}, [sp,:64] @ copy counter value - sub sp, sp, #0x10 - -.Lctr_enc_short_loop: - add r0, sp, #0x10 @ input counter value - mov r1, sp @ output on the stack - mov r2, r7 @ key - - bl AES_encrypt - - vld1.8 {@XMM[0]}, [r4]! @ load input - vld1.8 {@XMM[1]}, [sp,:64] @ load encrypted counter - add r8, r8, #1 -#ifdef __ARMEL__ - rev r0, r8 - str r0, [sp, #0x1c] @ next counter value -#else - str r8, [sp, #0x1c] @ next counter value -#endif - veor @XMM[0],@XMM[0],@XMM[1] - vst1.8 {@XMM[0]}, [r5]! @ store output - subs r6, r6, #1 - bne .Lctr_enc_short_loop - - vmov.i32 q0, #0 - vmov.i32 q1, #0 - vstmia sp!, {q0-q1} - - ldmia sp!, {r4-r8, pc} -.size bsaes_ctr32_encrypt_blocks,.-bsaes_ctr32_encrypt_blocks -___ -} -{ -###################################################################### -# void bsaes_xts_[en|de]crypt(const char *inp,char *out,size_t len, -# const AES_KEY *key1, const AES_KEY *key2, -# const unsigned char iv[16]); -# -my ($inp,$out,$len,$key,$rounds,$magic,$fp)=(map("r$_",(7..10,1..3))); -my $const="r6"; # returned by _bsaes_key_convert -my $twmask=@XMM[5]; -my @T=@XMM[6..7]; - -$code.=<<___; -.globl bsaes_xts_encrypt -.type bsaes_xts_encrypt,%function -.align 4 -bsaes_xts_encrypt: - mov ip, sp - stmdb sp!, {r4-r10, lr} @ 0x20 - VFP_ABI_PUSH - mov r6, sp @ future $fp - - mov $inp, r0 - mov $out, r1 - mov $len, r2 - mov $key, r3 - - sub r0, sp, #0x10 @ 0x10 - bic r0, #0xf @ align at 16 bytes - mov sp, r0 - -#ifdef XTS_CHAIN_TWEAK - ldr r0, [ip] @ pointer to input tweak -#else - @ generate initial tweak - ldr r0, [ip, #4] @ iv[] - mov r1, sp - ldr r2, [ip, #0] @ key2 - bl AES_encrypt - mov r0,sp @ pointer to initial tweak -#endif - - ldr $rounds, [$key, #240] @ get # of rounds - mov $fp, r6 -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, $rounds, lsl#7 @ 128 bytes per inner round key - @ add r12, #`128-32` @ size of bit-sliced key schedule - sub r12, #`32+16` @ place for tweak[9] - - @ populate the key schedule - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - mov sp, r12 - add r12, #0x90 @ pass key schedule - bl _bsaes_key_convert - veor @XMM[7], @XMM[7], @XMM[15] @ fix up last round key - vstmia r12, {@XMM[7]} @ save last round key -#else - ldr r12, [$key, #244] - eors r12, #1 - beq 0f - - str r12, [$key, #244] - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - add r12, $key, #248 @ pass key schedule - bl _bsaes_key_convert - veor @XMM[7], @XMM[7], @XMM[15] @ fix up last round key - vstmia r12, {@XMM[7]} - -.align 2 -0: sub sp, #0x90 @ place for tweak[9] -#endif - - vld1.8 {@XMM[8]}, [r0] @ initial tweak - adr $magic, .Lxts_magic - - subs $len, #0x80 - blo .Lxts_enc_short - b .Lxts_enc_loop - -.align 4 -.Lxts_enc_loop: - vldmia $magic, {$twmask} @ load XTS magic - vshr.s64 @T[0], @XMM[8], #63 - mov r0, sp - vand @T[0], @T[0], $twmask -___ -for($i=9;$i<16;$i++) { -$code.=<<___; - vadd.u64 @XMM[$i], @XMM[$i-1], @XMM[$i-1] - vst1.64 {@XMM[$i-1]}, [r0,:128]! - vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")` - vshr.s64 @T[1], @XMM[$i], #63 - veor @XMM[$i], @XMM[$i], @T[0] - vand @T[1], @T[1], $twmask -___ - @T=reverse(@T); - -$code.=<<___ if ($i>=10); - vld1.8 {@XMM[$i-10]}, [$inp]! -___ -$code.=<<___ if ($i>=11); - veor @XMM[$i-11], @XMM[$i-11], @XMM[$i-3] -___ -} -$code.=<<___; - vadd.u64 @XMM[8], @XMM[15], @XMM[15] - vst1.64 {@XMM[15]}, [r0,:128]! - vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")` - veor @XMM[8], @XMM[8], @T[0] - vst1.64 {@XMM[8]}, [r0,:128] @ next round tweak - - vld1.8 {@XMM[6]-@XMM[7]}, [$inp]! - veor @XMM[5], @XMM[5], @XMM[13] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[6], @XMM[6], @XMM[14] - mov r5, $rounds @ pass rounds - veor @XMM[7], @XMM[7], @XMM[15] - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]-@XMM[13]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[6], @XMM[11] - vld1.64 {@XMM[14]-@XMM[15]}, [r0,:128]! - veor @XMM[10], @XMM[3], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - veor @XMM[11], @XMM[7], @XMM[13] - veor @XMM[12], @XMM[2], @XMM[14] - vst1.8 {@XMM[10]-@XMM[11]}, [$out]! - veor @XMM[13], @XMM[5], @XMM[15] - vst1.8 {@XMM[12]-@XMM[13]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - - subs $len, #0x80 - bpl .Lxts_enc_loop - -.Lxts_enc_short: - adds $len, #0x70 - bmi .Lxts_enc_done - - vldmia $magic, {$twmask} @ load XTS magic - vshr.s64 @T[0], @XMM[8], #63 - mov r0, sp - vand @T[0], @T[0], $twmask -___ -for($i=9;$i<16;$i++) { -$code.=<<___; - vadd.u64 @XMM[$i], @XMM[$i-1], @XMM[$i-1] - vst1.64 {@XMM[$i-1]}, [r0,:128]! - vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")` - vshr.s64 @T[1], @XMM[$i], #63 - veor @XMM[$i], @XMM[$i], @T[0] - vand @T[1], @T[1], $twmask -___ - @T=reverse(@T); - -$code.=<<___ if ($i>=10); - vld1.8 {@XMM[$i-10]}, [$inp]! - subs $len, #0x10 - bmi .Lxts_enc_`$i-9` -___ -$code.=<<___ if ($i>=11); - veor @XMM[$i-11], @XMM[$i-11], @XMM[$i-3] -___ -} -$code.=<<___; - sub $len, #0x10 - vst1.64 {@XMM[15]}, [r0,:128] @ next round tweak - - vld1.8 {@XMM[6]}, [$inp]! - veor @XMM[5], @XMM[5], @XMM[13] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[6], @XMM[6], @XMM[14] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]-@XMM[13]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[6], @XMM[11] - vld1.64 {@XMM[14]}, [r0,:128]! - veor @XMM[10], @XMM[3], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - veor @XMM[11], @XMM[7], @XMM[13] - veor @XMM[12], @XMM[2], @XMM[14] - vst1.8 {@XMM[10]-@XMM[11]}, [$out]! - vst1.8 {@XMM[12]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_6: - vst1.64 {@XMM[14]}, [r0,:128] @ next round tweak - - veor @XMM[4], @XMM[4], @XMM[12] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[5], @XMM[5], @XMM[13] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]-@XMM[13]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[6], @XMM[11] - veor @XMM[10], @XMM[3], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - veor @XMM[11], @XMM[7], @XMM[13] - vst1.8 {@XMM[10]-@XMM[11]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_enc_done - -@ put this in range for both ARM and Thumb mode adr instructions -.align 5 -.Lxts_magic: - .quad 1, 0x87 - -.align 5 -.Lxts_enc_5: - vst1.64 {@XMM[13]}, [r0,:128] @ next round tweak - - veor @XMM[3], @XMM[3], @XMM[11] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[4], @XMM[4], @XMM[12] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[6], @XMM[11] - veor @XMM[10], @XMM[3], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - vst1.8 {@XMM[10]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_4: - vst1.64 {@XMM[12]}, [r0,:128] @ next round tweak - - veor @XMM[2], @XMM[2], @XMM[10] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[3], @XMM[3], @XMM[11] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[6], @XMM[11] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_3: - vst1.64 {@XMM[11]}, [r0,:128] @ next round tweak - - veor @XMM[1], @XMM[1], @XMM[9] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[2], @XMM[2], @XMM[10] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[8]-@XMM[9]}, [r0,:128]! - vld1.64 {@XMM[10]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[4], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - vst1.8 {@XMM[8]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_2: - vst1.64 {@XMM[10]}, [r0,:128] @ next round tweak - - veor @XMM[0], @XMM[0], @XMM[8] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[1], @XMM[1], @XMM[9] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_encrypt8 - - vld1.64 {@XMM[8]-@XMM[9]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - veor @XMM[1], @XMM[1], @XMM[ 9] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_enc_done -.align 4 -.Lxts_enc_1: - mov r0, sp - veor @XMM[0], @XMM[8] - mov r1, sp - vst1.8 {@XMM[0]}, [sp,:128] - mov r2, $key - mov r4, $fp @ preserve fp - - bl AES_encrypt - - vld1.8 {@XMM[0]}, [sp,:128] - veor @XMM[0], @XMM[0], @XMM[8] - vst1.8 {@XMM[0]}, [$out]! - mov $fp, r4 - - vmov @XMM[8], @XMM[9] @ next round tweak - -.Lxts_enc_done: -#ifndef XTS_CHAIN_TWEAK - adds $len, #0x10 - beq .Lxts_enc_ret - sub r6, $out, #0x10 - -.Lxts_enc_steal: - ldrb r0, [$inp], #1 - ldrb r1, [$out, #-0x10] - strb r0, [$out, #-0x10] - strb r1, [$out], #1 - - subs $len, #1 - bhi .Lxts_enc_steal - - vld1.8 {@XMM[0]}, [r6] - mov r0, sp - veor @XMM[0], @XMM[0], @XMM[8] - mov r1, sp - vst1.8 {@XMM[0]}, [sp,:128] - mov r2, $key - mov r4, $fp @ preserve fp - - bl AES_encrypt - - vld1.8 {@XMM[0]}, [sp,:128] - veor @XMM[0], @XMM[0], @XMM[8] - vst1.8 {@XMM[0]}, [r6] - mov $fp, r4 -#endif - -.Lxts_enc_ret: - bic r0, $fp, #0xf - vmov.i32 q0, #0 - vmov.i32 q1, #0 -#ifdef XTS_CHAIN_TWEAK - ldr r1, [$fp, #0x20+VFP_ABI_FRAME] @ chain tweak -#endif -.Lxts_enc_bzero: @ wipe key schedule [if any] - vstmia sp!, {q0-q1} - cmp sp, r0 - bne .Lxts_enc_bzero - - mov sp, $fp -#ifdef XTS_CHAIN_TWEAK - vst1.8 {@XMM[8]}, [r1] -#endif - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} @ return - -.size bsaes_xts_encrypt,.-bsaes_xts_encrypt - -.globl bsaes_xts_decrypt -.type bsaes_xts_decrypt,%function -.align 4 -bsaes_xts_decrypt: - mov ip, sp - stmdb sp!, {r4-r10, lr} @ 0x20 - VFP_ABI_PUSH - mov r6, sp @ future $fp - - mov $inp, r0 - mov $out, r1 - mov $len, r2 - mov $key, r3 - - sub r0, sp, #0x10 @ 0x10 - bic r0, #0xf @ align at 16 bytes - mov sp, r0 - -#ifdef XTS_CHAIN_TWEAK - ldr r0, [ip] @ pointer to input tweak -#else - @ generate initial tweak - ldr r0, [ip, #4] @ iv[] - mov r1, sp - ldr r2, [ip, #0] @ key2 - bl AES_encrypt - mov r0, sp @ pointer to initial tweak -#endif - - ldr $rounds, [$key, #240] @ get # of rounds - mov $fp, r6 -#ifndef BSAES_ASM_EXTENDED_KEY - @ allocate the key schedule on the stack - sub r12, sp, $rounds, lsl#7 @ 128 bytes per inner round key - @ add r12, #`128-32` @ size of bit-sliced key schedule - sub r12, #`32+16` @ place for tweak[9] - - @ populate the key schedule - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - mov sp, r12 - add r12, #0x90 @ pass key schedule - bl _bsaes_key_convert - add r4, sp, #0x90 - vldmia r4, {@XMM[6]} - vstmia r12, {@XMM[15]} @ save last round key - veor @XMM[7], @XMM[7], @XMM[6] @ fix up round 0 key - vstmia r4, {@XMM[7]} -#else - ldr r12, [$key, #244] - eors r12, #1 - beq 0f - - str r12, [$key, #244] - mov r4, $key @ pass key - mov r5, $rounds @ pass # of rounds - add r12, $key, #248 @ pass key schedule - bl _bsaes_key_convert - add r4, $key, #248 - vldmia r4, {@XMM[6]} - vstmia r12, {@XMM[15]} @ save last round key - veor @XMM[7], @XMM[7], @XMM[6] @ fix up round 0 key - vstmia r4, {@XMM[7]} - -.align 2 -0: sub sp, #0x90 @ place for tweak[9] -#endif - vld1.8 {@XMM[8]}, [r0] @ initial tweak - adr $magic, .Lxts_magic - - tst $len, #0xf @ if not multiple of 16 - it ne @ Thumb2 thing, sanity check in ARM - subne $len, #0x10 @ subtract another 16 bytes - subs $len, #0x80 - - blo .Lxts_dec_short - b .Lxts_dec_loop - -.align 4 -.Lxts_dec_loop: - vldmia $magic, {$twmask} @ load XTS magic - vshr.s64 @T[0], @XMM[8], #63 - mov r0, sp - vand @T[0], @T[0], $twmask -___ -for($i=9;$i<16;$i++) { -$code.=<<___; - vadd.u64 @XMM[$i], @XMM[$i-1], @XMM[$i-1] - vst1.64 {@XMM[$i-1]}, [r0,:128]! - vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")` - vshr.s64 @T[1], @XMM[$i], #63 - veor @XMM[$i], @XMM[$i], @T[0] - vand @T[1], @T[1], $twmask -___ - @T=reverse(@T); - -$code.=<<___ if ($i>=10); - vld1.8 {@XMM[$i-10]}, [$inp]! -___ -$code.=<<___ if ($i>=11); - veor @XMM[$i-11], @XMM[$i-11], @XMM[$i-3] -___ -} -$code.=<<___; - vadd.u64 @XMM[8], @XMM[15], @XMM[15] - vst1.64 {@XMM[15]}, [r0,:128]! - vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")` - veor @XMM[8], @XMM[8], @T[0] - vst1.64 {@XMM[8]}, [r0,:128] @ next round tweak - - vld1.8 {@XMM[6]-@XMM[7]}, [$inp]! - veor @XMM[5], @XMM[5], @XMM[13] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[6], @XMM[6], @XMM[14] - mov r5, $rounds @ pass rounds - veor @XMM[7], @XMM[7], @XMM[15] - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]-@XMM[13]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[6], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[4], @XMM[11] - vld1.64 {@XMM[14]-@XMM[15]}, [r0,:128]! - veor @XMM[10], @XMM[2], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - veor @XMM[11], @XMM[7], @XMM[13] - veor @XMM[12], @XMM[3], @XMM[14] - vst1.8 {@XMM[10]-@XMM[11]}, [$out]! - veor @XMM[13], @XMM[5], @XMM[15] - vst1.8 {@XMM[12]-@XMM[13]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - - subs $len, #0x80 - bpl .Lxts_dec_loop - -.Lxts_dec_short: - adds $len, #0x70 - bmi .Lxts_dec_done - - vldmia $magic, {$twmask} @ load XTS magic - vshr.s64 @T[0], @XMM[8], #63 - mov r0, sp - vand @T[0], @T[0], $twmask -___ -for($i=9;$i<16;$i++) { -$code.=<<___; - vadd.u64 @XMM[$i], @XMM[$i-1], @XMM[$i-1] - vst1.64 {@XMM[$i-1]}, [r0,:128]! - vswp `&Dhi("@T[0]")`,`&Dlo("@T[0]")` - vshr.s64 @T[1], @XMM[$i], #63 - veor @XMM[$i], @XMM[$i], @T[0] - vand @T[1], @T[1], $twmask -___ - @T=reverse(@T); - -$code.=<<___ if ($i>=10); - vld1.8 {@XMM[$i-10]}, [$inp]! - subs $len, #0x10 - bmi .Lxts_dec_`$i-9` -___ -$code.=<<___ if ($i>=11); - veor @XMM[$i-11], @XMM[$i-11], @XMM[$i-3] -___ -} -$code.=<<___; - sub $len, #0x10 - vst1.64 {@XMM[15]}, [r0,:128] @ next round tweak - - vld1.8 {@XMM[6]}, [$inp]! - veor @XMM[5], @XMM[5], @XMM[13] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[6], @XMM[6], @XMM[14] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]-@XMM[13]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[6], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[4], @XMM[11] - vld1.64 {@XMM[14]}, [r0,:128]! - veor @XMM[10], @XMM[2], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - veor @XMM[11], @XMM[7], @XMM[13] - veor @XMM[12], @XMM[3], @XMM[14] - vst1.8 {@XMM[10]-@XMM[11]}, [$out]! - vst1.8 {@XMM[12]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_6: - vst1.64 {@XMM[14]}, [r0,:128] @ next round tweak - - veor @XMM[4], @XMM[4], @XMM[12] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[5], @XMM[5], @XMM[13] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]-@XMM[13]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[6], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[4], @XMM[11] - veor @XMM[10], @XMM[2], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - veor @XMM[11], @XMM[7], @XMM[13] - vst1.8 {@XMM[10]-@XMM[11]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_5: - vst1.64 {@XMM[13]}, [r0,:128] @ next round tweak - - veor @XMM[3], @XMM[3], @XMM[11] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[4], @XMM[4], @XMM[12] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - vld1.64 {@XMM[12]}, [r0,:128]! - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[6], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[4], @XMM[11] - veor @XMM[10], @XMM[2], @XMM[12] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - vst1.8 {@XMM[10]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_4: - vst1.64 {@XMM[12]}, [r0,:128] @ next round tweak - - veor @XMM[2], @XMM[2], @XMM[10] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[3], @XMM[3], @XMM[11] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[ 8]-@XMM[ 9]}, [r0,:128]! - vld1.64 {@XMM[10]-@XMM[11]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[6], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - veor @XMM[9], @XMM[4], @XMM[11] - vst1.8 {@XMM[8]-@XMM[9]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_3: - vst1.64 {@XMM[11]}, [r0,:128] @ next round tweak - - veor @XMM[1], @XMM[1], @XMM[9] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[2], @XMM[2], @XMM[10] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[8]-@XMM[9]}, [r0,:128]! - vld1.64 {@XMM[10]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - veor @XMM[1], @XMM[1], @XMM[ 9] - veor @XMM[8], @XMM[6], @XMM[10] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - vst1.8 {@XMM[8]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_2: - vst1.64 {@XMM[10]}, [r0,:128] @ next round tweak - - veor @XMM[0], @XMM[0], @XMM[8] -#ifndef BSAES_ASM_EXTENDED_KEY - add r4, sp, #0x90 @ pass key schedule -#else - add r4, $key, #248 @ pass key schedule -#endif - veor @XMM[1], @XMM[1], @XMM[9] - mov r5, $rounds @ pass rounds - mov r0, sp - - bl _bsaes_decrypt8 - - vld1.64 {@XMM[8]-@XMM[9]}, [r0,:128]! - veor @XMM[0], @XMM[0], @XMM[ 8] - veor @XMM[1], @XMM[1], @XMM[ 9] - vst1.8 {@XMM[0]-@XMM[1]}, [$out]! - - vld1.64 {@XMM[8]}, [r0,:128] @ next round tweak - b .Lxts_dec_done -.align 4 -.Lxts_dec_1: - mov r0, sp - veor @XMM[0], @XMM[8] - mov r1, sp - vst1.8 {@XMM[0]}, [sp,:128] - mov r2, $key - mov r4, $fp @ preserve fp - mov r5, $magic @ preserve magic - - bl AES_decrypt - - vld1.8 {@XMM[0]}, [sp,:128] - veor @XMM[0], @XMM[0], @XMM[8] - vst1.8 {@XMM[0]}, [$out]! - mov $fp, r4 - mov $magic, r5 - - vmov @XMM[8], @XMM[9] @ next round tweak - -.Lxts_dec_done: -#ifndef XTS_CHAIN_TWEAK - adds $len, #0x10 - beq .Lxts_dec_ret - - @ calculate one round of extra tweak for the stolen ciphertext - vldmia $magic, {$twmask} - vshr.s64 @XMM[6], @XMM[8], #63 - vand @XMM[6], @XMM[6], $twmask - vadd.u64 @XMM[9], @XMM[8], @XMM[8] - vswp `&Dhi("@XMM[6]")`,`&Dlo("@XMM[6]")` - veor @XMM[9], @XMM[9], @XMM[6] - - @ perform the final decryption with the last tweak value - vld1.8 {@XMM[0]}, [$inp]! - mov r0, sp - veor @XMM[0], @XMM[0], @XMM[9] - mov r1, sp - vst1.8 {@XMM[0]}, [sp,:128] - mov r2, $key - mov r4, $fp @ preserve fp - - bl AES_decrypt - - vld1.8 {@XMM[0]}, [sp,:128] - veor @XMM[0], @XMM[0], @XMM[9] - vst1.8 {@XMM[0]}, [$out] - - mov r6, $out -.Lxts_dec_steal: - ldrb r1, [$out] - ldrb r0, [$inp], #1 - strb r1, [$out, #0x10] - strb r0, [$out], #1 - - subs $len, #1 - bhi .Lxts_dec_steal - - vld1.8 {@XMM[0]}, [r6] - mov r0, sp - veor @XMM[0], @XMM[8] - mov r1, sp - vst1.8 {@XMM[0]}, [sp,:128] - mov r2, $key - - bl AES_decrypt - - vld1.8 {@XMM[0]}, [sp,:128] - veor @XMM[0], @XMM[0], @XMM[8] - vst1.8 {@XMM[0]}, [r6] - mov $fp, r4 -#endif - -.Lxts_dec_ret: - bic r0, $fp, #0xf - vmov.i32 q0, #0 - vmov.i32 q1, #0 -#ifdef XTS_CHAIN_TWEAK - ldr r1, [$fp, #0x20+VFP_ABI_FRAME] @ chain tweak -#endif -.Lxts_dec_bzero: @ wipe key schedule [if any] - vstmia sp!, {q0-q1} - cmp sp, r0 - bne .Lxts_dec_bzero - - mov sp, $fp -#ifdef XTS_CHAIN_TWEAK - vst1.8 {@XMM[8]}, [r1] -#endif - VFP_ABI_POP - ldmia sp!, {r4-r10, pc} @ return - -.size bsaes_xts_decrypt,.-bsaes_xts_decrypt -___ -} -$code.=<<___; -#endif -___ - -$code =~ s/\`([^\`]*)\`/eval($1)/gem; - -open SELF,$0; -while(<SELF>) { - next if (/^#!/); - last if (!s/^#/@/ and !/^$/); - print; -} -close SELF; - -print $code; - -close STDOUT; diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index c38b58c..59ceae8 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -24,7 +24,6 @@ generic-y += sembuf.h generic-y += serial.h generic-y += shmbuf.h generic-y += siginfo.h -generic-y += simd.h generic-y += sizes.h generic-y += socket.h generic-y += sockios.h @@ -33,4 +32,3 @@ generic-y += termios.h generic-y += timex.h generic-y += trace_clock.h generic-y += unaligned.h -generic-y += preempt.h diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 0704e0c..5665134 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -87,43 +87,17 @@ static inline u64 arch_counter_get_cntvct(void) return cval; } -static inline u32 arch_timer_get_cntkctl(void) +static inline void arch_counter_set_user_access(void) { u32 cntkctl; + asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl)); - return cntkctl; -} -static inline void arch_timer_set_cntkctl(u32 cntkctl) -{ - asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); -} + /* disable user access to everything */ + cntkctl &= ~((3 << 8) | (7 << 0)); -static inline void arch_counter_set_user_access(void) -{ - u32 cntkctl = arch_timer_get_cntkctl(); - - /* Disable user access to both physical/virtual counters/timers */ - /* Also disable virtual event stream */ - cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN - | ARCH_TIMER_USR_VT_ACCESS_EN - | ARCH_TIMER_VIRT_EVT_EN - | ARCH_TIMER_USR_VCT_ACCESS_EN - | ARCH_TIMER_USR_PCT_ACCESS_EN); - arch_timer_set_cntkctl(cntkctl); -} - -static inline void arch_timer_evtstrm_enable(int divider) -{ - u32 cntkctl = arch_timer_get_cntkctl(); - cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK; - /* Set the divider and enable virtual event stream */ - cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) - | ARCH_TIMER_VIRT_EVT_EN; - arch_timer_set_cntkctl(cntkctl); - elf_hwcap |= HWCAP_EVTSTRM; + asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); } - #endif #endif diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 5c22851..fcc1b5b 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -53,13 +53,6 @@ #define put_byte_3 lsl #0 #endif -/* Select code for any configuration running in BE8 mode */ -#ifdef CONFIG_CPU_ENDIAN_BE8 -#define ARM_BE8(code...) code -#else -#define ARM_BE8(code...) -#endif - /* * Data preload for architectures that support it */ diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 62d2cb5..da1c77d 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -12,7 +12,6 @@ #define __ASM_ARM_ATOMIC_H #include <linux/compiler.h> -#include <linux/prefetch.h> #include <linux/types.h> #include <linux/irqflags.h> #include <asm/barrier.h> @@ -42,7 +41,6 @@ static inline void atomic_add(int i, atomic_t *v) unsigned long tmp; int result; - prefetchw(&v->counter); __asm__ __volatile__("@ atomic_add\n" "1: ldrex %0, [%3]\n" " add %0, %0, %4\n" @@ -81,7 +79,6 @@ static inline void atomic_sub(int i, atomic_t *v) unsigned long tmp; int result; - prefetchw(&v->counter); __asm__ __volatile__("@ atomic_sub\n" "1: ldrex %0, [%3]\n" " sub %0, %0, %4\n" @@ -117,8 +114,7 @@ static inline int atomic_sub_return(int i, atomic_t *v) static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) { - int oldval; - unsigned long res; + unsigned long oldval, res; smp_mb(); @@ -138,6 +134,21 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) return oldval; } +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long tmp, tmp2; + + __asm__ __volatile__("@ atomic_clear_mask\n" +"1: ldrex %0, [%3]\n" +" bic %0, %0, %4\n" +" strex %1, %0, [%3]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr) + : "r" (addr), "Ir" (mask) + : "cc"); +} + #else /* ARM_ARCH_6 */ #ifdef CONFIG_SMP @@ -186,6 +197,15 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new) return ret; } +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags; + + raw_local_irq_save(flags); + *addr &= ~mask; + raw_local_irq_restore(flags); +} + #endif /* __LINUX_ARM_ARCH__ */ #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) @@ -218,15 +238,15 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) #ifndef CONFIG_GENERIC_ATOMIC64 typedef struct { - long long counter; + u64 __aligned(8) counter; } atomic64_t; #define ATOMIC64_INIT(i) { (i) } #ifdef CONFIG_ARM_LPAE -static inline long long atomic64_read(const atomic64_t *v) +static inline u64 atomic64_read(const atomic64_t *v) { - long long result; + u64 result; __asm__ __volatile__("@ atomic64_read\n" " ldrd %0, %H0, [%1]" @@ -237,7 +257,7 @@ static inline long long atomic64_read(const atomic64_t *v) return result; } -static inline void atomic64_set(atomic64_t *v, long long i) +static inline void atomic64_set(atomic64_t *v, u64 i) { __asm__ __volatile__("@ atomic64_set\n" " strd %2, %H2, [%1]" @@ -246,9 +266,9 @@ static inline void atomic64_set(atomic64_t *v, long long i) ); } #else -static inline long long atomic64_read(const atomic64_t *v) +static inline u64 atomic64_read(const atomic64_t *v) { - long long result; + u64 result; __asm__ __volatile__("@ atomic64_read\n" " ldrexd %0, %H0, [%1]" @@ -259,11 +279,10 @@ static inline long long atomic64_read(const atomic64_t *v) return result; } -static inline void atomic64_set(atomic64_t *v, long long i) +static inline void atomic64_set(atomic64_t *v, u64 i) { - long long tmp; + u64 tmp; - prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_set\n" "1: ldrexd %0, %H0, [%2]\n" " strexd %0, %3, %H3, [%2]\n" @@ -275,16 +294,15 @@ static inline void atomic64_set(atomic64_t *v, long long i) } #endif -static inline void atomic64_add(long long i, atomic64_t *v) +static inline void atomic64_add(u64 i, atomic64_t *v) { - long long result; + u64 result; unsigned long tmp; - prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_add\n" "1: ldrexd %0, %H0, [%3]\n" -" adds %Q0, %Q0, %Q4\n" -" adc %R0, %R0, %R4\n" +" adds %0, %0, %4\n" +" adc %H0, %H0, %H4\n" " strexd %1, %0, %H0, [%3]\n" " teq %1, #0\n" " bne 1b" @@ -293,17 +311,17 @@ static inline void atomic64_add(long long i, atomic64_t *v) : "cc"); } -static inline long long atomic64_add_return(long long i, atomic64_t *v) +static inline u64 atomic64_add_return(u64 i, atomic64_t *v) { - long long result; + u64 result; unsigned long tmp; smp_mb(); __asm__ __volatile__("@ atomic64_add_return\n" "1: ldrexd %0, %H0, [%3]\n" -" adds %Q0, %Q0, %Q4\n" -" adc %R0, %R0, %R4\n" +" adds %0, %0, %4\n" +" adc %H0, %H0, %H4\n" " strexd %1, %0, %H0, [%3]\n" " teq %1, #0\n" " bne 1b" @@ -316,16 +334,15 @@ static inline long long atomic64_add_return(long long i, atomic64_t *v) return result; } -static inline void atomic64_sub(long long i, atomic64_t *v) +static inline void atomic64_sub(u64 i, atomic64_t *v) { - long long result; + u64 result; unsigned long tmp; - prefetchw(&v->counter); __asm__ __volatile__("@ atomic64_sub\n" "1: ldrexd %0, %H0, [%3]\n" -" subs %Q0, %Q0, %Q4\n" -" sbc %R0, %R0, %R4\n" +" subs %0, %0, %4\n" +" sbc %H0, %H0, %H4\n" " strexd %1, %0, %H0, [%3]\n" " teq %1, #0\n" " bne 1b" @@ -334,17 +351,17 @@ static inline void atomic64_sub(long long i, atomic64_t *v) : "cc"); } -static inline long long atomic64_sub_return(long long i, atomic64_t *v) +static inline u64 atomic64_sub_return(u64 i, atomic64_t *v) { - long long result; + u64 result; unsigned long tmp; smp_mb(); __asm__ __volatile__("@ atomic64_sub_return\n" "1: ldrexd %0, %H0, [%3]\n" -" subs %Q0, %Q0, %Q4\n" -" sbc %R0, %R0, %R4\n" +" subs %0, %0, %4\n" +" sbc %H0, %H0, %H4\n" " strexd %1, %0, %H0, [%3]\n" " teq %1, #0\n" " bne 1b" @@ -357,10 +374,9 @@ static inline long long atomic64_sub_return(long long i, atomic64_t *v) return result; } -static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old, - long long new) +static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new) { - long long oldval; + u64 oldval; unsigned long res; smp_mb(); @@ -382,9 +398,9 @@ static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old, return oldval; } -static inline long long atomic64_xchg(atomic64_t *ptr, long long new) +static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new) { - long long result; + u64 result; unsigned long tmp; smp_mb(); @@ -403,18 +419,18 @@ static inline long long atomic64_xchg(atomic64_t *ptr, long long new) return result; } -static inline long long atomic64_dec_if_positive(atomic64_t *v) +static inline u64 atomic64_dec_if_positive(atomic64_t *v) { - long long result; + u64 result; unsigned long tmp; smp_mb(); __asm__ __volatile__("@ atomic64_dec_if_positive\n" "1: ldrexd %0, %H0, [%3]\n" -" subs %Q0, %Q0, #1\n" -" sbc %R0, %R0, #0\n" -" teq %R0, #0\n" +" subs %0, %0, #1\n" +" sbc %H0, %H0, #0\n" +" teq %H0, #0\n" " bmi 2f\n" " strexd %1, %0, %H0, [%3]\n" " teq %1, #0\n" @@ -429,9 +445,9 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v) return result; } -static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) +static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u) { - long long val; + u64 val; unsigned long tmp; int ret = 1; @@ -443,8 +459,8 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) " teqeq %H0, %H5\n" " moveq %1, #0\n" " beq 2f\n" -" adds %Q0, %Q0, %Q6\n" -" adc %R0, %R0, %R6\n" +" adds %0, %0, %6\n" +" adc %H0, %H0, %H6\n" " strexd %2, %0, %H0, [%4]\n" " teq %2, #0\n" " bne 1b\n" diff --git a/arch/arm/include/asm/bL_switcher.h b/arch/arm/include/asm/bL_switcher.h deleted file mode 100644 index 1714800..0000000 --- a/arch/arm/include/asm/bL_switcher.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * arch/arm/include/asm/bL_switcher.h - * - * Created by: Nicolas Pitre, April 2012 - * Copyright: (C) 2012-2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ASM_BL_SWITCHER_H -#define ASM_BL_SWITCHER_H - -#include <linux/compiler.h> -#include <linux/types.h> - -typedef void (*bL_switch_completion_handler)(void *cookie); - -int bL_switch_request_cb(unsigned int cpu, unsigned int new_cluster_id, - bL_switch_completion_handler completer, - void *completer_cookie); -static inline int bL_switch_request(unsigned int cpu, unsigned int new_cluster_id) -{ - return bL_switch_request_cb(cpu, new_cluster_id, NULL, NULL); -} - -/* - * Register here to be notified about runtime enabling/disabling of - * the switcher. - * - * The notifier chain is called with the switcher activation lock held: - * the switcher will not be enabled or disabled during callbacks. - * Callbacks must not call bL_switcher_{get,put}_enabled(). - */ -#define BL_NOTIFY_PRE_ENABLE 0 -#define BL_NOTIFY_POST_ENABLE 1 -#define BL_NOTIFY_PRE_DISABLE 2 -#define BL_NOTIFY_POST_DISABLE 3 - -#ifdef CONFIG_BL_SWITCHER - -int bL_switcher_register_notifier(struct notifier_block *nb); -int bL_switcher_unregister_notifier(struct notifier_block *nb); - -/* - * Use these functions to temporarily prevent enabling/disabling of - * the switcher. - * bL_switcher_get_enabled() returns true if the switcher is currently - * enabled. Each call to bL_switcher_get_enabled() must be followed - * by a call to bL_switcher_put_enabled(). These functions are not - * recursive. - */ -bool bL_switcher_get_enabled(void); -void bL_switcher_put_enabled(void); - -int bL_switcher_trace_trigger(void); -int bL_switcher_get_logical_index(u32 mpidr); - -#else -static inline int bL_switcher_register_notifier(struct notifier_block *nb) -{ - return 0; -} - -static inline int bL_switcher_unregister_notifier(struct notifier_block *nb) -{ - return 0; -} - -static inline bool bL_switcher_get_enabled(void) { return false; } -static inline void bL_switcher_put_enabled(void) { } -static inline int bL_switcher_trace_trigger(void) { return 0; } -static inline int bL_switcher_get_logical_index(u32 mpidr) { return -EUNATCH; } -#endif /* CONFIG_BL_SWITCHER */ - -#endif diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h index b274bde..7af5c6c 100644 --- a/arch/arm/include/asm/bug.h +++ b/arch/arm/include/asm/bug.h @@ -2,8 +2,6 @@ #define _ASMARM_BUG_H #include <linux/linkage.h> -#include <linux/types.h> -#include <asm/opcodes.h> #ifdef CONFIG_BUG @@ -14,10 +12,10 @@ */ #ifdef CONFIG_THUMB2_KERNEL #define BUG_INSTR_VALUE 0xde02 -#define BUG_INSTR(__value) __inst_thumb16(__value) +#define BUG_INSTR_TYPE ".hword " #else #define BUG_INSTR_VALUE 0xe7f001f2 -#define BUG_INSTR(__value) __inst_arm(__value) +#define BUG_INSTR_TYPE ".word " #endif @@ -35,7 +33,7 @@ #define __BUG(__file, __line, __value) \ do { \ - asm volatile("1:\t" BUG_INSTR(__value) "\n" \ + asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \ ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \ "2:\t.asciz " #__file "\n" \ ".popsection\n" \ @@ -50,7 +48,7 @@ do { \ #define __BUG(__file, __line, __value) \ do { \ - asm volatile(BUG_INSTR(__value) "\n"); \ + asm volatile(BUG_INSTR_TYPE #__value); \ unreachable(); \ } while (0) #endif /* CONFIG_DEBUG_BUGVERBOSE */ diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index ee753f1..15f2d5b 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -435,50 +435,4 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) #define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr)) #define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr)) -/* - * Disabling cache access for one CPU in an ARMv7 SMP system is tricky. - * To do so we must: - * - * - Clear the SCTLR.C bit to prevent further cache allocations - * - Flush the desired level of cache - * - Clear the ACTLR "SMP" bit to disable local coherency - * - * ... and so without any intervening memory access in between those steps, - * not even to the stack. - * - * WARNING -- After this has been called: - * - * - No ldrex/strex (and similar) instructions must be used. - * - The CPU is obviously no longer coherent with the other CPUs. - * - This is unlikely to work as expected if Linux is running non-secure. - * - * Note: - * - * - This is known to apply to several ARMv7 processor implementations, - * however some exceptions may exist. Caveat emptor. - * - * - The clobber list is dictated by the call to v7_flush_dcache_*. - * fp is preserved to the stack explicitly prior disabling the cache - * since adding it to the clobber list is incompatible with having - * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering - * trampoline are inserted by the linker and to keep sp 64-bit aligned. - */ -#define v7_exit_coherency_flush(level) \ - asm volatile( \ - "stmfd sp!, {fp, ip} \n\t" \ - "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ - "bic r0, r0, #"__stringify(CR_C)" \n\t" \ - "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \ - "isb \n\t" \ - "bl v7_flush_dcache_"__stringify(level)" \n\t" \ - "clrex \n\t" \ - "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \ - "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \ - "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \ - "isb \n\t" \ - "dsb \n\t" \ - "ldmfd sp!, {fp, ip}" \ - : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ - "r9","r10","lr","memory" ) - #endif diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index df2fbba..4f009c1 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -223,42 +223,6 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, return ret; } -static inline unsigned long long __cmpxchg64(unsigned long long *ptr, - unsigned long long old, - unsigned long long new) -{ - unsigned long long oldval; - unsigned long res; - - __asm__ __volatile__( -"1: ldrexd %1, %H1, [%3]\n" -" teq %1, %4\n" -" teqeq %H1, %H4\n" -" bne 2f\n" -" strexd %0, %5, %H5, [%3]\n" -" teq %0, #0\n" -" bne 1b\n" -"2:" - : "=&r" (res), "=&r" (oldval), "+Qo" (*ptr) - : "r" (ptr), "r" (old), "r" (new) - : "cc"); - - return oldval; -} - -static inline unsigned long long __cmpxchg64_mb(unsigned long long *ptr, - unsigned long long old, - unsigned long long new) -{ - unsigned long long ret; - - smp_mb(); - ret = __cmpxchg64(ptr, old, new); - smp_mb(); - - return ret; -} - #define cmpxchg_local(ptr,o,n) \ ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \ (unsigned long)(o), \ @@ -266,16 +230,18 @@ static inline unsigned long long __cmpxchg64_mb(unsigned long long *ptr, sizeof(*(ptr)))) #define cmpxchg64(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#define cmpxchg64_relaxed(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg64((ptr), \ - (unsigned long long)(o), \ - (unsigned long long)(n))) - -#define cmpxchg64_local(ptr, o, n) cmpxchg64_relaxed((ptr), (o), (n)) + ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr), \ + atomic64_t, \ + counter), \ + (unsigned long long)(o), \ + (unsigned long long)(n))) + +#define cmpxchg64_local(ptr, o, n) \ + ((__typeof__(*(ptr)))local64_cmpxchg(container_of((ptr), \ + local64_t, \ + a), \ + (unsigned long long)(o), \ + (unsigned long long)(n))) #endif /* __LINUX_ARM_ARCH__ >= 6 */ diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index acdde76..9672e97 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -10,7 +10,6 @@ #define CPUID_TLBTYPE 3 #define CPUID_MPUIR 4 #define CPUID_MPIDR 5 -#define CPUID_REVIDR 6 #ifdef CONFIG_CPU_V7M #define CPUID_EXT_PFR0 0x40 diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index e701a4d..5b579b9 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -11,28 +11,17 @@ #include <asm-generic/dma-coherent.h> #include <asm/memory.h> -#include <xen/xen.h> -#include <asm/xen/hypervisor.h> - #define DMA_ERROR_CODE (~0) extern struct dma_map_ops arm_dma_ops; extern struct dma_map_ops arm_coherent_dma_ops; -static inline struct dma_map_ops *__generic_dma_ops(struct device *dev) +static inline struct dma_map_ops *get_dma_ops(struct device *dev) { if (dev && dev->archdata.dma_ops) return dev->archdata.dma_ops; return &arm_dma_ops; } -static inline struct dma_map_ops *get_dma_ops(struct device *dev) -{ - if (xen_initial_domain()) - return xen_dma_ops; - else - return __generic_dma_ops(dev); -} - static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops) { BUG_ON(!dev); @@ -75,7 +64,6 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) { return (dma_addr_t)__virt_to_bus((unsigned long)(addr)); } - #else static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn) { @@ -98,46 +86,6 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) } #endif -/* The ARM override for dma_max_pfn() */ -static inline unsigned long dma_max_pfn(struct device *dev) -{ - return PHYS_PFN_OFFSET + dma_to_pfn(dev, *dev->dma_mask); -} -#define dma_max_pfn(dev) dma_max_pfn(dev) - -static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) -{ - unsigned int offset = paddr & ~PAGE_MASK; - return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset; -} - -static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr) -{ - unsigned int offset = dev_addr & ~PAGE_MASK; - return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset; -} - -static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) -{ - u64 limit, mask; - - if (!dev->dma_mask) - return 0; - - mask = *dev->dma_mask; - - limit = (mask + 1) & ~mask; - if (limit && size > limit) - return 0; - - if ((addr | (addr + size - 1)) & ~mask) - return 0; - - return 1; -} - -static inline void dma_mark_clean(void *addr, size_t size) { } - /* * DMA errors are defined by all-bits-set in the DMA address. */ diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index fe3ea77..2740c2a 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -5,7 +5,7 @@ #include <linux/threads.h> #include <asm/irq.h> -#define NR_IPI 8 +#define NR_IPI 6 typedef struct { unsigned int __softirq_pending; diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index ad774f3..0cf7a6b 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -24,8 +24,8 @@ #define TRACER_TIMEOUT 10000 #define etm_writel(t, v, x) \ - (writel_relaxed((v), (t)->etm_regs + (x))) -#define etm_readl(t, x) (readl_relaxed((t)->etm_regs + (x))) + (__raw_writel((v), (t)->etm_regs + (x))) +#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x))) /* CoreSight Management Registers */ #define CSMR_LOCKACCESS 0xfb0 @@ -142,8 +142,8 @@ #define ETBFF_TRIGFL BIT(10) #define etb_writel(t, v, x) \ - (writel_relaxed((v), (t)->etb_regs + (x))) -#define etb_readl(t, x) (readl_relaxed((t)->etb_regs + (x))) + (__raw_writel((v), (t)->etb_regs + (x))) +#define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x))) #define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) #define etm_unlock(t) \ diff --git a/arch/arm/include/asm/hardware/iop3xx-adma.h b/arch/arm/include/asm/hardware/iop3xx-adma.h index 240b29e..9b28f12 100644 --- a/arch/arm/include/asm/hardware/iop3xx-adma.h +++ b/arch/arm/include/asm/hardware/iop3xx-adma.h @@ -393,6 +393,36 @@ static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, return slot_cnt; } +static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc) +{ + return 0; +} + +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->dest_addr; + case AAU_ID: + return hw_desc.aau->dest_addr; + default: + BUG(); + } + return 0; +} + + +static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + BUG(); + return 0; +} + static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) { diff --git a/arch/arm/include/asm/hardware/iop3xx-gpio.h b/arch/arm/include/asm/hardware/iop3xx-gpio.h new file mode 100644 index 0000000..9eda7dc --- /dev/null +++ b/arch/arm/include/asm/hardware/iop3xx-gpio.h @@ -0,0 +1,75 @@ +/* + * arch/arm/include/asm/hardware/iop3xx-gpio.h + * + * IOP3xx GPIO wrappers + * + * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org> + * Based on IXP4XX gpio.h file + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H +#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H + +#include <mach/hardware.h> +#include <asm-generic/gpio.h> + +#define __ARM_GPIOLIB_COMPLEX + +#define IOP3XX_N_GPIOS 8 + +static inline int gpio_get_value(unsigned gpio) +{ + if (gpio > IOP3XX_N_GPIOS) + return __gpio_get_value(gpio); + + return gpio_line_get(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (gpio > IOP3XX_N_GPIOS) { + __gpio_set_value(gpio, value); + return; + } + gpio_line_set(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + if (gpio < IOP3XX_N_GPIOS) + return 0; + else + return __gpio_cansleep(gpio); +} + +/* + * The GPIOs are not generating any interrupt + * Note : manuals are not clear about this + */ +static inline int gpio_to_irq(int gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(int gpio) +{ + return -EINVAL; +} + +#endif + diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 2594a95..423744b 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -18,9 +18,16 @@ /* * IOP3XX GPIO handling */ +#define GPIO_IN 0 +#define GPIO_OUT 1 +#define GPIO_LOW 0 +#define GPIO_HIGH 1 #define IOP3XX_GPIO_LINE(x) (x) #ifndef __ASSEMBLY__ +extern void gpio_line_config(int line, int direction); +extern int gpio_line_get(int line); +extern void gpio_line_set(int line, int value); extern int init_atu; extern int iop3xx_get_init_atu(void); #endif @@ -161,6 +168,11 @@ extern int iop3xx_get_init_atu(void); /* PERCR0 DOESN'T EXIST - index from 1! */ #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) +/* General Purpose I/O */ +#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000) +#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004) +#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008) + /* Timers */ #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h index 250760e..122f86d 100644 --- a/arch/arm/include/asm/hardware/iop_adma.h +++ b/arch/arm/include/asm/hardware/iop_adma.h @@ -82,6 +82,8 @@ struct iop_adma_chan { * @slot_cnt: total slots used in an transaction (group of operations) * @slots_per_op: number of slots per operation * @idx: pool index + * @unmap_src_cnt: number of xor sources + * @unmap_len: transaction bytecount * @tx_list: list of descriptors that are associated with one operation * @async_tx: support for the async_tx api * @group_list: list of slots that make up a multi-descriptor transaction @@ -97,6 +99,8 @@ struct iop_adma_desc_slot { u16 slot_cnt; u16 slots_per_op; u16 idx; + u16 unmap_src_cnt; + size_t unmap_len; struct list_head tx_list; struct dma_async_tx_descriptor async_tx; union { diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 3c597c2..d070741 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -24,11 +24,9 @@ #ifdef __KERNEL__ #include <linux/types.h> -#include <linux/blk_types.h> #include <asm/byteorder.h> #include <asm/memory.h> #include <asm-generic/pci_iomap.h> -#include <xen/xen.h> /* * ISA I/O bus memory addresses are 1:1 with the physical address. @@ -374,13 +372,6 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define BIOVEC_MERGEABLE(vec1, vec2) \ ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) -struct bio_vec; -extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, - const struct bio_vec *vec2); -#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ - (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ - (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) - #ifdef CONFIG_MMU #define ARCH_HAS_VALID_PHYS_ADDR_RANGE extern int valid_phys_addr_range(phys_addr_t addr, size_t size); diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h index 0a9d5dd..48066ce 100644 --- a/arch/arm/include/asm/kgdb.h +++ b/arch/arm/include/asm/kgdb.h @@ -11,7 +11,6 @@ #define __ARM_KGDB_H__ #include <linux/ptrace.h> -#include <asm/opcodes.h> /* * GDB assumes that we're a user process being debugged, so @@ -42,7 +41,7 @@ static inline void arch_kgdb_breakpoint(void) { - asm(__inst_arm(0xe7ffdeff)); + asm(".word 0xe7ffdeff"); } extern void kgdb_handle_bus_error(void); diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h index 1d3153c..64e9696 100644 --- a/arch/arm/include/asm/kvm_arm.h +++ b/arch/arm/include/asm/kvm_arm.h @@ -57,7 +57,6 @@ * TSC: Trap SMC * TSW: Trap cache operations by set/way * TWI: Trap WFI - * TWE: Trap WFE * TIDCP: Trap L2CTLR/L2ECTLR * BSU_IS: Upgrade barriers to the inner shareable domain * FB: Force broadcast of all maintainance operations @@ -68,7 +67,7 @@ */ #define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ - HCR_TWE | HCR_SWIO | HCR_TIDCP) + HCR_SWIO | HCR_TIDCP) #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) /* System Control Register (SCTLR) bits */ @@ -96,12 +95,12 @@ #define TTBCR_IRGN1 (3 << 24) #define TTBCR_EPD1 (1 << 23) #define TTBCR_A1 (1 << 22) -#define TTBCR_T1SZ (7 << 16) +#define TTBCR_T1SZ (3 << 16) #define TTBCR_SH0 (3 << 12) #define TTBCR_ORGN0 (3 << 10) #define TTBCR_IRGN0 (3 << 8) #define TTBCR_EPD0 (1 << 7) -#define TTBCR_T0SZ (7 << 0) +#define TTBCR_T0SZ 3 #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) /* Hyp System Trap Register */ @@ -209,8 +208,6 @@ #define HSR_EC_DABT (0x24) #define HSR_EC_DABT_HYP (0x25) -#define HSR_WFI_IS_WFE (1U << 0) - #define HSR_HVC_IMM_MASK ((1UL << 16) - 1) #define HSR_DABT_S1PTW (1U << 7) diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h index 661da11..a2f43dd 100644 --- a/arch/arm/include/asm/kvm_asm.h +++ b/arch/arm/include/asm/kvm_asm.h @@ -39,7 +39,7 @@ #define c6_IFAR 17 /* Instruction Fault Address Register */ #define c7_PAR 18 /* Physical Address Register */ #define c7_PAR_high 19 /* PAR top 32 bits */ -#define c9_L2CTLR 20 /* Cortex A15/A7 L2 Control Register */ +#define c9_L2CTLR 20 /* Cortex A15 L2 Control Register */ #define c10_PRRR 21 /* Primary Region Remap Register */ #define c10_NMRR 22 /* Normal Memory Remap Register */ #define c12_VBAR 23 /* Vector Base Address Register */ diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h index 0fa90c9..a464e8d 100644 --- a/arch/arm/include/asm/kvm_emulate.h +++ b/arch/arm/include/asm/kvm_emulate.h @@ -157,55 +157,4 @@ static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu) return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK; } -static inline unsigned long kvm_vcpu_get_mpidr(struct kvm_vcpu *vcpu) -{ - return vcpu->arch.cp15[c0_MPIDR]; -} - -static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) -{ - *vcpu_cpsr(vcpu) |= PSR_E_BIT; -} - -static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) -{ - return !!(*vcpu_cpsr(vcpu) & PSR_E_BIT); -} - -static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu, - unsigned long data, - unsigned int len) -{ - if (kvm_vcpu_is_be(vcpu)) { - switch (len) { - case 1: - return data & 0xff; - case 2: - return be16_to_cpu(data & 0xffff); - default: - return be32_to_cpu(data); - } - } - - return data; /* Leave LE untouched */ -} - -static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu, - unsigned long data, - unsigned int len) -{ - if (kvm_vcpu_is_be(vcpu)) { - switch (len) { - case 1: - return data & 0xff; - case 2: - return cpu_to_be16(data & 0xffff); - default: - return cpu_to_be32(data); - } - } - - return data; /* Leave LE untouched */ -} - #endif /* __ARM_KVM_EMULATE_H__ */ diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 8a6f6db..7d22517 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -38,6 +38,11 @@ #define KVM_VCPU_MAX_FEATURES 1 +/* We don't currently support large pages. */ +#define KVM_HPAGE_GFN_SHIFT(x) 0 +#define KVM_NR_PAGE_SIZES 1 +#define KVM_PAGES_PER_HPAGE(x) (1UL<<31) + #include <kvm/arm_vgic.h> struct kvm_vcpu; @@ -149,7 +154,6 @@ struct kvm_vcpu_stat { struct kvm_vcpu_init; int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, const struct kvm_vcpu_init *init); -int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); struct kvm_one_reg; diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 77de4a4..9b28c41 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -62,12 +62,6 @@ phys_addr_t kvm_get_idmap_vector(void); int kvm_mmu_init(void); void kvm_clear_hyp_idmap(void); -static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd) -{ - *pmd = new_pmd; - flush_pmd_entry(pmd); -} - static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) { *pte = new_pte; @@ -109,15 +103,9 @@ static inline void kvm_set_s2pte_writable(pte_t *pte) pte_val(*pte) |= L_PTE_S2_RDWR; } -static inline void kvm_set_s2pmd_writable(pmd_t *pmd) -{ - pmd_val(*pmd) |= L_PMD_S2_RDWR; -} - struct kvm; -static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva, - unsigned long size) +static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn) { /* * If we are going to insert an instruction page and the icache is @@ -132,7 +120,8 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva, * need any kind of flushing (DDI 0406C.b - Page B3-1392). */ if (icache_is_pipt()) { - __cpuc_coherent_user_range(hva, hva + size); + unsigned long hva = gfn_to_hva(kvm, gfn); + __cpuc_coherent_user_range(hva, hva + PAGE_SIZE); } else if (!icache_is_vivt_asid_tagged()) { /* any kind of VIPT cache */ __flush_icache_all(); diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 17a3fa2..402a2bc 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -49,7 +49,6 @@ struct machine_desc { bool (*smp_init)(void); void (*fixup)(struct tag *, char **, struct meminfo *); - void (*init_meminfo)(void); void (*reserve)(void);/* reserve mem blocks */ void (*map_io)(void);/* IO mapping function */ void (*init_early)(void); diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 7fc4278..454d642 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -106,4 +106,8 @@ extern int dc21285_setup(int nr, struct pci_sys_data *); extern void dc21285_preinit(void); extern void dc21285_postinit(void); +extern struct pci_ops via82c505_ops; +extern int via82c505_setup(int nr, struct pci_sys_data *); +extern void via82c505_init(void *sysdata); + #endif /* __ASM_MACH_PCI_H */ diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h index 608516e..fc82a88 100644 --- a/arch/arm/include/asm/mcpm.h +++ b/arch/arm/include/asm/mcpm.h @@ -42,14 +42,6 @@ extern void mcpm_entry_point(void); void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr); /* - * This sets an early poke i.e a value to be poked into some address - * from very early assembly code before the CPU is ungated. The - * address must be physical, and if 0 then nothing will happen. - */ -void mcpm_set_early_poke(unsigned cpu, unsigned cluster, - unsigned long poke_phys_addr, unsigned long poke_val); - -/* * CPU/cluster power operations API for higher subsystems to use. */ @@ -89,40 +81,10 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster); * * This will return if mcpm_platform_register() has not been called * previously in which case the caller should take appropriate action. - * - * On success, the CPU is not guaranteed to be truly halted until - * mcpm_cpu_power_down_finish() subsequently returns non-zero for the - * specified cpu. Until then, other CPUs should make sure they do not - * trash memory the target CPU might be executing/accessing. */ void mcpm_cpu_power_down(void); /** - * mcpm_cpu_power_down_finish - wait for a specified CPU to halt, and - * make sure it is powered off - * - * @cpu: CPU number within given cluster - * @cluster: cluster number for the CPU - * - * Call this function to ensure that a pending powerdown has taken - * effect and the CPU is safely parked before performing non-mcpm - * operations that may affect the CPU (such as kexec trashing the - * kernel text). - * - * It is *not* necessary to call this function if you only need to - * serialise a pending powerdown with mcpm_cpu_power_up() or a wakeup - * event. - * - * Do not call this function unless the specified CPU has already - * called mcpm_cpu_power_down() or has committed to doing so. - * - * @return: - * - zero if the CPU is in a safely parked state - * - nonzero otherwise (e.g., timeout) - */ -int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster); - -/** * mcpm_cpu_suspend - bring the calling CPU in a suspended state * * @expected_residency: duration in microseconds the CPU is expected @@ -164,7 +126,6 @@ int mcpm_cpu_powered_up(void); struct mcpm_platform_ops { int (*power_up)(unsigned int cpu, unsigned int cluster); void (*power_down)(void); - int (*power_down_finish)(unsigned int cpu, unsigned int cluster); void (*suspend)(u64); void (*powered_up)(void); }; diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 9ecccc8..e750a93 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -172,13 +172,8 @@ * so that all we need to do is modify the 8-bit constant field. */ #define __PV_BITS_31_24 0x81000000 -#define __PV_BITS_7_0 0x81 - -extern u64 __pv_phys_offset; -extern u64 __pv_offset; -extern void fixup_pv_table(const void *, unsigned long); -extern const void *__pv_table_begin, *__pv_table_end; +extern unsigned long __pv_phys_offset; #define PHYS_OFFSET __pv_phys_offset #define __pv_stub(from,to,instr,type) \ @@ -190,65 +185,22 @@ extern const void *__pv_table_begin, *__pv_table_end; : "=r" (to) \ : "r" (from), "I" (type)) -#define __pv_stub_mov_hi(t) \ - __asm__ volatile("@ __pv_stub_mov\n" \ - "1: mov %R0, %1\n" \ - " .pushsection .pv_table,\"a\"\n" \ - " .long 1b\n" \ - " .popsection\n" \ - : "=r" (t) \ - : "I" (__PV_BITS_7_0)) - -#define __pv_add_carry_stub(x, y) \ - __asm__ volatile("@ __pv_add_carry_stub\n" \ - "1: adds %Q0, %1, %2\n" \ - " adc %R0, %R0, #0\n" \ - " .pushsection .pv_table,\"a\"\n" \ - " .long 1b\n" \ - " .popsection\n" \ - : "+r" (y) \ - : "r" (x), "I" (__PV_BITS_31_24) \ - : "cc") - -static inline phys_addr_t __virt_to_phys(unsigned long x) +static inline unsigned long __virt_to_phys(unsigned long x) { - phys_addr_t t; - - if (sizeof(phys_addr_t) == 4) { - __pv_stub(x, t, "add", __PV_BITS_31_24); - } else { - __pv_stub_mov_hi(t); - __pv_add_carry_stub(x, t); - } + unsigned long t; + __pv_stub(x, t, "add", __PV_BITS_31_24); return t; } -static inline unsigned long __phys_to_virt(phys_addr_t x) +static inline unsigned long __phys_to_virt(unsigned long x) { unsigned long t; - - /* - * 'unsigned long' cast discard upper word when - * phys_addr_t is 64 bit, and makes sure that inline - * assembler expression receives 32 bit argument - * in place where 'r' 32 bit operand is expected. - */ - __pv_stub((unsigned long) x, t, "sub", __PV_BITS_31_24); + __pv_stub(x, t, "sub", __PV_BITS_31_24); return t; } - #else - -static inline phys_addr_t __virt_to_phys(unsigned long x) -{ - return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET; -} - -static inline unsigned long __phys_to_virt(phys_addr_t x) -{ - return x - PHYS_OFFSET + PAGE_OFFSET; -} - +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) #endif #endif #endif /* __ASSEMBLY__ */ @@ -286,33 +238,16 @@ static inline phys_addr_t virt_to_phys(const volatile void *x) static inline void *phys_to_virt(phys_addr_t x) { - return (void *)__phys_to_virt(x); + return (void *)(__phys_to_virt((unsigned long)(x))); } /* * Drivers should NOT use these either. */ #define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x))) +#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) -extern phys_addr_t (*arch_virt_to_idmap)(unsigned long x); - -/* - * These are for systems that have a hardware interconnect supported alias of - * physical memory for idmap purposes. Most cases should leave these - * untouched. - */ -static inline phys_addr_t __virt_to_idmap(unsigned long x) -{ - if (arch_virt_to_idmap) - return arch_virt_to_idmap(x); - else - return __virt_to_phys(x); -} - -#define virt_to_idmap(x) __virt_to_idmap((unsigned long)(x)) - /* * Virtual <-> DMA view memory address translations * Again, these are *only* valid on the kernel direct mapped RAM diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index 64fd151..6f18da0 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -16,7 +16,7 @@ typedef struct { #ifdef CONFIG_CPU_HAS_ASID #define ASID_BITS 8 #define ASID_MASK ((~0ULL) << ASID_BITS) -#define ASID(mm) ((unsigned int)((mm)->context.id.counter & ~ASID_MASK)) +#define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK) #else #define ASID(mm) (0) #endif diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 78a7793..943504f 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -102,14 +102,12 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) #else pte = alloc_pages(PGALLOC_GFP, 0); #endif - if (!pte) - return NULL; - if (!PageHighMem(pte)) - clean_pte_table(page_address(pte)); - if (!pgtable_page_ctor(pte)) { - __free_page(pte); - return NULL; + if (pte) { + if (!PageHighMem(pte)) + clean_pte_table(page_address(pte)); + pgtable_page_ctor(pte); } + return pte; } diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 86a659a..f97ee02 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -181,13 +181,6 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) -/* - * We don't have huge page support for short descriptors, for the moment - * define empty stubs for use by pin_page_for_write. - */ -#define pmd_hugewillfault(pmd) (0) -#define pmd_thp_or_huge(pmd) (0) - #endif /* __ASSEMBLY__ */ #endif /* _ASM_PGTABLE_2LEVEL_H */ diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 4f95039..5689c18 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -126,8 +126,6 @@ #define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ #define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ -#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ - /* * Hyp-mode PL2 PTE definitions for LPAE. */ @@ -208,9 +206,6 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) #define __HAVE_ARCH_PMD_WRITE #define pmd_write(pmd) (!(pmd_val(pmd) & PMD_SECT_RDONLY)) -#define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd)) -#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) - #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) #define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING) diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 1571d12..be956db 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -61,7 +61,7 @@ extern void __pgd_error(const char *file, int line, pgd_t); * mapping to be mapped at. This is particularly important for * non-high vector CPUs. */ -#define FIRST_USER_ADDRESS (PAGE_SIZE * 2) +#define FIRST_USER_ADDRESS PAGE_SIZE /* * Use TASK_SIZE as the ceiling argument for free_pgtables() and diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index c3d5fc1..413f387 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -22,7 +22,6 @@ #include <asm/hw_breakpoint.h> #include <asm/ptrace.h> #include <asm/types.h> -#include <asm/unified.h> #ifdef __KERNEL__ #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ @@ -88,17 +87,6 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) task_pt_regs(tsk)->ARM_pc #define KSTK_ESP(tsk) task_pt_regs(tsk)->ARM_sp -#ifdef CONFIG_SMP -#define __ALT_SMP_ASM(smp, up) \ - "9998: " smp "\n" \ - " .pushsection \".alt.smp.init\", \"a\"\n" \ - " .long 9998b\n" \ - " " up "\n" \ - " .popsection\n" -#else -#define __ALT_SMP_ASM(smp, up) up -#endif - /* * Prefetching support - only ARMv5. */ @@ -109,22 +97,17 @@ static inline void prefetch(const void *ptr) { __asm__ __volatile__( "pld\t%a0" - :: "p" (ptr)); + : + : "p" (ptr) + : "cc"); } -#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) #define ARCH_HAS_PREFETCHW -static inline void prefetchw(const void *ptr) -{ - __asm__ __volatile__( - ".arch_extension mp\n" - __ALT_SMP_ASM( - WASM(pldw) "\t%a0", - WASM(pld) "\t%a0" - ) - :: "p" (ptr)); -} -#endif +#define prefetchw(ptr) prefetch(ptr) + +#define ARCH_HAS_SPINLOCK_PREFETCH +#define spin_lock_prefetch(x) do { } while (0) + #endif #define HAVE_ARCH_PICK_MMAP_LAYOUT diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h index b681575..4a2985e 100644 --- a/arch/arm/include/asm/prom.h +++ b/arch/arm/include/asm/prom.h @@ -11,6 +11,8 @@ #ifndef __ASMARM_PROM_H #define __ASMARM_PROM_H +#define HAVE_ARCH_DEVTREE_FIXUPS + #ifdef CONFIG_OF extern const struct machine_desc *setup_machine_fdt(unsigned int dt_phys); diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h new file mode 100644 index 0000000..2389b71 --- /dev/null +++ b/arch/arm/include/asm/sched_clock.h @@ -0,0 +1,4 @@ +/* You shouldn't include this file. Use linux/sched_clock.h instead. + * Temporary file until all asm/sched_clock.h users are gone + */ +#include <linux/sched_clock.h> diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 8d6a089..c50f0560 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -49,7 +49,7 @@ extern struct meminfo meminfo; #define bank_phys_end(bank) ((bank)->start + (bank)->size) #define bank_phys_size(bank) (bank)->size -extern int arm_add_memory(u64 start, u64 size); +extern int arm_add_memory(phys_addr_t start, phys_addr_t size); extern void early_print(const char *str, ...); extern void dump_machine_table(void); diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 22a3b9b..a8cae71c 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -84,8 +84,6 @@ extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); -extern int register_ipi_completion(struct completion *completion, int cpu); - struct smp_operations { #ifdef CONFIG_SMP /* diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index ef3c607..4f2c280 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -5,13 +5,21 @@ #error SMP not supported on pre-ARMv6 CPUs #endif -#include <linux/prefetch.h> +#include <asm/processor.h> /* * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K * extensions, so when running on UP, we have to patch these instructions away. */ +#define ALT_SMP(smp, up) \ + "9998: " smp "\n" \ + " .pushsection \".alt.smp.init\", \"a\"\n" \ + " .long 9998b\n" \ + " " up "\n" \ + " .popsection\n" + #ifdef CONFIG_THUMB2_KERNEL +#define SEV ALT_SMP("sev.w", "nop.w") /* * For Thumb-2, special care is needed to ensure that the conditional WFE * instruction really does assemble to exactly 4 bytes (as required by @@ -23,18 +31,17 @@ * the assembler won't change IT instructions which are explicitly present * in the input. */ -#define WFE(cond) __ALT_SMP_ASM( \ +#define WFE(cond) ALT_SMP( \ "it " cond "\n\t" \ "wfe" cond ".n", \ \ "nop.w" \ ) #else -#define WFE(cond) __ALT_SMP_ASM("wfe" cond, "nop") +#define SEV ALT_SMP("sev", "nop") +#define WFE(cond) ALT_SMP("wfe" cond, "nop") #endif -#define SEV __ALT_SMP_ASM(WASM(sev), WASM(nop)) - static inline void dsb_sev(void) { #if __LINUX_ARM_ARCH__ >= 7 @@ -70,7 +77,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) u32 newval; arch_spinlock_t lockval; - prefetchw(&lock->slock); __asm__ __volatile__( "1: ldrex %0, [%3]\n" " add %1, %0, %4\n" @@ -94,7 +100,6 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock) unsigned long contended, res; u32 slock; - prefetchw(&lock->slock); do { __asm__ __volatile__( " ldrex %0, [%3]\n" @@ -122,14 +127,10 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock) dsb_sev(); } -static inline int arch_spin_value_unlocked(arch_spinlock_t lock) -{ - return lock.tickets.owner == lock.tickets.next; -} - static inline int arch_spin_is_locked(arch_spinlock_t *lock) { - return !arch_spin_value_unlocked(ACCESS_ONCE(*lock)); + struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets); + return tickets.owner != tickets.next; } static inline int arch_spin_is_contended(arch_spinlock_t *lock) @@ -151,7 +152,6 @@ static inline void arch_write_lock(arch_rwlock_t *rw) { unsigned long tmp; - prefetchw(&rw->lock); __asm__ __volatile__( "1: ldrex %0, [%1]\n" " teq %0, #0\n" @@ -170,7 +170,6 @@ static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned long contended, res; - prefetchw(&rw->lock); do { __asm__ __volatile__( " ldrex %0, [%2]\n" @@ -204,7 +203,7 @@ static inline void arch_write_unlock(arch_rwlock_t *rw) } /* write_can_lock - would write_trylock() succeed? */ -#define arch_write_can_lock(x) (ACCESS_ONCE((x)->lock) == 0) +#define arch_write_can_lock(x) ((x)->lock == 0) /* * Read locks are a bit more hairy: @@ -222,7 +221,6 @@ static inline void arch_read_lock(arch_rwlock_t *rw) { unsigned long tmp, tmp2; - prefetchw(&rw->lock); __asm__ __volatile__( "1: ldrex %0, [%2]\n" " adds %0, %0, #1\n" @@ -243,7 +241,6 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) smp_mb(); - prefetchw(&rw->lock); __asm__ __volatile__( "1: ldrex %0, [%2]\n" " sub %0, %0, #1\n" @@ -262,7 +259,6 @@ static inline int arch_read_trylock(arch_rwlock_t *rw) { unsigned long contended, res; - prefetchw(&rw->lock); do { __asm__ __volatile__( " ldrex %0, [%2]\n" @@ -284,7 +280,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw) } /* read_can_lock - would read_trylock() succeed? */ -#define arch_read_can_lock(x) (ACCESS_ONCE((x)->lock) < 0x80000000) +#define arch_read_can_lock(x) ((x)->lock < 0x80000000) #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h index 47663fc..b262d2f 100644 --- a/arch/arm/include/asm/spinlock_types.h +++ b/arch/arm/include/asm/spinlock_types.h @@ -25,7 +25,7 @@ typedef struct { #define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } } typedef struct { - u32 lock; + volatile unsigned int lock; } arch_rwlock_t; #define __ARCH_RW_LOCK_UNLOCKED { 0 } diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 71a06b2..df5e13d 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -141,6 +141,12 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *, #endif /* + * We use bit 30 of the preempt_count to indicate that kernel + * preemption is occurring. See <asm/hardirq.h>. + */ +#define PREEMPT_ACTIVE 0x40000000 + +/* * thread information flags: * TIF_SYSCALL_TRACE - syscall trace active * TIF_SYSCAL_AUDIT - syscall auditing active diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index def9e57..3896026 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -560,6 +560,37 @@ static inline void __flush_bp_all(void) asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); } +#include <asm/cputype.h> +#ifdef CONFIG_ARM_ERRATA_798181 +static inline int erratum_a15_798181(void) +{ + unsigned int midr = read_cpuid_id(); + + /* Cortex-A15 r0p0..r3p2 affected */ + if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) + return 0; + return 1; +} + +static inline void dummy_flush_tlb_a15_erratum(void) +{ + /* + * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. + */ + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); + dsb(ish); +} +#else +static inline int erratum_a15_798181(void) +{ + return 0; +} + +static inline void dummy_flush_tlb_a15_erratum(void) +{ +} +#endif + /* * flush_pmd_entry * @@ -666,21 +697,4 @@ extern void flush_bp_all(void); #endif -#ifndef __ASSEMBLY__ -#ifdef CONFIG_ARM_ERRATA_798181 -extern void erratum_a15_798181_init(void); -#else -static inline void erratum_a15_798181_init(void) {} -#endif -extern bool (*erratum_a15_798181_handler)(void); - -static inline bool erratum_a15_798181(void) -{ - if (unlikely(IS_ENABLED(CONFIG_ARM_ERRATA_798181) && - erratum_a15_798181_handler)) - return erratum_a15_798181_handler(); - return false; -} -#endif - #endif diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h index b88beab..f5989f4 100644 --- a/arch/arm/include/asm/unified.h +++ b/arch/arm/include/asm/unified.h @@ -38,8 +38,6 @@ #ifdef __ASSEMBLY__ #define W(instr) instr.w #define BSYM(sym) sym + 1 -#else -#define WASM(instr) #instr ".w" #endif #else /* !CONFIG_THUMB2_KERNEL */ @@ -52,8 +50,6 @@ #ifdef __ASSEMBLY__ #define W(instr) instr #define BSYM(sym) sym -#else -#define WASM(instr) #instr #endif #endif /* CONFIG_THUMB2_KERNEL */ diff --git a/arch/arm/include/asm/xen/hypervisor.h b/arch/arm/include/asm/xen/hypervisor.h index 1317ee4..d7ab99a 100644 --- a/arch/arm/include/asm/xen/hypervisor.h +++ b/arch/arm/include/asm/xen/hypervisor.h @@ -16,6 +16,4 @@ static inline enum paravirt_lazy_mode paravirt_get_lazy_mode(void) return PARAVIRT_LAZY_NONE; } -extern struct dma_map_ops *xen_dma_ops; - #endif /* _ASM_ARM_XEN_HYPERVISOR_H */ diff --git a/arch/arm/include/asm/xen/page-coherent.h b/arch/arm/include/asm/xen/page-coherent.h deleted file mode 100644 index 1109017..0000000 --- a/arch/arm/include/asm/xen/page-coherent.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef _ASM_ARM_XEN_PAGE_COHERENT_H -#define _ASM_ARM_XEN_PAGE_COHERENT_H - -#include <asm/page.h> -#include <linux/dma-attrs.h> -#include <linux/dma-mapping.h> - -static inline void *xen_alloc_coherent_pages(struct device *hwdev, size_t size, - dma_addr_t *dma_handle, gfp_t flags, - struct dma_attrs *attrs) -{ - return __generic_dma_ops(hwdev)->alloc(hwdev, size, dma_handle, flags, attrs); -} - -static inline void xen_free_coherent_pages(struct device *hwdev, size_t size, - void *cpu_addr, dma_addr_t dma_handle, - struct dma_attrs *attrs) -{ - __generic_dma_ops(hwdev)->free(hwdev, size, cpu_addr, dma_handle, attrs); -} - -static inline void xen_dma_map_page(struct device *hwdev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) -{ - __generic_dma_ops(hwdev)->map_page(hwdev, page, offset, size, dir, attrs); -} - -static inline void xen_dma_unmap_page(struct device *hwdev, dma_addr_t handle, - size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) -{ - if (__generic_dma_ops(hwdev)->unmap_page) - __generic_dma_ops(hwdev)->unmap_page(hwdev, handle, size, dir, attrs); -} - -static inline void xen_dma_sync_single_for_cpu(struct device *hwdev, - dma_addr_t handle, size_t size, enum dma_data_direction dir) -{ - if (__generic_dma_ops(hwdev)->sync_single_for_cpu) - __generic_dma_ops(hwdev)->sync_single_for_cpu(hwdev, handle, size, dir); -} - -static inline void xen_dma_sync_single_for_device(struct device *hwdev, - dma_addr_t handle, size_t size, enum dma_data_direction dir) -{ - if (__generic_dma_ops(hwdev)->sync_single_for_device) - __generic_dma_ops(hwdev)->sync_single_for_device(hwdev, handle, size, dir); -} -#endif /* _ASM_ARM_XEN_PAGE_COHERENT_H */ diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h index 75579a9..359a7b5 100644 --- a/arch/arm/include/asm/xen/page.h +++ b/arch/arm/include/asm/xen/page.h @@ -6,12 +6,12 @@ #include <linux/pfn.h> #include <linux/types.h> -#include <linux/dma-mapping.h> -#include <xen/xen.h> #include <xen/interface/grant_table.h> +#define pfn_to_mfn(pfn) (pfn) #define phys_to_machine_mapping_valid(pfn) (1) +#define mfn_to_pfn(mfn) (mfn) #define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) #define pte_mfn pte_pfn @@ -32,38 +32,6 @@ typedef struct xpaddr { #define INVALID_P2M_ENTRY (~0UL) -unsigned long __pfn_to_mfn(unsigned long pfn); -unsigned long __mfn_to_pfn(unsigned long mfn); -extern struct rb_root phys_to_mach; - -static inline unsigned long pfn_to_mfn(unsigned long pfn) -{ - unsigned long mfn; - - if (phys_to_mach.rb_node != NULL) { - mfn = __pfn_to_mfn(pfn); - if (mfn != INVALID_P2M_ENTRY) - return mfn; - } - - return pfn; -} - -static inline unsigned long mfn_to_pfn(unsigned long mfn) -{ - unsigned long pfn; - - if (phys_to_mach.rb_node != NULL) { - pfn = __mfn_to_pfn(mfn); - if (pfn != INVALID_P2M_ENTRY) - return pfn; - } - - return mfn; -} - -#define mfn_to_local_pfn(mfn) mfn_to_pfn(mfn) - static inline xmaddr_t phys_to_machine(xpaddr_t phys) { unsigned offset = phys.paddr & ~PAGE_MASK; @@ -108,9 +76,11 @@ static inline int m2p_remove_override(struct page *page, bool clear_pte) return 0; } -bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn); -bool __set_phys_to_machine_multi(unsigned long pfn, unsigned long mfn, - unsigned long nr_pages); +static inline bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn) +{ + BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY); + return true; +} static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn) { diff --git a/arch/arm/include/debug/efm32.S b/arch/arm/include/debug/efm32.S deleted file mode 100644 index 2265a19..0000000 --- a/arch/arm/include/debug/efm32.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2013 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define UARTn_CMD 0x000c -#define UARTn_CMD_TXEN 0x0004 - -#define UARTn_STATUS 0x0010 -#define UARTn_STATUS_TXC 0x0020 -#define UARTn_STATUS_TXBL 0x0040 - -#define UARTn_TXDATA 0x0034 - - .macro addruart, rx, tmp - ldr \rx, =(CONFIG_DEBUG_UART_PHYS) - - /* - * enable TX. The driver might disable it to save energy. We - * don't care about disabling at the end as during debug power - * consumption isn't that important. - */ - ldr \tmp, =(UARTn_CMD_TXEN) - str \tmp, [\rx, #UARTn_CMD] - .endm - - .macro senduart,rd,rx - strb \rd, [\rx, #UARTn_TXDATA] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #UARTn_STATUS] - tst \rd, #UARTn_STATUS_TXBL - beq 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, UARTn_STATUS] - tst \rd, #UARTn_STATUS_TXC - bne 1001b - .endm diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S index 9d653d4..9166e1b 100644 --- a/arch/arm/include/debug/msm.S +++ b/arch/arm/include/debug/msm.S @@ -46,11 +46,6 @@ #define MSM_DEBUG_UART_PHYS 0x16440000 #endif -#ifdef CONFIG_DEBUG_MSM8974_UART -#define MSM_DEBUG_UART_BASE 0xFA71E000 -#define MSM_DEBUG_UART_PHYS 0xF991E000 -#endif - .macro addruart, rp, rv, tmp #ifdef MSM_DEBUG_UART_PHYS ldr \rp, =MSM_DEBUG_UART_PHYS diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index 92ef808..37c6895b 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -25,14 +25,12 @@ .macro waituart,rd,rx 1001: ldr \rd, [\rx, #UART01x_FR] - ARM_BE8( rev \rd, \rd ) tst \rd, #UART01x_FR_TXFF bne 1001b .endm .macro busyuart,rd,rx 1001: ldr \rd, [\rx, #UART01x_FR] - ARM_BE8( rev \rd, \rd ) tst \rd, #UART01x_FR_BUSY bne 1001b .endm diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S deleted file mode 100644 index ba12cc4..0000000 --- a/arch/arm/include/debug/vf.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - - .macro addruart, rp, rv, tmp - ldr \rp, =0x40028000 @ physical - ldr \rv, =0xfe028000 @ virtual - .endm - - .macro senduart, rd, rx - strb \rd, [\rx, #0x7] @ Data Register - .endm - - .macro busyuart, rd, rx -1001: ldrb \rd, [\rx, #0x4] @ Status Register 1 - tst \rd, #1 << 6 @ TC - beq 1001b @ wait until transmit done - .endm - - .macro waituart,rd,rx - .endm diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index 70a1c9d..18d76fd 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -7,7 +7,6 @@ header-y += hwcap.h header-y += ioctls.h header-y += kvm_para.h header-y += mman.h -header-y += perf_regs.h header-y += posix_types.h header-y += ptrace.h header-y += setup.h diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h index 7dcc10d..6d34d08 100644 --- a/arch/arm/include/uapi/asm/hwcap.h +++ b/arch/arm/include/uapi/asm/hwcap.h @@ -26,6 +26,5 @@ #define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs (not 16) */ #define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) #define HWCAP_LPAE (1 << 20) -#define HWCAP_EVTSTRM (1 << 21) #endif /* _UAPI__ASMARM_HWCAP_H */ diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h index c498b60..c1ee007 100644 --- a/arch/arm/include/uapi/asm/kvm.h +++ b/arch/arm/include/uapi/asm/kvm.h @@ -63,8 +63,7 @@ struct kvm_regs { /* Supported Processor Types */ #define KVM_ARM_TARGET_CORTEX_A15 0 -#define KVM_ARM_TARGET_CORTEX_A7 1 -#define KVM_ARM_NUM_TARGETS 2 +#define KVM_ARM_NUM_TARGETS 1 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ #define KVM_ARM_DEVICE_TYPE_SHIFT 0 diff --git a/arch/arm/include/uapi/asm/perf_regs.h b/arch/arm/include/uapi/asm/perf_regs.h deleted file mode 100644 index ce59448..0000000 --- a/arch/arm/include/uapi/asm/perf_regs.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _ASM_ARM_PERF_REGS_H -#define _ASM_ARM_PERF_REGS_H - -enum perf_event_arm_regs { - PERF_REG_ARM_R0, - PERF_REG_ARM_R1, - PERF_REG_ARM_R2, - PERF_REG_ARM_R3, - PERF_REG_ARM_R4, - PERF_REG_ARM_R5, - PERF_REG_ARM_R6, - PERF_REG_ARM_R7, - PERF_REG_ARM_R8, - PERF_REG_ARM_R9, - PERF_REG_ARM_R10, - PERF_REG_ARM_FP, - PERF_REG_ARM_IP, - PERF_REG_ARM_SP, - PERF_REG_ARM_LR, - PERF_REG_ARM_PC, - PERF_REG_ARM_MAX, -}; -#endif /* _ASM_ARM_PERF_REGS_H */ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index a30fc9b..5140df5f 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -17,8 +17,7 @@ CFLAGS_REMOVE_return_address.o = -pg obj-y := elf.o entry-common.o irq.o opcodes.o \ process.o ptrace.o return_address.o \ - setup.o signal.o sigreturn_codes.o \ - stacktrace.o sys_arm.o time.o traps.o + setup.o signal.o stacktrace.o sys_arm.o time.o traps.o obj-$(CONFIG_ATAGS) += atags_parse.o obj-$(CONFIG_ATAGS_PROC) += atags_proc.o @@ -79,7 +78,6 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o -obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index 1791f12..221f07b 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/types.h> #include <linux/errno.h> +#include <linux/sched_clock.h> #include <asm/delay.h> @@ -21,6 +22,13 @@ static unsigned long arch_timer_read_counter_long(void) return arch_timer_read_counter(); } +static u32 sched_clock_mult __read_mostly; + +static unsigned long long notrace arch_timer_sched_clock(void) +{ + return arch_timer_read_counter() * sched_clock_mult; +} + static struct delay_timer arch_delay_timer; static void __init arch_timer_delay_timer_register(void) @@ -40,5 +48,11 @@ int __init arch_timer_arch_init(void) arch_timer_delay_timer_register(); + /* Cache the sched_clock multiplier to save a divide in the hot path. */ + sched_clock_mult = NSEC_PER_SEC / arch_timer_rate; + sched_clock_func = arch_timer_sched_clock; + pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n", + arch_timer_rate / 1000, sched_clock_mult); + return 0; } diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 1f031dd..60d3b73 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -155,5 +155,4 @@ EXPORT_SYMBOL(__gnu_mcount_nc); #ifdef CONFIG_ARM_PATCH_PHYS_VIRT EXPORT_SYMBOL(__pv_phys_offset); -EXPORT_SYMBOL(__pv_offset); #endif diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 739c3df..f35906b 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -174,19 +174,6 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id) return (phys_id & MPIDR_HWID_BITMASK) == cpu_logical_map(cpu); } -static const void * __init arch_get_next_mach(const char *const **match) -{ - static const struct machine_desc *mdesc = __arch_info_begin; - const struct machine_desc *m = mdesc; - - if (m >= __arch_info_end) - return NULL; - - mdesc++; - *match = m->dt_compat; - return m; -} - /** * setup_machine_fdt - Machine setup when an dtb was passed to the kernel * @dt_phys: physical address of dt blob @@ -196,7 +183,11 @@ static const void * __init arch_get_next_mach(const char *const **match) */ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) { + struct boot_param_header *devtree; const struct machine_desc *mdesc, *mdesc_best = NULL; + unsigned int score, mdesc_score = ~1; + unsigned long dt_root; + const char *model; #ifdef CONFIG_ARCH_MULTIPLATFORM DT_MACHINE_START(GENERIC_DT, "Generic DT based system") @@ -205,20 +196,32 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) mdesc_best = &__mach_desc_GENERIC_DT; #endif - if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) + if (!dt_phys) return NULL; - mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach); + devtree = phys_to_virt(dt_phys); - if (!mdesc) { + /* check device tree validity */ + if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) + return NULL; + + /* Search the mdescs for the 'best' compatible value match */ + initial_boot_params = devtree; + dt_root = of_get_flat_dt_root(); + for_each_machine_desc(mdesc) { + score = of_flat_dt_match(dt_root, mdesc->dt_compat); + if (score > 0 && score < mdesc_score) { + mdesc_best = mdesc; + mdesc_score = score; + } + } + if (!mdesc_best) { const char *prop; long size; - unsigned long dt_root; early_print("\nError: unrecognized/unsupported " "device tree compatible list:\n[ "); - dt_root = of_get_flat_dt_root(); prop = of_get_flat_dt_prop(dt_root, "compatible", &size); while (size > 0) { early_print("'%s' ", prop); @@ -230,8 +233,22 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) dump_machine_table(); /* does not return */ } + model = of_get_flat_dt_prop(dt_root, "model", NULL); + if (!model) + model = of_get_flat_dt_prop(dt_root, "compatible", NULL); + if (!model) + model = "<unknown>"; + pr_info("Machine: %s, model: %s\n", mdesc_best->name, model); + + /* Retrieve various information from the /chosen node */ + of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line); + /* Initialize {size,address}-cells info */ + of_scan_flat_dt(early_init_dt_scan_root, NULL); + /* Setup memory, calling early_init_dt_add_memory_arch */ + of_scan_flat_dt(early_init_dt_scan_memory, NULL); + /* Change machine number to match the mdesc we're using */ - __machine_arch_type = mdesc->nr; + __machine_arch_type = mdesc_best->nr; - return mdesc; + return mdesc_best; } diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index b3fb8c9..9cbe70c 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -192,7 +192,6 @@ __dabt_svc: svc_entry mov r2, sp dabt_helper - THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR svc_exit r5 @ return from exception UNWIND(.fnend ) ENDPROC(__dabt_svc) @@ -417,8 +416,9 @@ __und_usr: bne __und_usr_thumb sub r4, r2, #4 @ ARM instr at LR - 4 1: ldrt r0, [r4] - ARM_BE8(rev r0, r0) @ little endian instruction - +#ifdef CONFIG_CPU_ENDIAN_BE8 + rev r0, r0 @ little endian instruction +#endif @ r0 = 32-bit ARM instruction which caused the exception @ r2 = PC value for the following instruction (:= regs->ARM_pc) @ r4 = PC value for the faulting instruction diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index a2dcafd..bc6bd96 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -393,7 +393,9 @@ ENTRY(vector_swi) #else USER( ldr r10, [lr, #-4] ) @ get SWI instruction #endif - ARM_BE8(rev r10, r10) @ little endian instruction +#ifdef CONFIG_CPU_ENDIAN_BE8 + rev r10, r10 @ little endian instruction +#endif #elif defined(CONFIG_AEABI) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 11d59b3..476de57 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -77,7 +77,6 @@ __HEAD ENTRY(stext) - ARM_BE8(setend be ) @ ensure we are in BE8 mode THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. THUMB( bx r9 ) @ If this is a Thumb-2 kernel, @@ -353,9 +352,6 @@ ENTRY(secondary_startup) * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ - - ARM_BE8(setend be) @ ensure we are in BE8 mode - #ifdef CONFIG_ARM_VIRT_EXT bl __hyp_stub_install_secondary #endif @@ -508,7 +504,6 @@ __fixup_smp: teq r0, #0x0 @ '0' on actual UP A9 hardware beq __fixup_smp_on_up @ So its an A9 UP ldr r0, [r0, #4] @ read SCU Config -ARM_BE8(rev r0, r0) @ byteswap if big endian and r0, r0, #0x3 @ number of CPUs teq r0, #0x0 @ is 1? movne pc, lr @@ -560,14 +555,6 @@ ENTRY(fixup_smp) ldmfd sp!, {r4 - r6, pc} ENDPROC(fixup_smp) -#ifdef __ARMEB__ -#define LOW_OFFSET 0x4 -#define HIGH_OFFSET 0x0 -#else -#define LOW_OFFSET 0x0 -#define HIGH_OFFSET 0x4 -#endif - #ifdef CONFIG_ARM_PATCH_PHYS_VIRT /* __fixup_pv_table - patch the stub instructions with the delta between @@ -578,20 +565,17 @@ ENDPROC(fixup_smp) __HEAD __fixup_pv_table: adr r0, 1f - ldmia r0, {r3-r7} - mvn ip, #0 - subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET + ldmia r0, {r3-r5, r7} + sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET add r4, r4, r3 @ adjust table start address add r5, r5, r3 @ adjust table end address - add r6, r6, r3 @ adjust __pv_phys_offset address - add r7, r7, r3 @ adjust __pv_offset address - str r8, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_offset - strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits + add r7, r7, r3 @ adjust __pv_phys_offset address + str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset mov r6, r3, lsr #24 @ constant for add/sub instructions teq r3, r6, lsl #24 @ must be 16MiB aligned THUMB( it ne @ cross section branch ) bne __error - str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits + str r6, [r7, #4] @ save to __pv_offset b __fixup_a_pv_table ENDPROC(__fixup_pv_table) @@ -600,19 +584,10 @@ ENDPROC(__fixup_pv_table) .long __pv_table_begin .long __pv_table_end 2: .long __pv_phys_offset - .long __pv_offset .text __fixup_a_pv_table: - adr r0, 3f - ldr r6, [r0] - add r6, r6, r3 - ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word - ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word - mov r6, r6, lsr #24 - cmn r0, #1 #ifdef CONFIG_THUMB2_KERNEL - moveq r0, #0x200000 @ set bit 21, mov to mvn instruction lsls r6, #24 beq 2f clz r7, r6 @@ -626,46 +601,18 @@ __fixup_a_pv_table: b 2f 1: add r7, r3 ldrh ip, [r7, #2] -ARM_BE8(rev16 ip, ip) - tst ip, #0x4000 - and ip, #0x8f00 - orrne ip, r6 @ mask in offset bits 31-24 - orreq ip, r0 @ mask in offset bits 7-0 -ARM_BE8(rev16 ip, ip) + and ip, 0x8f00 + orr ip, r6 @ mask in offset bits 31-24 strh ip, [r7, #2] - bne 2f - ldrh ip, [r7] -ARM_BE8(rev16 ip, ip) - bic ip, #0x20 - orr ip, ip, r0, lsr #16 -ARM_BE8(rev16 ip, ip) - strh ip, [r7] 2: cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b bx lr #else -#ifdef CONFIG_CPU_ENDIAN_BE8 - moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction -#else - moveq r0, #0x400000 @ set bit 22, mov to mvn instruction -#endif b 2f 1: ldr ip, [r7, r3] -#ifdef CONFIG_CPU_ENDIAN_BE8 - @ in BE8, we load data in BE, but instructions still in LE - bic ip, ip, #0xff000000 - tst ip, #0x000f0000 @ check the rotation field - orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 - biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0 @ mask in offset bits 7-0 -#else bic ip, ip, #0x000000ff - tst ip, #0xf00 @ check the rotation field - orrne ip, ip, r6 @ mask in offset bits 31-24 - biceq ip, ip, #0x400000 @ clear bit 22 - orreq ip, ip, r0 @ mask in offset bits 7-0 -#endif + orr ip, ip, r6 @ mask in offset bits 31-24 str ip, [r7, r3] 2: cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot @@ -674,30 +621,28 @@ ARM_BE8(rev16 ip, ip) #endif ENDPROC(__fixup_a_pv_table) - .align -3: .long __pv_offset - ENTRY(fixup_pv_table) stmfd sp!, {r4 - r7, lr} + ldr r2, 2f @ get address of __pv_phys_offset mov r3, #0 @ no offset mov r4, r0 @ r0 = table start add r5, r0, r1 @ r1 = table size + ldr r6, [r2, #4] @ get __pv_offset bl __fixup_a_pv_table ldmfd sp!, {r4 - r7, pc} ENDPROC(fixup_pv_table) + .align +2: .long __pv_phys_offset + .data .globl __pv_phys_offset .type __pv_phys_offset, %object __pv_phys_offset: - .quad 0 - .size __pv_phys_offset, . -__pv_phys_offset - - .globl __pv_offset - .type __pv_offset, %object + .long 0 + .size __pv_phys_offset, . - __pv_phys_offset __pv_offset: - .quad 0 - .size __pv_offset, . -__pv_offset + .long 0 #endif #include "head-common.S" diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 3d44660..7b95de6 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -344,13 +344,13 @@ int arch_install_hw_breakpoint(struct perf_event *bp) /* Breakpoint */ ctrl_base = ARM_BASE_BCR; val_base = ARM_BASE_BVR; - slots = this_cpu_ptr(bp_on_reg); + slots = (struct perf_event **)__get_cpu_var(bp_on_reg); max_slots = core_num_brps; } else { /* Watchpoint */ ctrl_base = ARM_BASE_WCR; val_base = ARM_BASE_WVR; - slots = this_cpu_ptr(wp_on_reg); + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); max_slots = core_num_wrps; } @@ -396,12 +396,12 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { /* Breakpoint */ base = ARM_BASE_BCR; - slots = this_cpu_ptr(bp_on_reg); + slots = (struct perf_event **)__get_cpu_var(bp_on_reg); max_slots = core_num_brps; } else { /* Watchpoint */ base = ARM_BASE_WCR; - slots = this_cpu_ptr(wp_on_reg); + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); max_slots = core_num_wrps; } @@ -697,7 +697,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, struct arch_hw_breakpoint *info; struct arch_hw_breakpoint_ctrl ctrl; - slots = this_cpu_ptr(wp_on_reg); + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); for (i = 0; i < core_num_wrps; ++i) { rcu_read_lock(); @@ -768,7 +768,7 @@ static void watchpoint_single_step_handler(unsigned long pc) struct perf_event *wp, **slots; struct arch_hw_breakpoint *info; - slots = this_cpu_ptr(wp_on_reg); + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); for (i = 0; i < core_num_wrps; ++i) { rcu_read_lock(); @@ -802,7 +802,7 @@ static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) struct arch_hw_breakpoint *info; struct arch_hw_breakpoint_ctrl ctrl; - slots = this_cpu_ptr(bp_on_reg); + slots = (struct perf_event **)__get_cpu_var(bp_on_reg); /* The exception entry code places the amended lr in the PC. */ addr = regs->ARM_pc; diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c index a7b621e..170e9f3 100644 --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c @@ -171,13 +171,13 @@ static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb) static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb) { - __this_cpu_write(current_kprobe, kcb->prev_kprobe.kp); + __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp; kcb->kprobe_status = kcb->prev_kprobe.status; } static void __kprobes set_current_kprobe(struct kprobe *p) { - __this_cpu_write(current_kprobe, p); + __get_cpu_var(current_kprobe) = p; } static void __kprobes @@ -421,10 +421,10 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs) continue; if (ri->rp && ri->rp->handler) { - __this_cpu_write(current_kprobe, &ri->rp->kp); + __get_cpu_var(current_kprobe) = &ri->rp->kp; get_kprobe_ctlblk()->kprobe_status = KPROBE_HIT_ACTIVE; ri->rp->handler(ri, regs); - __this_cpu_write(current_kprobe, NULL); + __get_cpu_var(current_kprobe) = NULL; } orig_ret_address = (unsigned long)ri->ret_addr; diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index f0d180d..57221e3 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -14,12 +14,11 @@ #include <asm/pgalloc.h> #include <asm/mmu_context.h> #include <asm/cacheflush.h> -#include <asm/fncpy.h> #include <asm/mach-types.h> #include <asm/smp_plat.h> #include <asm/system_misc.h> -extern void relocate_new_kernel(void); +extern const unsigned char relocate_new_kernel[]; extern const unsigned int relocate_new_kernel_size; extern unsigned long kexec_start_address; @@ -143,8 +142,6 @@ void machine_kexec(struct kimage *image) { unsigned long page_list; unsigned long reboot_code_buffer_phys; - unsigned long reboot_entry = (unsigned long)relocate_new_kernel; - unsigned long reboot_entry_phys; void *reboot_code_buffer; /* @@ -171,16 +168,16 @@ void machine_kexec(struct kimage *image) /* copy our kernel relocation code to the control code page */ - reboot_entry = fncpy(reboot_code_buffer, - reboot_entry, - relocate_new_kernel_size); - reboot_entry_phys = (unsigned long)reboot_entry + - (reboot_code_buffer_phys - (unsigned long)reboot_code_buffer); + memcpy(reboot_code_buffer, + relocate_new_kernel, relocate_new_kernel_size); + + flush_icache_range((unsigned long) reboot_code_buffer, + (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE); printk(KERN_INFO "Bye!\n"); if (kexec_reinit) kexec_reinit(); - soft_restart(reboot_entry_phys); + soft_restart(reboot_code_buffer_phys); } diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 45e4781..084dc88 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -24,7 +24,6 @@ #include <asm/sections.h> #include <asm/smp_plat.h> #include <asm/unwind.h> -#include <asm/opcodes.h> #ifdef CONFIG_XIP_KERNEL /* @@ -41,7 +40,7 @@ void *module_alloc(unsigned long size) { return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, - GFP_KERNEL, PAGE_KERNEL_EXEC, NUMA_NO_NODE, + GFP_KERNEL, PAGE_KERNEL_EXEC, -1, __builtin_return_address(0)); } #endif @@ -61,7 +60,6 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, Elf32_Sym *sym; const char *symname; s32 offset; - u32 tmp; #ifdef CONFIG_THUMB2_KERNEL u32 upper, lower, sign, j1, j2; #endif @@ -97,8 +95,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, case R_ARM_PC24: case R_ARM_CALL: case R_ARM_JUMP24: - offset = __mem_to_opcode_arm(*(u32 *)loc); - offset = (offset & 0x00ffffff) << 2; + offset = (*(u32 *)loc & 0x00ffffff) << 2; if (offset & 0x02000000) offset -= 0x04000000; @@ -114,10 +111,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, } offset >>= 2; - offset &= 0x00ffffff; - *(u32 *)loc &= __opcode_to_mem_arm(0xff000000); - *(u32 *)loc |= __opcode_to_mem_arm(offset); + *(u32 *)loc &= 0xff000000; + *(u32 *)loc |= offset & 0x00ffffff; break; case R_ARM_V4BX: @@ -125,8 +121,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, * other bits to re-code instruction as * MOV PC,Rm. */ - *(u32 *)loc &= __opcode_to_mem_arm(0xf000000f); - *(u32 *)loc |= __opcode_to_mem_arm(0x01a0f000); + *(u32 *)loc &= 0xf000000f; + *(u32 *)loc |= 0x01a0f000; break; case R_ARM_PREL31: @@ -136,7 +132,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, case R_ARM_MOVW_ABS_NC: case R_ARM_MOVT_ABS: - offset = tmp = __mem_to_opcode_arm(*(u32 *)loc); + offset = *(u32 *)loc; offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); offset = (offset ^ 0x8000) - 0x8000; @@ -144,18 +140,16 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS) offset >>= 16; - tmp &= 0xfff0f000; - tmp |= ((offset & 0xf000) << 4) | - (offset & 0x0fff); - - *(u32 *)loc = __opcode_to_mem_arm(tmp); + *(u32 *)loc &= 0xfff0f000; + *(u32 *)loc |= ((offset & 0xf000) << 4) | + (offset & 0x0fff); break; #ifdef CONFIG_THUMB2_KERNEL case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: - upper = __mem_to_opcode_thumb16(*(u16 *)loc); - lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); + upper = *(u16 *)loc; + lower = *(u16 *)(loc + 2); /* * 25 bit signed address range (Thumb-2 BL and B.W @@ -204,20 +198,17 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, sign = (offset >> 24) & 1; j1 = sign ^ (~(offset >> 23) & 1); j2 = sign ^ (~(offset >> 22) & 1); - upper = (u16)((upper & 0xf800) | (sign << 10) | + *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) | ((offset >> 12) & 0x03ff)); - lower = (u16)((lower & 0xd000) | - (j1 << 13) | (j2 << 11) | - ((offset >> 1) & 0x07ff)); - - *(u16 *)loc = __opcode_to_mem_thumb16(upper); - *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower); + *(u16 *)(loc + 2) = (u16)((lower & 0xd000) | + (j1 << 13) | (j2 << 11) | + ((offset >> 1) & 0x07ff)); break; case R_ARM_THM_MOVW_ABS_NC: case R_ARM_THM_MOVT_ABS: - upper = __mem_to_opcode_thumb16(*(u16 *)loc); - lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); + upper = *(u16 *)loc; + lower = *(u16 *)(loc + 2); /* * MOVT/MOVW instructions encoding in Thumb-2: @@ -238,14 +229,12 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) offset >>= 16; - upper = (u16)((upper & 0xfbf0) | - ((offset & 0xf000) >> 12) | - ((offset & 0x0800) >> 1)); - lower = (u16)((lower & 0x8f00) | - ((offset & 0x0700) << 4) | - (offset & 0x00ff)); - *(u16 *)loc = __opcode_to_mem_thumb16(upper); - *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower); + *(u16 *)loc = (u16)((upper & 0xfbf0) | + ((offset & 0xf000) >> 12) | + ((offset & 0x0800) >> 1)); + *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) | + ((offset & 0x0700) << 4) | + (offset & 0x00ff)); break; #endif diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index bc3f2ef..e186ee1 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -256,11 +256,12 @@ validate_event(struct pmu_hw_events *hw_events, struct perf_event *event) { struct arm_pmu *armpmu = to_arm_pmu(event->pmu); + struct pmu *leader_pmu = event->group_leader->pmu; if (is_software_event(event)) return 1; - if (event->state < PERF_EVENT_STATE_OFF) + if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF) return 1; if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index d85055c..8d6147b 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -68,7 +68,7 @@ EXPORT_SYMBOL_GPL(perf_num_counters); static struct pmu_hw_events *cpu_pmu_get_cpu_events(void) { - return this_cpu_ptr(&cpu_hw_events); + return &__get_cpu_var(cpu_hw_events); } static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) diff --git a/arch/arm/kernel/perf_regs.c b/arch/arm/kernel/perf_regs.c deleted file mode 100644 index 6e4379c..0000000 --- a/arch/arm/kernel/perf_regs.c +++ /dev/null @@ -1,30 +0,0 @@ - -#include <linux/errno.h> -#include <linux/kernel.h> -#include <linux/perf_event.h> -#include <linux/bug.h> -#include <asm/perf_regs.h> -#include <asm/ptrace.h> - -u64 perf_reg_value(struct pt_regs *regs, int idx) -{ - if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM_MAX)) - return 0; - - return regs->uregs[idx]; -} - -#define REG_RESERVED (~((1ULL << PERF_REG_ARM_MAX) - 1)) - -int perf_reg_validate(u64 mask) -{ - if (!mask || mask & REG_RESERVED) - return -EINVAL; - - return 0; -} - -u64 perf_reg_abi(struct task_struct *task) -{ - return PERF_SAMPLE_REGS_ABI_32; -} diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c index 570a48c..70ded3f 100644 --- a/arch/arm/kernel/psci_smp.c +++ b/arch/arm/kernel/psci_smp.c @@ -14,6 +14,7 @@ */ #include <linux/init.h> +#include <linux/irqchip/arm-gic.h> #include <linux/smp.h> #include <linux/of.h> diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S index 9585896..d0cdedf 100644 --- a/arch/arm/kernel/relocate_kernel.S +++ b/arch/arm/kernel/relocate_kernel.S @@ -2,12 +2,10 @@ * relocate_kernel.S - put the kernel image in place to boot */ -#include <linux/linkage.h> #include <asm/kexec.h> - .align 3 /* not needed for this code, but keeps fncpy() happy */ - -ENTRY(relocate_new_kernel) + .globl relocate_new_kernel +relocate_new_kernel: ldr r0,kexec_indirection_page ldr r1,kexec_start_address @@ -81,8 +79,6 @@ kexec_mach_type: kexec_boot_atags: .long 0x0 -ENDPROC(relocate_new_kernel) - relocate_new_kernel_end: .globl relocate_new_kernel_size diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 6a1b8a8..0e1e2b3 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -73,8 +73,6 @@ __setup("fpe=", fpe_setup); #endif extern void paging_init(const struct machine_desc *desc); -extern void early_paging_init(const struct machine_desc *, - struct proc_info_list *); extern void sanity_check_meminfo(void); extern enum reboot_mode reboot_mode; extern void setup_dma_zone(const struct machine_desc *desc); @@ -601,8 +599,6 @@ static void __init setup_processor(void) elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); #endif - erratum_a15_798181_init(); - feat_v6_fixup(); cacheid_init(); @@ -623,10 +619,9 @@ void __init dump_machine_table(void) /* can't use cpu_relax() here as it may require MMU setup */; } -int __init arm_add_memory(u64 start, u64 size) +int __init arm_add_memory(phys_addr_t start, phys_addr_t size) { struct membank *bank = &meminfo.bank[meminfo.nr_banks]; - u64 aligned_start; if (meminfo.nr_banks >= NR_BANKS) { printk(KERN_CRIT "NR_BANKS too low, " @@ -639,16 +634,10 @@ int __init arm_add_memory(u64 start, u64 size) * Size is appropriately rounded down, start is rounded up. */ size -= start & ~PAGE_MASK; - aligned_start = PAGE_ALIGN(start); + bank->start = PAGE_ALIGN(start); -#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT - if (aligned_start > ULONG_MAX) { - printk(KERN_CRIT "Ignoring memory at 0x%08llx outside " - "32-bit physical address space\n", (long long)start); - return -EINVAL; - } - - if (aligned_start + size > ULONG_MAX) { +#ifndef CONFIG_ARM_LPAE + if (bank->start + size < bank->start) { printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " "32-bit physical address space\n", (long long)start); /* @@ -656,11 +645,10 @@ int __init arm_add_memory(u64 start, u64 size) * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. * This means we lose a page after masking. */ - size = ULONG_MAX - aligned_start; + size = ULONG_MAX - bank->start; } #endif - bank->start = aligned_start; bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1); /* @@ -681,8 +669,8 @@ int __init arm_add_memory(u64 start, u64 size) static int __init early_mem(char *p) { static int usermem __initdata = 0; - u64 size; - u64 start; + phys_addr_t size; + phys_addr_t start; char *endp; /* @@ -890,8 +878,6 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL); - - early_paging_init(mdesc, lookup_processor_type(read_cpuid_id())); sanity_check_meminfo(); arm_memblock_init(&meminfo, mdesc); @@ -989,7 +975,6 @@ static const char *hwcap_str[] = { "idivt", "vfpd32", "lpae", - "evtstrm", NULL }; diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 04d6388..ab33042 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -21,7 +21,29 @@ #include <asm/unistd.h> #include <asm/vfp.h> -extern const unsigned long sigreturn_codes[7]; +/* + * For ARM syscalls, we encode the syscall number into the instruction. + */ +#define SWI_SYS_SIGRETURN (0xef000000|(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE)) +#define SWI_SYS_RT_SIGRETURN (0xef000000|(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE)) + +/* + * With EABI, the syscall number has to be loaded into r7. + */ +#define MOV_R7_NR_SIGRETURN (0xe3a07000 | (__NR_sigreturn - __NR_SYSCALL_BASE)) +#define MOV_R7_NR_RT_SIGRETURN (0xe3a07000 | (__NR_rt_sigreturn - __NR_SYSCALL_BASE)) + +/* + * For Thumb syscalls, we pass the syscall number via r7. We therefore + * need two 16-bit instructions. + */ +#define SWI_THUMB_SIGRETURN (0xdf00 << 16 | 0x2700 | (__NR_sigreturn - __NR_SYSCALL_BASE)) +#define SWI_THUMB_RT_SIGRETURN (0xdf00 << 16 | 0x2700 | (__NR_rt_sigreturn - __NR_SYSCALL_BASE)) + +static const unsigned long sigreturn_codes[7] = { + MOV_R7_NR_SIGRETURN, SWI_SYS_SIGRETURN, SWI_THUMB_SIGRETURN, + MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN, +}; static unsigned long signal_return_offset; @@ -353,18 +375,12 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig, */ thumb = handler & 1; -#if __LINUX_ARM_ARCH__ >= 7 - /* - * Clear the If-Then Thumb-2 execution state - * ARM spec requires this to be all 000s in ARM mode - * Snapdragon S4/Krait misbehaves on a Thumb=>ARM - * signal transition without this. - */ - cpsr &= ~PSR_IT_MASK; -#endif - if (thumb) { cpsr |= PSR_T_BIT; +#if __LINUX_ARM_ARCH__ >= 7 + /* clear the If-Then Thumb-2 execution state */ + cpsr &= ~PSR_IT_MASK; +#endif } else cpsr &= ~PSR_T_BIT; } diff --git a/arch/arm/kernel/sigreturn_codes.S b/arch/arm/kernel/sigreturn_codes.S deleted file mode 100644 index b84d0cb..0000000 --- a/arch/arm/kernel/sigreturn_codes.S +++ /dev/null @@ -1,102 +0,0 @@ -/* - * sigreturn_codes.S - code sinpets for sigreturn syscalls - * - * Created by: Victor Kamensky, 2013-08-13 - * Copyright: (C) 2013 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <asm/unistd.h> - -/* - * For ARM syscalls, we encode the syscall number into the instruction. - * With EABI, the syscall number has to be loaded into r7. As result - * ARM syscall sequence snippet will have move and svc in .arm encoding - * - * For Thumb syscalls, we pass the syscall number via r7. We therefore - * need two 16-bit instructions in .thumb encoding - * - * Please note sigreturn_codes code are not executed in place. Instead - * they just copied by kernel into appropriate places. Code inside of - * arch/arm/kernel/signal.c is very sensitive to layout of these code - * snippets. - */ - -/* - * In CPU_THUMBONLY case kernel arm opcodes are not allowed. - * Note in this case codes skips those instructions but it uses .org - * directive to keep correct layout of sigreturn_codes array. - */ -#ifndef CONFIG_CPU_THUMBONLY -#define ARM_OK(code...) code -#else -#define ARM_OK(code...) -#endif - - .macro arm_slot n - .org sigreturn_codes + 12 * (\n) -ARM_OK( .arm ) - .endm - - .macro thumb_slot n - .org sigreturn_codes + 12 * (\n) + 8 - .thumb - .endm - -#if __LINUX_ARM_ARCH__ <= 4 - /* - * Note we manually set minimally required arch that supports - * required thumb opcodes for early arch versions. It is OK - * for this file to be used in combination with other - * lower arch variants, since these code snippets are only - * used as input data. - */ - .arch armv4t -#endif - - .section .rodata - .global sigreturn_codes - .type sigreturn_codes, #object - - .align - -sigreturn_codes: - - /* ARM sigreturn syscall code snippet */ - arm_slot 0 -ARM_OK( mov r7, #(__NR_sigreturn - __NR_SYSCALL_BASE) ) -ARM_OK( swi #(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE) ) - - /* Thumb sigreturn syscall code snippet */ - thumb_slot 0 - movs r7, #(__NR_sigreturn - __NR_SYSCALL_BASE) - swi #0 - - /* ARM sigreturn_rt syscall code snippet */ - arm_slot 1 -ARM_OK( mov r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE) ) -ARM_OK( swi #(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE) ) - - /* Thumb sigreturn_rt syscall code snippet */ - thumb_slot 1 - movs r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE) - swi #0 - - /* - * Note on addtional space: setup_return in signal.c - * algorithm uses two words copy regardless whether - * it is thumb case or not, so we need additional - * word after real last entry. - */ - arm_slot 2 - .space 4 - - .size sigreturn_codes, . - sigreturn_codes diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index b907d9b..db1536b 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -55,7 +55,6 @@ * specific registers and some other data for resume. * r0 = suspend function arg0 * r1 = suspend function - * r2 = MPIDR value the resuming CPU will use */ ENTRY(__cpu_suspend) stmfd sp!, {r4 - r11, lr} @@ -68,18 +67,23 @@ ENTRY(__cpu_suspend) mov r5, sp @ current virtual SP add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn sub sp, sp, r4 @ allocate CPU state on stack - ldr r3, =sleep_save_sp stmfd sp!, {r0, r1} @ save suspend func arg and pointer - ldr r3, [r3, #SLEEP_SAVE_SP_VIRT] - ALT_SMP(ldr r0, =mpidr_hash) - ALT_UP_B(1f) - /* This ldmia relies on the memory layout of the mpidr_hash struct */ - ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts - compute_mpidr_hash r0, r6, r7, r8, r2, r1 - add r3, r3, r0, lsl #2 -1: mov r2, r5 @ virtual SP + add r0, sp, #8 @ save pointer to save block mov r1, r4 @ size of save block - add r0, sp, #8 @ pointer to save block + mov r2, r5 @ virtual SP + ldr r3, =sleep_save_sp + ldr r3, [r3, #SLEEP_SAVE_SP_VIRT] + ALT_SMP(mrc p15, 0, r9, c0, c0, 5) + ALT_UP_B(1f) + ldr r8, =mpidr_hash + /* + * This ldmia relies on the memory layout of the mpidr_hash + * struct mpidr_hash. + */ + ldmia r8, {r4-r7} @ r4 = mpidr mask (r5,r6,r7) = l[0,1,2] shifts + compute_mpidr_hash lr, r5, r6, r7, r9, r4 + add r3, r3, lr, lsl #2 +1: bl __cpu_suspend_save adr lr, BSYM(cpu_suspend_abort) ldmfd sp!, {r0, pc} @ call suspend fn @@ -126,7 +130,6 @@ ENDPROC(cpu_resume_after_mmu) .data .align ENTRY(cpu_resume) -ARM_BE8(setend be) @ ensure we are in BE mode mov r1, #0 ALT_SMP(mrc p15, 0, r0, c0, c0, 5) ALT_UP_B(1f) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index dc894ab..72024ea 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -25,7 +25,6 @@ #include <linux/clockchips.h> #include <linux/completion.h> #include <linux/cpufreq.h> -#include <linux/irq_work.h> #include <linux/atomic.h> #include <asm/smp.h> @@ -67,8 +66,6 @@ enum ipi_msg_type { IPI_CALL_FUNC, IPI_CALL_FUNC_SINGLE, IPI_CPU_STOP, - IPI_IRQ_WORK, - IPI_COMPLETION, }; static DECLARE_COMPLETION(cpu_running); @@ -83,7 +80,7 @@ void __init smp_set_ops(struct smp_operations *ops) static unsigned long get_arch_pgd(pgd_t *pgd) { - phys_addr_t pgdir = virt_to_idmap(pgd); + phys_addr_t pgdir = virt_to_phys(pgd); BUG_ON(pgdir & ARCH_PGD_MASK); return pgdir >> ARCH_PGD_SHIFT; } @@ -451,14 +448,6 @@ void arch_send_call_function_single_ipi(int cpu) smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); } -#ifdef CONFIG_IRQ_WORK -void arch_irq_work_raise(void) -{ - if (is_smp()) - smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); -} -#endif - static const char *ipi_types[NR_IPI] = { #define S(x,s) [x] = s S(IPI_WAKEUP, "CPU wakeup interrupts"), @@ -467,8 +456,6 @@ static const char *ipi_types[NR_IPI] = { S(IPI_CALL_FUNC, "Function call interrupts"), S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), S(IPI_CPU_STOP, "CPU stop interrupts"), - S(IPI_IRQ_WORK, "IRQ work interrupts"), - S(IPI_COMPLETION, "completion interrupts"), }; void show_ipi_list(struct seq_file *p, int prec) @@ -528,19 +515,6 @@ static void ipi_cpu_stop(unsigned int cpu) cpu_relax(); } -static DEFINE_PER_CPU(struct completion *, cpu_completion); - -int register_ipi_completion(struct completion *completion, int cpu) -{ - per_cpu(cpu_completion, cpu) = completion; - return IPI_COMPLETION; -} - -static void ipi_complete(unsigned int cpu) -{ - complete(per_cpu(cpu_completion, cpu)); -} - /* * Main handler for inter-processor interrupts */ @@ -591,20 +565,6 @@ void handle_IPI(int ipinr, struct pt_regs *regs) irq_exit(); break; -#ifdef CONFIG_IRQ_WORK - case IPI_IRQ_WORK: - irq_enter(); - irq_work_run(); - irq_exit(); - break; -#endif - - case IPI_COMPLETION: - irq_enter(); - ipi_complete(cpu); - irq_exit(); - break; - default: printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 1aafa0d..5bc1a63 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -28,7 +28,7 @@ */ unsigned int __init scu_get_core_count(void __iomem *scu_base) { - unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG); + unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG); return (ncores & 0x03) + 1; } @@ -42,19 +42,19 @@ void scu_enable(void __iomem *scu_base) #ifdef CONFIG_ARM_ERRATA_764369 /* Cortex-A9 only */ if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) { - scu_ctrl = readl_relaxed(scu_base + 0x30); + scu_ctrl = __raw_readl(scu_base + 0x30); if (!(scu_ctrl & 1)) - writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30); + __raw_writel(scu_ctrl | 0x1, scu_base + 0x30); } #endif - scu_ctrl = readl_relaxed(scu_base + SCU_CTRL); + scu_ctrl = __raw_readl(scu_base + SCU_CTRL); /* already enabled? */ if (scu_ctrl & 1) return; scu_ctrl |= 1; - writel_relaxed(scu_ctrl, scu_base + SCU_CTRL); + __raw_writel(scu_ctrl, scu_base + SCU_CTRL); /* * Ensure that the data accessed by CPU0 before the SCU was @@ -80,9 +80,9 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode) if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; - val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; + val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; val |= mode; - writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); + __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu); return 0; } diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index 95d0636..83ccca3 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c @@ -70,40 +70,6 @@ static inline void ipi_flush_bp_all(void *ignored) local_flush_bp_all(); } -#ifdef CONFIG_ARM_ERRATA_798181 -bool (*erratum_a15_798181_handler)(void); - -static bool erratum_a15_798181_partial(void) -{ - asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(ish); - return false; -} - -static bool erratum_a15_798181_broadcast(void) -{ - asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(ish); - return true; -} - -void erratum_a15_798181_init(void) -{ - unsigned int midr = read_cpuid_id(); - unsigned int revidr = read_cpuid(CPUID_REVIDR); - - /* Cortex-A15 r0p0..r3p2 w/o ECO fix affected */ - if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2 || - (revidr & 0x210) == 0x210) { - return; - } - if (revidr & 0x10) - erratum_a15_798181_handler = erratum_a15_798181_partial; - else - erratum_a15_798181_handler = erratum_a15_798181_broadcast; -} -#endif - static void ipi_flush_tlb_a15_erratum(void *arg) { dmb(); @@ -114,6 +80,7 @@ static void broadcast_tlb_a15_erratum(void) if (!erratum_a15_798181()) return; + dummy_flush_tlb_a15_erratum(); smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1); } @@ -125,6 +92,7 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm) if (!erratum_a15_798181()) return; + dummy_flush_tlb_a15_erratum(); this_cpu = get_cpu(); a15_erratum_get_cpumask(this_cpu, mm, &mask); smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1); diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 6591e26..2985c9f 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -45,7 +45,7 @@ static void twd_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_PERIODIC: ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_PERIODIC; - writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), + __raw_writel(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), twd_base + TWD_TIMER_LOAD); break; case CLOCK_EVT_MODE_ONESHOT: @@ -58,18 +58,18 @@ static void twd_set_mode(enum clock_event_mode mode, ctrl = 0; } - writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); + __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); } static int twd_set_next_event(unsigned long evt, struct clock_event_device *unused) { - unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); + unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); ctrl |= TWD_TIMER_CONTROL_ENABLE; - writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER); - writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); + __raw_writel(evt, twd_base + TWD_TIMER_COUNTER); + __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); return 0; } @@ -82,8 +82,8 @@ static int twd_set_next_event(unsigned long evt, */ static int twd_timer_ack(void) { - if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) { - writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); + if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) { + __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); return 1; } @@ -211,15 +211,15 @@ static void twd_calibrate_rate(void) waitjiffies += 5; /* enable, no interrupt or reload */ - writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL); + __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL); /* maximum value */ - writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); + __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); while (get_jiffies_64() < waitjiffies) udelay(10); - count = readl_relaxed(twd_base + TWD_TIMER_COUNTER); + count = __raw_readl(twd_base + TWD_TIMER_COUNTER); twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); @@ -277,7 +277,7 @@ static void twd_timer_setup(void) * bother with the below. */ if (per_cpu(percpu_setup_called, cpu)) { - writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); clockevents_register_device(clk); enable_percpu_irq(clk->irq, 0); return; @@ -290,7 +290,7 @@ static void twd_timer_setup(void) * The following is done once per CPU the first time .setup() is * called. */ - writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); clk->name = "local_timer"; clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c index 2835d35..41cf3cb 100644 --- a/arch/arm/kernel/suspend.c +++ b/arch/arm/kernel/suspend.c @@ -10,7 +10,7 @@ #include <asm/suspend.h> #include <asm/tlbflush.h> -extern int __cpu_suspend(unsigned long, int (*)(unsigned long), u32 cpuid); +extern int __cpu_suspend(unsigned long, int (*)(unsigned long)); extern void cpu_resume_mmu(void); #ifdef CONFIG_MMU @@ -21,7 +21,6 @@ extern void cpu_resume_mmu(void); int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) { struct mm_struct *mm = current->active_mm; - u32 __mpidr = cpu_logical_map(smp_processor_id()); int ret; if (!idmap_pgd) @@ -33,7 +32,7 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) * resume (indicated by a zero return code), we need to switch * back to the correct page tables. */ - ret = __cpu_suspend(arg, fn, __mpidr); + ret = __cpu_suspend(arg, fn); if (ret == 0) { cpu_switch_mm(mm->pgd, mm); local_flush_bp_all(); @@ -45,8 +44,7 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) #else int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) { - u32 __mpidr = cpu_logical_map(smp_processor_id()); - return __cpu_suspend(arg, fn, __mpidr); + return __cpu_suspend(arg, fn); } #define idmap_pgd NULL #endif diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 829a96d..98aee32 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -11,26 +11,25 @@ * This file contains the ARM-specific time handling details: * reading the RTC at bootup, etc... */ -#include <linux/clk-provider.h> -#include <linux/clocksource.h> -#include <linux/errno.h> #include <linux/export.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> #include <linux/kernel.h> -#include <linux/profile.h> +#include <linux/interrupt.h> +#include <linux/time.h> +#include <linux/init.h> #include <linux/sched.h> -#include <linux/sched_clock.h> #include <linux/smp.h> -#include <linux/time.h> #include <linux/timex.h> +#include <linux/errno.h> +#include <linux/profile.h> #include <linux/timer.h> +#include <linux/clocksource.h> +#include <linux/irq.h> +#include <linux/sched_clock.h> +#include <asm/thread_info.h> +#include <asm/stacktrace.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <asm/stacktrace.h> -#include <asm/thread_info.h> #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \ defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE) @@ -117,12 +116,8 @@ int __init register_persistent_clock(clock_access_fn read_boot, void __init time_init(void) { - if (machine_desc->init_time) { + if (machine_desc->init_time) machine_desc->init_time(); - } else { -#ifdef CONFIG_COMMON_CLK - of_clk_init(NULL); -#endif + else clocksource_of_init(); - } } diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index dbf0923..8fcda14 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -34,7 +34,6 @@ #include <asm/unwind.h> #include <asm/tls.h> #include <asm/system_misc.h> -#include <asm/opcodes.h> static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; @@ -342,17 +341,15 @@ void arm_notify_die(const char *str, struct pt_regs *regs, int is_valid_bugaddr(unsigned long pc) { #ifdef CONFIG_THUMB2_KERNEL - u16 bkpt; - u16 insn = __opcode_to_mem_thumb16(BUG_INSTR_VALUE); + unsigned short bkpt; #else - u32 bkpt; - u32 insn = __opcode_to_mem_arm(BUG_INSTR_VALUE); + unsigned long bkpt; #endif if (probe_kernel_address((unsigned *)pc, bkpt)) return 0; - return bkpt == insn; + return bkpt == BUG_INSTR_VALUE; } #endif @@ -405,28 +402,25 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) if (processor_mode(regs) == SVC_MODE) { #ifdef CONFIG_THUMB2_KERNEL if (thumb_mode(regs)) { - instr = __mem_to_opcode_thumb16(((u16 *)pc)[0]); + instr = ((u16 *)pc)[0]; if (is_wide_instruction(instr)) { - u16 inst2; - inst2 = __mem_to_opcode_thumb16(((u16 *)pc)[1]); - instr = __opcode_thumb32_compose(instr, inst2); + instr <<= 16; + instr |= ((u16 *)pc)[1]; } } else #endif - instr = __mem_to_opcode_arm(*(u32 *) pc); + instr = *(u32 *) pc; } else if (thumb_mode(regs)) { if (get_user(instr, (u16 __user *)pc)) goto die_sig; - instr = __mem_to_opcode_thumb16(instr); if (is_wide_instruction(instr)) { unsigned int instr2; if (get_user(instr2, (u16 __user *)pc+1)) goto die_sig; - instr2 = __mem_to_opcode_thumb16(instr2); - instr = __opcode_thumb32_compose(instr, instr2); + instr <<= 16; + instr |= instr2; } } else if (get_user(instr, (u32 __user *)pc)) { - instr = __mem_to_opcode_arm(instr); goto die_sig; } @@ -856,7 +850,7 @@ static void __init kuser_init(void *vectors) memcpy(vectors + 0xfe0, vectors + 0xfe8, 4); } #else -static inline void __init kuser_init(void *vectors) +static void __init kuser_init(void *vectors) { } #endif diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig index 466bd29..ebf5015 100644 --- a/arch/arm/kvm/Kconfig +++ b/arch/arm/kvm/Kconfig @@ -20,7 +20,6 @@ config KVM bool "Kernel-based Virtual Machine (KVM) support" select PREEMPT_NOTIFIERS select ANON_INODES - select HAVE_KVM_CPU_RELAX_INTERCEPT select KVM_MMIO select KVM_ARM_HOST depends on ARM_VIRT_EXT && ARM_LPAE diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile index 789bca9..d99bee4 100644 --- a/arch/arm/kvm/Makefile +++ b/arch/arm/kvm/Makefile @@ -19,6 +19,6 @@ kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o obj-y += kvm-arm.o init.o interrupts.o obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o -obj-y += coproc.o coproc_a15.o coproc_a7.o mmio.o psci.o perf.o +obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 2a700e0..9c697db 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -65,7 +65,7 @@ static bool vgic_present; static void kvm_arm_set_running_vcpu(struct kvm_vcpu *vcpu) { BUG_ON(preemptible()); - __this_cpu_write(kvm_arm_running_vcpu, vcpu); + __get_cpu_var(kvm_arm_running_vcpu) = vcpu; } /** @@ -75,7 +75,7 @@ static void kvm_arm_set_running_vcpu(struct kvm_vcpu *vcpu) struct kvm_vcpu *kvm_arm_get_running_vcpu(void) { BUG_ON(preemptible()); - return __this_cpu_read(kvm_arm_running_vcpu); + return __get_cpu_var(kvm_arm_running_vcpu); } /** @@ -152,13 +152,12 @@ int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) return VM_FAULT_SIGBUS; } -void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, +void kvm_arch_free_memslot(struct kvm_memory_slot *free, struct kvm_memory_slot *dont) { } -int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, - unsigned long npages) +int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) { return 0; } @@ -798,19 +797,6 @@ long kvm_arch_vm_ioctl(struct file *filp, return -EFAULT; return kvm_vm_ioctl_set_device_addr(kvm, &dev_addr); } - case KVM_ARM_PREFERRED_TARGET: { - int err; - struct kvm_vcpu_init init; - - err = kvm_vcpu_preferred_target(&init); - if (err) - return err; - - if (copy_to_user(argp, &init, sizeof(init))) - return -EFAULT; - - return 0; - } default: return -EINVAL; } @@ -829,7 +815,7 @@ static void cpu_init_hyp_mode(void *dummy) boot_pgd_ptr = kvm_mmu_get_boot_httbr(); pgd_ptr = kvm_mmu_get_httbr(); - stack_page = __this_cpu_read(kvm_arm_hyp_stack_page); + stack_page = __get_cpu_var(kvm_arm_hyp_stack_page); hyp_stack_ptr = stack_page + PAGE_SIZE; vector_ptr = (unsigned long)__kvm_hyp_vector; diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index 78c0885..db9cf69 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -71,98 +71,6 @@ int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run) return 1; } -static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) -{ - /* - * Compute guest MPIDR. We build a virtual cluster out of the - * vcpu_id, but we read the 'U' bit from the underlying - * hardware directly. - */ - vcpu->arch.cp15[c0_MPIDR] = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) | - ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) | - (vcpu->vcpu_id & 3)); -} - -/* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */ -static bool access_actlr(struct kvm_vcpu *vcpu, - const struct coproc_params *p, - const struct coproc_reg *r) -{ - if (p->is_write) - return ignore_write(vcpu, p); - - *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR]; - return true; -} - -/* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */ -static bool access_cbar(struct kvm_vcpu *vcpu, - const struct coproc_params *p, - const struct coproc_reg *r) -{ - if (p->is_write) - return write_to_read_only(vcpu, p); - return read_zero(vcpu, p); -} - -/* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */ -static bool access_l2ctlr(struct kvm_vcpu *vcpu, - const struct coproc_params *p, - const struct coproc_reg *r) -{ - if (p->is_write) - return ignore_write(vcpu, p); - - *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR]; - return true; -} - -static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) -{ - u32 l2ctlr, ncores; - - asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); - l2ctlr &= ~(3 << 24); - ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1; - /* How many cores in the current cluster and the next ones */ - ncores -= (vcpu->vcpu_id & ~3); - /* Cap it to the maximum number of cores in a single cluster */ - ncores = min(ncores, 3U); - l2ctlr |= (ncores & 3) << 24; - - vcpu->arch.cp15[c9_L2CTLR] = l2ctlr; -} - -static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) -{ - u32 actlr; - - /* ACTLR contains SMP bit: make sure you create all cpus first! */ - asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); - /* Make the SMP bit consistent with the guest configuration */ - if (atomic_read(&vcpu->kvm->online_vcpus) > 1) - actlr |= 1U << 6; - else - actlr &= ~(1U << 6); - - vcpu->arch.cp15[c1_ACTLR] = actlr; -} - -/* - * TRM entries: A7:4.3.50, A15:4.3.49 - * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). - */ -static bool access_l2ectlr(struct kvm_vcpu *vcpu, - const struct coproc_params *p, - const struct coproc_reg *r) -{ - if (p->is_write) - return ignore_write(vcpu, p); - - *vcpu_reg(vcpu, p->Rt1) = 0; - return true; -} - /* See note at ARM ARM B1.14.4 */ static bool access_dcsw(struct kvm_vcpu *vcpu, const struct coproc_params *p, @@ -245,22 +153,10 @@ static bool pm_fake(struct kvm_vcpu *vcpu, * registers preceding 32-bit ones. */ static const struct coproc_reg cp15_regs[] = { - /* MPIDR: we use VMPIDR for guest access. */ - { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32, - NULL, reset_mpidr, c0_MPIDR }, - /* CSSELR: swapped by interrupt.S. */ { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32, NULL, reset_unknown, c0_CSSELR }, - /* ACTLR: trapped by HCR.TAC bit. */ - { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32, - access_actlr, reset_actlr, c1_ACTLR }, - - /* CPACR: swapped by interrupt.S. */ - { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, - NULL, reset_val, c1_CPACR, 0x00000000 }, - /* TTBR0/TTBR1: swapped by interrupt.S. */ { CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, { CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, @@ -299,13 +195,6 @@ static const struct coproc_reg cp15_regs[] = { { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw}, { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw}, /* - * L2CTLR access (guest wants to know #CPUs). - */ - { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, - access_l2ctlr, reset_l2ctlr, c9_L2CTLR }, - { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr}, - - /* * Dummy performance monitor implementation. */ { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr}, @@ -345,9 +234,6 @@ static const struct coproc_reg cp15_regs[] = { /* CNTKCTL: swapped by interrupt.S. */ { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32, NULL, reset_val, c14_CNTKCTL, 0x00000000 }, - - /* The Configuration Base Address Register. */ - { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, }; /* Target specific emulation tables */ @@ -355,12 +241,6 @@ static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS]; void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table) { - unsigned int i; - - for (i = 1; i < table->num; i++) - BUG_ON(cmp_reg(&table->table[i-1], - &table->table[i]) >= 0); - target_tables[table->target] = table; } diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c index bb0cac1..cf93472 100644 --- a/arch/arm/kvm/coproc_a15.c +++ b/arch/arm/kvm/coproc_a15.c @@ -17,12 +17,101 @@ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <linux/kvm_host.h> -#include <asm/kvm_coproc.h> +#include <asm/cputype.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_host.h> #include <asm/kvm_emulate.h> +#include <asm/kvm_coproc.h> #include <linux/init.h> +static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + /* + * Compute guest MPIDR: + * (Even if we present only one VCPU to the guest on an SMP + * host we don't set the U bit in the MPIDR, or vice versa, as + * revealing the underlying hardware properties is likely to + * be the best choice). + */ + vcpu->arch.cp15[c0_MPIDR] = (read_cpuid_mpidr() & ~MPIDR_LEVEL_MASK) + | (vcpu->vcpu_id & MPIDR_LEVEL_MASK); +} + #include "coproc.h" +/* A15 TRM 4.3.28: RO WI */ +static bool access_actlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR]; + return true; +} + +/* A15 TRM 4.3.60: R/O. */ +static bool access_cbar(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return write_to_read_only(vcpu, p); + return read_zero(vcpu, p); +} + +/* A15 TRM 4.3.48: R/O WI. */ +static bool access_l2ctlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR]; + return true; +} + +static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + u32 l2ctlr, ncores; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); + l2ctlr &= ~(3 << 24); + ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1; + l2ctlr |= (ncores & 3) << 24; + + vcpu->arch.cp15[c9_L2CTLR] = l2ctlr; +} + +static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + u32 actlr; + + /* ACTLR contains SMP bit: make sure you create all cpus first! */ + asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); + /* Make the SMP bit consistent with the guest configuration */ + if (atomic_read(&vcpu->kvm->online_vcpus) > 1) + actlr |= 1U << 6; + else + actlr &= ~(1U << 6); + + vcpu->arch.cp15[c1_ACTLR] = actlr; +} + +/* A15 TRM 4.3.49: R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). */ +static bool access_l2ectlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt1) = 0; + return true; +} + /* * A15-specific CP15 registers. * CRn denotes the primary register number, but is copied to the CRm in the @@ -32,9 +121,29 @@ * registers preceding 32-bit ones. */ static const struct coproc_reg a15_regs[] = { + /* MPIDR: we use VMPIDR for guest access. */ + { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32, + NULL, reset_mpidr, c0_MPIDR }, + /* SCTLR: swapped by interrupt.S. */ { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, NULL, reset_val, c1_SCTLR, 0x00C50078 }, + /* ACTLR: trapped by HCR.TAC bit. */ + { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32, + access_actlr, reset_actlr, c1_ACTLR }, + /* CPACR: swapped by interrupt.S. */ + { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, + NULL, reset_val, c1_CPACR, 0x00000000 }, + + /* + * L2CTLR access (guest wants to know #CPUs). + */ + { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, + access_l2ctlr, reset_l2ctlr, c9_L2CTLR }, + { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr}, + + /* The Configuration Base Address Register. */ + { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, }; static struct kvm_coproc_target_table a15_target_table = { @@ -45,6 +154,12 @@ static struct kvm_coproc_target_table a15_target_table = { static int __init coproc_a15_init(void) { + unsigned int i; + + for (i = 1; i < ARRAY_SIZE(a15_regs); i++) + BUG_ON(cmp_reg(&a15_regs[i-1], + &a15_regs[i]) >= 0); + kvm_register_target_coproc_table(&a15_target_table); return 0; } diff --git a/arch/arm/kvm/coproc_a7.c b/arch/arm/kvm/coproc_a7.c deleted file mode 100644 index 1df7673..0000000 --- a/arch/arm/kvm/coproc_a7.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2012 - Virtual Open Systems and Columbia University - * Copyright (C) 2013 - ARM Ltd - * - * Authors: Rusty Russell <rusty@rustcorp.au> - * Christoffer Dall <c.dall@virtualopensystems.com> - * Jonathan Austin <jonathan.austin@arm.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#include <linux/kvm_host.h> -#include <asm/kvm_coproc.h> -#include <asm/kvm_emulate.h> -#include <linux/init.h> - -#include "coproc.h" - -/* - * Cortex-A7 specific CP15 registers. - * CRn denotes the primary register number, but is copied to the CRm in the - * user space API for 64-bit register access in line with the terminology used - * in the ARM ARM. - * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit - * registers preceding 32-bit ones. - */ -static const struct coproc_reg a7_regs[] = { - /* SCTLR: swapped by interrupt.S. */ - { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, - NULL, reset_val, c1_SCTLR, 0x00C50878 }, -}; - -static struct kvm_coproc_target_table a7_target_table = { - .target = KVM_ARM_TARGET_CORTEX_A7, - .table = a7_regs, - .num = ARRAY_SIZE(a7_regs), -}; - -static int __init coproc_a7_init(void) -{ - kvm_register_target_coproc_table(&a7_target_table); - return 0; -} -late_initcall(coproc_a7_init); diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c index d6c0052..bdede9e 100644 --- a/arch/arm/kvm/emulate.c +++ b/arch/arm/kvm/emulate.c @@ -354,7 +354,7 @@ static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr) *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset; if (is_pabt) { - /* Set IFAR and IFSR */ + /* Set DFAR and DFSR */ vcpu->arch.cp15[c6_IFAR] = addr; is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31); /* Always give debug fault for now - should give guest a clue */ diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index 20f8d97..152d036 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -190,8 +190,6 @@ int __attribute_const__ kvm_target_cpu(void) return -EINVAL; switch (part_number) { - case ARM_CPU_PART_CORTEX_A7: - return KVM_ARM_TARGET_CORTEX_A7; case ARM_CPU_PART_CORTEX_A15: return KVM_ARM_TARGET_CORTEX_A15; default: @@ -204,7 +202,7 @@ int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, { unsigned int i; - /* We can only cope with guest==host and only on A15/A7 (for now). */ + /* We can only do a cortex A15 for now. */ if (init->target != kvm_target_cpu()) return -EINVAL; @@ -224,26 +222,6 @@ int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, return kvm_reset_vcpu(vcpu); } -int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init) -{ - int target = kvm_target_cpu(); - - if (target < 0) - return -ENODEV; - - memset(init, 0, sizeof(*init)); - - /* - * For now, we don't return any features. - * In future, we might use features to return target - * specific features available for the preferred - * target type. - */ - init->target = (__u32)target; - - return 0; -} - int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) { return -EINVAL; diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c index a920790..df4c82d 100644 --- a/arch/arm/kvm/handle_exit.c +++ b/arch/arm/kvm/handle_exit.c @@ -73,29 +73,23 @@ static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run) } /** - * kvm_handle_wfx - handle a WFI or WFE instructions trapped in guests + * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest * @vcpu: the vcpu pointer * @run: the kvm_run structure pointer * - * WFE: Yield the CPU and come back to this vcpu when the scheduler - * decides to. - * WFI: Simply call kvm_vcpu_block(), which will halt execution of - * world-switches and schedule other host processes until there is an - * incoming IRQ or FIQ to the VM. + * Simply sets the wait_for_interrupts flag on the vcpu structure, which will + * halt execution of world-switches and schedule other host processes until + * there is an incoming IRQ or FIQ to the VM. */ -static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run) +static int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run) { trace_kvm_wfi(*vcpu_pc(vcpu)); - if (kvm_vcpu_get_hsr(vcpu) & HSR_WFI_IS_WFE) - kvm_vcpu_on_spin(vcpu); - else - kvm_vcpu_block(vcpu); - + kvm_vcpu_block(vcpu); return 1; } static exit_handle_fn arm_exit_handlers[] = { - [HSR_EC_WFI] = kvm_handle_wfx, + [HSR_EC_WFI] = kvm_handle_wfi, [HSR_EC_CP15_32] = kvm_handle_cp15_32, [HSR_EC_CP15_64] = kvm_handle_cp15_64, [HSR_EC_CP14_MR] = kvm_handle_cp14_access, diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c index 4cb5a93..0c25d94 100644 --- a/arch/arm/kvm/mmio.c +++ b/arch/arm/kvm/mmio.c @@ -23,68 +23,6 @@ #include "trace.h" -static void mmio_write_buf(char *buf, unsigned int len, unsigned long data) -{ - void *datap = NULL; - union { - u8 byte; - u16 hword; - u32 word; - u64 dword; - } tmp; - - switch (len) { - case 1: - tmp.byte = data; - datap = &tmp.byte; - break; - case 2: - tmp.hword = data; - datap = &tmp.hword; - break; - case 4: - tmp.word = data; - datap = &tmp.word; - break; - case 8: - tmp.dword = data; - datap = &tmp.dword; - break; - } - - memcpy(buf, datap, len); -} - -static unsigned long mmio_read_buf(char *buf, unsigned int len) -{ - unsigned long data = 0; - union { - u16 hword; - u32 word; - u64 dword; - } tmp; - - switch (len) { - case 1: - data = buf[0]; - break; - case 2: - memcpy(&tmp.hword, buf, len); - data = tmp.hword; - break; - case 4: - memcpy(&tmp.word, buf, len); - data = tmp.word; - break; - case 8: - memcpy(&tmp.dword, buf, len); - data = tmp.dword; - break; - } - - return data; -} - /** * kvm_handle_mmio_return -- Handle MMIO loads after user space emulation * @vcpu: The VCPU pointer @@ -95,27 +33,28 @@ static unsigned long mmio_read_buf(char *buf, unsigned int len) */ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) { - unsigned long data; + unsigned long *dest; unsigned int len; int mask; if (!run->mmio.is_write) { + dest = vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt); + *dest = 0; + len = run->mmio.len; if (len > sizeof(unsigned long)) return -EINVAL; - data = mmio_read_buf(run->mmio.data, len); + memcpy(dest, run->mmio.data, len); + + trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, + *((u64 *)run->mmio.data)); if (vcpu->arch.mmio_decode.sign_extend && len < sizeof(unsigned long)) { mask = 1U << ((len * 8) - 1); - data = (data ^ mask) - mask; + *dest = (*dest ^ mask) - mask; } - - trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, - data); - data = vcpu_data_host_to_guest(vcpu, data, len); - *vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt) = data; } return 0; @@ -166,7 +105,6 @@ int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, phys_addr_t fault_ipa) { struct kvm_exit_mmio mmio; - unsigned long data; unsigned long rt; int ret; @@ -187,15 +125,13 @@ int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, } rt = vcpu->arch.mmio_decode.rt; - data = vcpu_data_guest_to_host(vcpu, *vcpu_reg(vcpu, rt), mmio.len); - trace_kvm_mmio((mmio.is_write) ? KVM_TRACE_MMIO_WRITE : KVM_TRACE_MMIO_READ_UNSATISFIED, mmio.len, fault_ipa, - (mmio.is_write) ? data : 0); + (mmio.is_write) ? *vcpu_reg(vcpu, rt) : 0); if (mmio.is_write) - mmio_write_buf(mmio.data, mmio.len, data); + memcpy(mmio.data, vcpu_reg(vcpu, rt), mmio.len); if (vgic_handle_mmio(vcpu, run, &mmio)) return 1; diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 5809069..b0de86b 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -19,7 +19,6 @@ #include <linux/mman.h> #include <linux/kvm_host.h> #include <linux/io.h> -#include <linux/hugetlb.h> #include <trace/events/kvm.h> #include <asm/pgalloc.h> #include <asm/cacheflush.h> @@ -42,8 +41,6 @@ static unsigned long hyp_idmap_start; static unsigned long hyp_idmap_end; static phys_addr_t hyp_idmap_vector; -#define kvm_pmd_huge(_x) (pmd_huge(_x) || pmd_trans_huge(_x)) - static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) { /* @@ -96,29 +93,19 @@ static bool page_empty(void *ptr) static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr) { - if (pud_huge(*pud)) { - pud_clear(pud); - kvm_tlb_flush_vmid_ipa(kvm, addr); - } else { - pmd_t *pmd_table = pmd_offset(pud, 0); - pud_clear(pud); - kvm_tlb_flush_vmid_ipa(kvm, addr); - pmd_free(NULL, pmd_table); - } + pmd_t *pmd_table = pmd_offset(pud, 0); + pud_clear(pud); + kvm_tlb_flush_vmid_ipa(kvm, addr); + pmd_free(NULL, pmd_table); put_page(virt_to_page(pud)); } static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr) { - if (kvm_pmd_huge(*pmd)) { - pmd_clear(pmd); - kvm_tlb_flush_vmid_ipa(kvm, addr); - } else { - pte_t *pte_table = pte_offset_kernel(pmd, 0); - pmd_clear(pmd); - kvm_tlb_flush_vmid_ipa(kvm, addr); - pte_free_kernel(NULL, pte_table); - } + pte_t *pte_table = pte_offset_kernel(pmd, 0); + pmd_clear(pmd); + kvm_tlb_flush_vmid_ipa(kvm, addr); + pte_free_kernel(NULL, pte_table); put_page(virt_to_page(pmd)); } @@ -149,32 +136,18 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp, continue; } - if (pud_huge(*pud)) { - /* - * If we are dealing with a huge pud, just clear it and - * move on. - */ - clear_pud_entry(kvm, pud, addr); - addr = pud_addr_end(addr, end); - continue; - } - pmd = pmd_offset(pud, addr); if (pmd_none(*pmd)) { addr = pmd_addr_end(addr, end); continue; } - if (!kvm_pmd_huge(*pmd)) { - pte = pte_offset_kernel(pmd, addr); - clear_pte_entry(kvm, pte, addr); - next = addr + PAGE_SIZE; - } + pte = pte_offset_kernel(pmd, addr); + clear_pte_entry(kvm, pte, addr); + next = addr + PAGE_SIZE; - /* - * If the pmd entry is to be cleared, walk back up the ladder - */ - if (kvm_pmd_huge(*pmd) || page_empty(pte)) { + /* If we emptied the pte, walk back up the ladder */ + if (page_empty(pte)) { clear_pmd_entry(kvm, pmd, addr); next = pmd_addr_end(addr, end); if (page_empty(pmd) && !page_empty(pud)) { @@ -334,17 +307,6 @@ out: return err; } -static phys_addr_t kvm_kaddr_to_phys(void *kaddr) -{ - if (!is_vmalloc_addr(kaddr)) { - BUG_ON(!virt_addr_valid(kaddr)); - return __pa(kaddr); - } else { - return page_to_phys(vmalloc_to_page(kaddr)) + - offset_in_page(kaddr); - } -} - /** * create_hyp_mappings - duplicate a kernel virtual address range in Hyp mode * @from: The virtual kernel start address of the range @@ -356,27 +318,16 @@ static phys_addr_t kvm_kaddr_to_phys(void *kaddr) */ int create_hyp_mappings(void *from, void *to) { - phys_addr_t phys_addr; - unsigned long virt_addr; + unsigned long phys_addr = virt_to_phys(from); unsigned long start = KERN_TO_HYP((unsigned long)from); unsigned long end = KERN_TO_HYP((unsigned long)to); - start = start & PAGE_MASK; - end = PAGE_ALIGN(end); - - for (virt_addr = start; virt_addr < end; virt_addr += PAGE_SIZE) { - int err; - - phys_addr = kvm_kaddr_to_phys(from + virt_addr - start); - err = __create_hyp_mappings(hyp_pgd, virt_addr, - virt_addr + PAGE_SIZE, - __phys_to_pfn(phys_addr), - PAGE_HYP); - if (err) - return err; - } + /* Check for a valid kernel memory mapping */ + if (!virt_addr_valid(from) || !virt_addr_valid(to - 1)) + return -EINVAL; - return 0; + return __create_hyp_mappings(hyp_pgd, start, end, + __phys_to_pfn(phys_addr), PAGE_HYP); } /** @@ -469,71 +420,29 @@ void kvm_free_stage2_pgd(struct kvm *kvm) kvm->arch.pgd = NULL; } -static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, - phys_addr_t addr) + +static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, + phys_addr_t addr, const pte_t *new_pte, bool iomap) { pgd_t *pgd; pud_t *pud; pmd_t *pmd; + pte_t *pte, old_pte; + /* Create 2nd stage page table mapping - Level 1 */ pgd = kvm->arch.pgd + pgd_index(addr); pud = pud_offset(pgd, addr); if (pud_none(*pud)) { if (!cache) - return NULL; + return 0; /* ignore calls from kvm_set_spte_hva */ pmd = mmu_memory_cache_alloc(cache); pud_populate(NULL, pud, pmd); get_page(virt_to_page(pud)); } - return pmd_offset(pud, addr); -} - -static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache - *cache, phys_addr_t addr, const pmd_t *new_pmd) -{ - pmd_t *pmd, old_pmd; - - pmd = stage2_get_pmd(kvm, cache, addr); - VM_BUG_ON(!pmd); - - /* - * Mapping in huge pages should only happen through a fault. If a - * page is merged into a transparent huge page, the individual - * subpages of that huge page should be unmapped through MMU - * notifiers before we get here. - * - * Merging of CompoundPages is not supported; they should become - * splitting first, unmapped, merged, and mapped back in on-demand. - */ - VM_BUG_ON(pmd_present(*pmd) && pmd_pfn(*pmd) != pmd_pfn(*new_pmd)); - - old_pmd = *pmd; - kvm_set_pmd(pmd, *new_pmd); - if (pmd_present(old_pmd)) - kvm_tlb_flush_vmid_ipa(kvm, addr); - else - get_page(virt_to_page(pmd)); - return 0; -} - -static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, - phys_addr_t addr, const pte_t *new_pte, bool iomap) -{ - pmd_t *pmd; - pte_t *pte, old_pte; - - /* Create stage-2 page table mapping - Level 1 */ - pmd = stage2_get_pmd(kvm, cache, addr); - if (!pmd) { - /* - * Ignore calls from kvm_set_spte_hva for unallocated - * address ranges. - */ - return 0; - } + pmd = pmd_offset(pud, addr); - /* Create stage-2 page mappings - Level 2 */ + /* Create 2nd stage page table mapping - Level 2 */ if (pmd_none(*pmd)) { if (!cache) return 0; /* ignore calls from kvm_set_spte_hva */ @@ -598,60 +507,16 @@ out: return ret; } -static bool transparent_hugepage_adjust(pfn_t *pfnp, phys_addr_t *ipap) -{ - pfn_t pfn = *pfnp; - gfn_t gfn = *ipap >> PAGE_SHIFT; - - if (PageTransCompound(pfn_to_page(pfn))) { - unsigned long mask; - /* - * The address we faulted on is backed by a transparent huge - * page. However, because we map the compound huge page and - * not the individual tail page, we need to transfer the - * refcount to the head page. We have to be careful that the - * THP doesn't start to split while we are adjusting the - * refcounts. - * - * We are sure this doesn't happen, because mmu_notifier_retry - * was successful and we are holding the mmu_lock, so if this - * THP is trying to split, it will be blocked in the mmu - * notifier before touching any of the pages, specifically - * before being able to call __split_huge_page_refcount(). - * - * We can therefore safely transfer the refcount from PG_tail - * to PG_head and switch the pfn from a tail page to the head - * page accordingly. - */ - mask = PTRS_PER_PMD - 1; - VM_BUG_ON((gfn & mask) != (pfn & mask)); - if (pfn & mask) { - *ipap &= PMD_MASK; - kvm_release_pfn_clean(pfn); - pfn &= ~mask; - kvm_get_pfn(pfn); - *pfnp = pfn; - } - - return true; - } - - return false; -} - static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, - struct kvm_memory_slot *memslot, + gfn_t gfn, struct kvm_memory_slot *memslot, unsigned long fault_status) { + pte_t new_pte; + pfn_t pfn; int ret; - bool write_fault, writable, hugetlb = false, force_pte = false; + bool write_fault, writable; unsigned long mmu_seq; - gfn_t gfn = fault_ipa >> PAGE_SHIFT; - unsigned long hva = gfn_to_hva(vcpu->kvm, gfn); - struct kvm *kvm = vcpu->kvm; struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache; - struct vm_area_struct *vma; - pfn_t pfn; write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu)); if (fault_status == FSC_PERM && !write_fault) { @@ -659,26 +524,6 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, return -EFAULT; } - /* Let's check if we will get back a huge page backed by hugetlbfs */ - down_read(¤t->mm->mmap_sem); - vma = find_vma_intersection(current->mm, hva, hva + 1); - if (is_vm_hugetlb_page(vma)) { - hugetlb = true; - gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT; - } else { - /* - * Pages belonging to VMAs not aligned to the PMD mapping - * granularity cannot be mapped using block descriptors even - * if the pages belong to a THP for the process, because the - * stage-2 block descriptor will cover more than a single THP - * and we loose atomicity for unmapping, updates, and splits - * of the THP or other pages in the stage-2 block range. - */ - if (vma->vm_start & ~PMD_MASK) - force_pte = true; - } - up_read(¤t->mm->mmap_sem); - /* We need minimum second+third level pages */ ret = mmu_topup_memory_cache(memcache, 2, KVM_NR_MEM_OBJS); if (ret) @@ -696,40 +541,26 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, */ smp_rmb(); - pfn = gfn_to_pfn_prot(kvm, gfn, write_fault, &writable); + pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write_fault, &writable); if (is_error_pfn(pfn)) return -EFAULT; - spin_lock(&kvm->mmu_lock); - if (mmu_notifier_retry(kvm, mmu_seq)) + new_pte = pfn_pte(pfn, PAGE_S2); + coherent_icache_guest_page(vcpu->kvm, gfn); + + spin_lock(&vcpu->kvm->mmu_lock); + if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) goto out_unlock; - if (!hugetlb && !force_pte) - hugetlb = transparent_hugepage_adjust(&pfn, &fault_ipa); - - if (hugetlb) { - pmd_t new_pmd = pfn_pmd(pfn, PAGE_S2); - new_pmd = pmd_mkhuge(new_pmd); - if (writable) { - kvm_set_s2pmd_writable(&new_pmd); - kvm_set_pfn_dirty(pfn); - } - coherent_icache_guest_page(kvm, hva & PMD_MASK, PMD_SIZE); - ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd); - } else { - pte_t new_pte = pfn_pte(pfn, PAGE_S2); - if (writable) { - kvm_set_s2pte_writable(&new_pte); - kvm_set_pfn_dirty(pfn); - } - coherent_icache_guest_page(kvm, hva, PAGE_SIZE); - ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, false); + if (writable) { + kvm_set_s2pte_writable(&new_pte); + kvm_set_pfn_dirty(pfn); } - + stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false); out_unlock: - spin_unlock(&kvm->mmu_lock); + spin_unlock(&vcpu->kvm->mmu_lock); kvm_release_pfn_clean(pfn); - return ret; + return 0; } /** @@ -798,7 +629,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run) memslot = gfn_to_memslot(vcpu->kvm, gfn); - ret = user_mem_abort(vcpu, fault_ipa, memslot, fault_status); + ret = user_mem_abort(vcpu, fault_ipa, gfn, memslot, fault_status); if (ret == 0) ret = 1; out_unlock: diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 0881bf1..86a693a 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -18,7 +18,6 @@ #include <linux/kvm_host.h> #include <linux/wait.h> -#include <asm/cputype.h> #include <asm/kvm_emulate.h> #include <asm/kvm_psci.h> @@ -35,30 +34,22 @@ static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu) static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) { struct kvm *kvm = source_vcpu->kvm; - struct kvm_vcpu *vcpu = NULL, *tmp; + struct kvm_vcpu *vcpu; wait_queue_head_t *wq; unsigned long cpu_id; - unsigned long mpidr; phys_addr_t target_pc; - int i; cpu_id = *vcpu_reg(source_vcpu, 1); if (vcpu_mode_is_32bit(source_vcpu)) cpu_id &= ~((u32) 0); - kvm_for_each_vcpu(i, tmp, kvm) { - mpidr = kvm_vcpu_get_mpidr(tmp); - if ((mpidr & MPIDR_HWID_BITMASK) == (cpu_id & MPIDR_HWID_BITMASK)) { - vcpu = tmp; - break; - } - } - - if (!vcpu) + if (cpu_id >= atomic_read(&kvm->online_vcpus)) return KVM_PSCI_RET_INVAL; target_pc = *vcpu_reg(source_vcpu, 2); + vcpu = kvm_get_vcpu(kvm, cpu_id); + wq = kvm_arch_vcpu_wq(vcpu); if (!waitqueue_active(wq)) return KVM_PSCI_RET_INVAL; @@ -71,10 +62,6 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) vcpu_set_thumb(vcpu); } - /* Propagate caller endianness */ - if (kvm_vcpu_is_be(source_vcpu)) - kvm_vcpu_set_be(vcpu); - *vcpu_pc(vcpu) = target_pc; vcpu->arch.pause = false; smp_mb(); /* Make sure the above is visible */ diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c index f558c07..c02ba4a 100644 --- a/arch/arm/kvm/reset.c +++ b/arch/arm/kvm/reset.c @@ -30,14 +30,16 @@ #include <kvm/arm_arch_timer.h> /****************************************************************************** - * Cortex-A15 and Cortex-A7 Reset Values + * Cortex-A15 Reset Values */ -static struct kvm_regs cortexa_regs_reset = { +static const int a15_max_cpu_idx = 3; + +static struct kvm_regs a15_regs_reset = { .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT, }; -static const struct kvm_irq_level cortexa_vtimer_irq = { +static const struct kvm_irq_level a15_vtimer_irq = { { .irq = 27 }, .level = 1, }; @@ -60,11 +62,12 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) const struct kvm_irq_level *cpu_vtimer_irq; switch (vcpu->arch.target) { - case KVM_ARM_TARGET_CORTEX_A7: case KVM_ARM_TARGET_CORTEX_A15: - reset_regs = &cortexa_regs_reset; + if (vcpu->vcpu_id > a15_max_cpu_idx) + return -EINVAL; + reset_regs = &a15_regs_reset; vcpu->arch.midr = read_cpuid_id(); - cpu_vtimer_irq = &cortexa_vtimer_irq; + cpu_vtimer_irq = &a15_vtimer_irq; break; default: return -ENODEV; diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 47d7338..bd454b0 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -41,6 +41,7 @@ else endif lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o +lib-$(CONFIG_ARCH_SHARK) += io-shark.o $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h index 52886b8..d6408d1 100644 --- a/arch/arm/lib/bitops.h +++ b/arch/arm/lib/bitops.h @@ -10,11 +10,6 @@ UNWIND( .fnstart ) and r3, r0, #31 @ Get bit offset mov r0, r0, lsr #5 add r1, r1, r0, lsl #2 @ Get word offset -#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) - .arch_extension mp - ALT_SMP(W(pldw) [r1]) - ALT_UP(W(nop)) -#endif mov r3, r2, lsl r3 1: ldrex r2, [r1] \instr r2, r2, r3 diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S index bc1033b..36b668d 100644 --- a/arch/arm/lib/delay-loop.S +++ b/arch/arm/lib/delay-loop.S @@ -40,7 +40,6 @@ ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0x7fffff06 /* * loops = r0 * HZ * loops_per_jiffy / 1000000 */ - .align 3 @ Delay routine ENTRY(__loop_delay) diff --git a/arch/arm/lib/io-shark.c b/arch/arm/lib/io-shark.c new file mode 100644 index 0000000..8242539 --- /dev/null +++ b/arch/arm/lib/io-shark.c @@ -0,0 +1,13 @@ +/* + * linux/arch/arm/lib/io-shark.c + * + * by Alexander Schulz + * + * derived from: + * linux/arch/arm/lib/io-ebsa.S + * Copyright (C) 1995, 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index 3e58d71..025f742 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -18,7 +18,6 @@ #include <linux/hardirq.h> /* for in_atomic() */ #include <linux/gfp.h> #include <linux/highmem.h> -#include <linux/hugetlb.h> #include <asm/current.h> #include <asm/page.h> @@ -41,35 +40,7 @@ pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) return 0; pmd = pmd_offset(pud, addr); - if (unlikely(pmd_none(*pmd))) - return 0; - - /* - * A pmd can be bad if it refers to a HugeTLB or THP page. - * - * Both THP and HugeTLB pages have the same pmd layout - * and should not be manipulated by the pte functions. - * - * Lock the page table for the destination and check - * to see that it's still huge and whether or not we will - * need to fault on write, or if we have a splitting THP. - */ - if (unlikely(pmd_thp_or_huge(*pmd))) { - ptl = ¤t->mm->page_table_lock; - spin_lock(ptl); - if (unlikely(!pmd_thp_or_huge(*pmd) - || pmd_hugewillfault(*pmd) - || pmd_trans_splitting(*pmd))) { - spin_unlock(ptl); - return 0; - } - - *ptep = NULL; - *ptlp = ptl; - return 1; - } - - if (unlikely(pmd_bad(*pmd))) + if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) return 0; pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl); @@ -123,10 +94,7 @@ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) from += tocopy; n -= tocopy; - if (pte) - pte_unmap_unlock(pte, ptl); - else - spin_unlock(ptl); + pte_unmap_unlock(pte, ptl); } if (!atomic) up_read(¤t->mm->mmap_sem); @@ -179,10 +147,7 @@ __clear_user_memset(void __user *addr, unsigned long n) addr += tocopy; n -= tocopy; - if (pte) - pte_unmap_unlock(pte, ptl); - else - spin_unlock(ptl); + pte_unmap_unlock(pte, ptl); } up_read(¤t->mm->mmap_sem); diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 90aab2d..3b0a953 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o gpio.o setup.o sysirq_mask.o +obj-y := irq.o gpio.o setup.o obj-m := obj-n := obj- := @@ -98,6 +98,7 @@ obj-y += leds.o # Power Management obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o +obj-$(CONFIG_CPU_IDLE) += cpuidle.o ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 25805f2..4aad93d 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -27,7 +27,6 @@ #include "generic.h" #include "clock.h" #include "sam9_smc.h" -#include "pm.h" /* -------------------------------------------------------------------- * Clocks @@ -328,7 +327,6 @@ static void __init at91rm9200_ioremap_registers(void) { at91rm9200_ioremap_st(AT91RM9200_BASE_ST); at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256); - at91_pm_set_standby(at91rm9200_standby); } static void __init at91rm9200_initialize(void) diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index bc7b363..f607deb 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) static struct clock_event_device clkevt = { .name = "at91_tick", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, .rating = 150, .set_next_event = clkevt32k_next_event, .set_mode = clkevt32k_mode, @@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void) at91_st_write(AT91_ST_RTMR, 1); /* Setup timer clockevent, with minimum of two ticks (important!!) */ + clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); + clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; clkevt.cpumask = cpumask_of(0); - clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, - 2, AT91_ST_ALMV); + clockevents_register_device(&clkevt); /* register clocksource */ clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index d6a1fa8..5de6074 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -28,7 +28,6 @@ #include "generic.h" #include "clock.h" #include "sam9_smc.h" -#include "pm.h" /* -------------------------------------------------------------------- * Clocks @@ -343,7 +342,6 @@ static void __init at91sam9260_ioremap_registers(void) at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX); - at91_pm_set_standby(at91sam9_sdram_standby); } static void __init at91sam9260_initialize(void) @@ -351,8 +349,6 @@ static void __init at91sam9260_initialize(void) arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9260_gpio, 3); } diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 23ba1d8..0e07932 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -27,7 +27,6 @@ #include "generic.h" #include "clock.h" #include "sam9_smc.h" -#include "pm.h" /* -------------------------------------------------------------------- * Clocks @@ -285,7 +284,6 @@ static void __init at91sam9261_ioremap_registers(void) at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX); - at91_pm_set_standby(at91sam9_sdram_standby); } static void __init at91sam9261_initialize(void) @@ -293,8 +291,6 @@ static void __init at91sam9261_initialize(void) arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9261_gpio, 3); } diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index b2a3474..629ea5f 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -465,7 +465,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) static u64 lcdc_dmamask = DMA_BIT_MASK(32); -static struct atmel_lcdfb_pdata lcdc_data; +static struct atmel_lcdfb_info lcdc_data; static struct resource lcdc_resources[] = { [0] = { @@ -498,7 +498,7 @@ static struct platform_device at91_lcdc_device = { .num_resources = ARRAY_SIZE(lcdc_resources), }; -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) { return; @@ -559,7 +559,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) platform_device_register(&at91_lcdc_device); } #else -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} #endif diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 7eccb0f..6ce7d18 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -26,7 +26,6 @@ #include "generic.h" #include "clock.h" #include "sam9_smc.h" -#include "pm.h" /* -------------------------------------------------------------------- * Clocks @@ -322,7 +321,6 @@ static void __init at91sam9263_ioremap_registers(void) at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX); - at91_pm_set_standby(at91sam9_sdram_standby); } static void __init at91sam9263_initialize(void) @@ -330,9 +328,6 @@ static void __init at91sam9263_initialize(void) arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0); - at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9263_gpio, 5); } diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 4aeaddd..858c8aa 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -832,7 +832,7 @@ void __init at91_add_device_can(struct at91_can_data *data) {} #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) static u64 lcdc_dmamask = DMA_BIT_MASK(32); -static struct atmel_lcdfb_pdata lcdc_data; +static struct atmel_lcdfb_info lcdc_data; static struct resource lcdc_resources[] = { [0] = { @@ -859,7 +859,7 @@ static struct platform_device at91_lcdc_device = { .num_resources = ARRAY_SIZE(lcdc_resources), }; -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) return; @@ -891,7 +891,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) platform_device_register(&at91_lcdc_device); } #else -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} #endif diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9405aa0..474ee04 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -26,7 +26,6 @@ #include "generic.h" #include "clock.h" #include "sam9_smc.h" -#include "pm.h" /* -------------------------------------------------------------------- * Clocks @@ -371,7 +370,6 @@ static void __init at91sam9g45_ioremap_registers(void) at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX); - at91_pm_set_standby(at91_ddr_standby); } static void __init at91sam9g45_initialize(void) @@ -379,9 +377,6 @@ static void __init at91sam9g45_initialize(void) arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9g45_restart; - at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); - at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9g45_gpio, 5); } diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index cb36fa8..acb703e 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -965,7 +965,7 @@ void __init at91_add_device_isi(struct isi_platform_data *data, #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) static u64 lcdc_dmamask = DMA_BIT_MASK(32); -static struct atmel_lcdfb_pdata lcdc_data; +static struct atmel_lcdfb_info lcdc_data; static struct resource lcdc_resources[] = { [0] = { @@ -991,7 +991,7 @@ static struct platform_device at91_lcdc_device = { .num_resources = ARRAY_SIZE(lcdc_resources), }; -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) return; @@ -1037,7 +1037,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) platform_device_register(&at91_lcdc_device); } #else -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} #endif diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 388ec3a..c7d670d 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -169,7 +169,6 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk), CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk), CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk), - CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), @@ -224,13 +223,7 @@ static void __init at91sam9n12_map_io(void) at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); } -static void __init at91sam9n12_initialize(void) -{ - at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC); -} - AT91_SOC_START(at91sam9n12) .map_io = at91sam9n12_map_io, .register_clocks = at91sam9n12_register_clocks, - .init = at91sam9n12_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 0750ffb..d4ec0d9 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -27,7 +27,6 @@ #include "generic.h" #include "clock.h" #include "sam9_smc.h" -#include "pm.h" /* -------------------------------------------------------------------- * Clocks @@ -288,7 +287,6 @@ static void __init at91sam9rl_ioremap_registers(void) at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX); - at91_pm_set_standby(at91sam9_sdram_standby); } static void __init at91sam9rl_initialize(void) @@ -296,9 +294,6 @@ static void __init at91sam9rl_initialize(void) arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); - at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9rl_gpio, 4); } diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index a698bda..352468f 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -498,7 +498,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) static u64 lcdc_dmamask = DMA_BIT_MASK(32); -static struct atmel_lcdfb_pdata lcdc_data; +static struct atmel_lcdfb_info lcdc_data; static struct resource lcdc_resources[] = { [0] = { @@ -525,7 +525,7 @@ static struct platform_device at91_lcdc_device = { .num_resources = ARRAY_SIZE(lcdc_resources), }; -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) { return; @@ -557,7 +557,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) platform_device_register(&at91_lcdc_device); } #else -void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} #endif diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index e8a2e07..916e5a1 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -322,11 +322,6 @@ static void __init at91sam9x5_map_io(void) at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); } -static void __init at91sam9x5_initialize(void) -{ - at91_sysirq_mask_rtc(AT91SAM9X5_BASE_RTC); -} - /* -------------------------------------------------------------------- * Interrupt initialization * -------------------------------------------------------------------- */ @@ -334,5 +329,4 @@ static void __init at91sam9x5_initialize(void) AT91_SOC_START(at91sam9x5) .map_io = at91sam9x5_map_io, .register_clocks = at91sam9x5_register_clocks, - .init = at91sam9x5_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 112e867..ade948b 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -112,7 +112,7 @@ static struct spi_board_info cam60_spi_devices[] __initdata = { /* * MACB Ethernet device */ -static struct macb_platform_data cam60_macb_data __initdata = { +static struct __initdata macb_platform_data cam60_macb_data = { .phy_irq_pin = AT91_PIN_PB5, .is_rmii = 0, }; diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c index 3a185fa..3fcb662 100644 --- a/arch/arm/mach-at91/board-dt-rm9200.c +++ b/arch/arm/mach-at91/board-dt-rm9200.c @@ -14,6 +14,7 @@ #include <linux/gpio.h> #include <linux/of.h> #include <linux/of_irq.h> +#include <linux/of_platform.h> #include <asm/setup.h> #include <asm/irq.h> @@ -35,6 +36,11 @@ static void __init at91rm9200_dt_init_irq(void) of_irq_init(irq_of_match); } +static void __init at91rm9200_dt_device_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + static const char *at91rm9200_dt_board_compat[] __initdata = { "atmel,at91rm9200", NULL @@ -46,5 +52,6 @@ DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") .handle_irq = at91_aic_handle_irq, .init_early = at91rm9200_dt_initialize, .init_irq = at91rm9200_dt_init_irq, + .init_machine = at91rm9200_dt_device_init, .dt_compat = at91rm9200_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c index 3dab868..8db3013 100644 --- a/arch/arm/mach-at91/board-dt-sam9.c +++ b/arch/arm/mach-at91/board-dt-sam9.c @@ -13,6 +13,7 @@ #include <linux/gpio.h> #include <linux/of.h> #include <linux/of_irq.h> +#include <linux/of_platform.h> #include <asm/setup.h> #include <asm/irq.h> @@ -36,6 +37,11 @@ static void __init at91_dt_init_irq(void) of_irq_init(irq_of_match); } +static void __init at91_dt_device_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + static const char *at91_dt_board_compat[] __initdata = { "atmel,at91sam9", NULL @@ -48,5 +54,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") .handle_irq = at91_aic_handle_irq, .init_early = at91_dt_initialize, .init_irq = at91_dt_init_irq, + .init_machine = at91_dt_device_init, .dt_compat = at91_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index f4f8735..0b153c8 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -28,7 +28,7 @@ #include <linux/spi/spi.h> #include <linux/spi/at73c213.h> #include <linux/clk.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/gpio_keys.h> #include <linux/input.h> diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 473546b..d343762 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -389,7 +389,7 @@ static struct fb_monspecs at91fb_default_stn_monspecs = { | ATMEL_LCDC_IFWIDTH_4 \ | ATMEL_LCDC_SCANMOD_SINGLE) -static void at91_lcdc_stn_power_control(struct atmel_lcdfb_pdata *pdata, int on) +static void at91_lcdc_stn_power_control(int on) { /* backlight */ if (on) { /* power up */ @@ -401,7 +401,7 @@ static void at91_lcdc_stn_power_control(struct atmel_lcdfb_pdata *pdata, int on) } } -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .default_bpp = 1, .default_dmacon = ATMEL_LCDC_DMAEN, .default_lcdcon2 = AT91SAM9261_DEFAULT_STN_LCDCON2, @@ -445,7 +445,7 @@ static struct fb_monspecs at91fb_default_tft_monspecs = { | ATMEL_LCDC_DISTYPE_TFT \ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -static void at91_lcdc_tft_power_control(struct atmel_lcdfb_pdata *pdata, int on) +static void at91_lcdc_tft_power_control(int on) { if (on) at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ @@ -453,7 +453,7 @@ static void at91_lcdc_tft_power_control(struct atmel_lcdfb_pdata *pdata, int on) at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ } -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .lcdcon_is_backlight = true, .default_bpp = 16, .default_dmacon = ATMEL_LCDC_DMAEN, @@ -465,7 +465,7 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { #endif #else -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; +static struct atmel_lcdfb_info __initdata ek_lcdc_data; #endif diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 2f93191..3284df0 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -27,7 +27,7 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/fb.h> #include <linux/gpio_keys.h> #include <linux/input.h> @@ -275,13 +275,13 @@ static struct fb_monspecs at91fb_default_monspecs = { | ATMEL_LCDC_DISTYPE_TFT \ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on) +static void at91_lcdc_power_control(int on) { at91_set_gpio_value(AT91_PIN_PA30, on); } /* Driver datas */ -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .lcdcon_is_backlight = true, .default_bpp = 16, .default_dmacon = ATMEL_LCDC_DMAEN, @@ -292,7 +292,7 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { }; #else -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; +static struct atmel_lcdfb_info __initdata ek_lcdc_data; #endif diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index ef39078..2a94896 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -284,7 +284,7 @@ static struct fb_monspecs at91fb_default_monspecs = { | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) /* Driver datas */ -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .lcdcon_is_backlight = true, .default_bpp = 32, .default_dmacon = ATMEL_LCDC_DMAEN, @@ -295,7 +295,7 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { }; #else -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; +static struct atmel_lcdfb_info __initdata ek_lcdc_data; #endif diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index 604eecf..aa265dc 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -170,7 +170,7 @@ static struct fb_monspecs at91fb_default_monspecs = { | ATMEL_LCDC_DISTYPE_TFT \ | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) -static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on) +static void at91_lcdc_power_control(int on) { if (on) at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */ @@ -179,7 +179,7 @@ static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on) } /* Driver datas */ -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { +static struct atmel_lcdfb_info __initdata ek_lcdc_data = { .lcdcon_is_backlight = true, .default_bpp = 16, .default_dmacon = ATMEL_LCDC_DMAEN, @@ -191,7 +191,7 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { }; #else -static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; +static struct atmel_lcdfb_info __initdata ek_lcdc_data; #endif diff --git a/arch/arm/mach-at91/board.h b/arch/arm/mach-at91/board.h index 6c08b34..4a234fb 100644 --- a/arch/arm/mach-at91/board.h +++ b/arch/arm/mach-at91/board.h @@ -107,8 +107,8 @@ extern void __init at91_add_device_pwm(u32 mask); extern void __init at91_add_device_ssc(unsigned id, unsigned pins); /* LCD Controller */ -struct atmel_lcdfb_pdata; -extern void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data); +struct atmel_lcdfb_info; +extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); /* AC97 */ extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c new file mode 100644 index 0000000..4ec6a6d --- /dev/null +++ b/arch/arm/mach-at91/cpuidle.c @@ -0,0 +1,68 @@ +/* + * based on arch/arm/mach-kirkwood/cpuidle.c + * + * CPU idle support for AT91 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * The cpu idle uses wait-for-interrupt and RAM self refresh in order + * to implement two idle states - + * #1 wait-for-interrupt + * #2 wait-for-interrupt and RAM self refresh + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/cpuidle.h> +#include <linux/io.h> +#include <linux/export.h> +#include <asm/proc-fns.h> +#include <asm/cpuidle.h> +#include <mach/cpu.h> + +#include "pm.h" + +#define AT91_MAX_STATES 2 + +/* Actual code that puts the SoC in different idle states */ +static int at91_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + if (cpu_is_at91rm9200()) + at91rm9200_standby(); + else if (cpu_is_at91sam9g45()) + at91sam9g45_standby(); + else if (cpu_is_at91sam9263()) + at91sam9263_standby(); + else + at91sam9_standby(); + + return index; +} + +static struct cpuidle_driver at91_idle_driver = { + .name = "at91_idle", + .owner = THIS_MODULE, + .states[0] = ARM_CPUIDLE_WFI_STATE, + .states[1] = { + .enter = at91_enter_idle, + .exit_latency = 10, + .target_residency = 10000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "RAM_SR", + .desc = "WFI and DDR Self Refresh", + }, + .state_count = AT91_MAX_STATES, +}; + +/* Initialize CPU idle by registering the idle states */ +static int __init at91_init_cpuidle(void) +{ + return cpuidle_register(&at91_idle_driver, NULL); +} + +device_initcall(at91_init_cpuidle); diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 26dee3c..dc6e2f5 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -34,8 +34,6 @@ extern int __init at91_aic_of_init(struct device_node *node, struct device_node *parent); extern int __init at91_aic5_of_init(struct device_node *node, struct device_node *parent); -extern void __init at91_sysirq_mask_rtc(u32 rtc_base); -extern void __init at91_sysirq_mask_rtt(u32 rtt_base); /* Timer */ diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h index c287307..048a57f 100644 --- a/arch/arm/mach-at91/include/mach/at91_adc.h +++ b/arch/arm/mach-at91/include/mach/at91_adc.h @@ -60,48 +60,14 @@ #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ -#define AT91_ADC_IER_PEN (1 << 29) -#define AT91_ADC_IER_NOPEN (1 << 30) -#define AT91_ADC_IER_XRDY (1 << 20) -#define AT91_ADC_IER_YRDY (1 << 21) -#define AT91_ADC_IER_PRDY (1 << 22) -#define AT91_ADC_ISR_PENS (1 << 31) #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ #define AT91_ADC_DATA (0x3ff) #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ -#define AT91_ADC_ACR 0x94 /* Analog Control Register */ -#define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ - -#define AT91_ADC_TSMR 0xB0 -#define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ -#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) -#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) -#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) -#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) -#define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ -#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) -#define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ -#define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ -#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) -#define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ -#define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ -#define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ - -#define AT91_ADC_TSXPOSR 0xB4 -#define AT91_ADC_TSYPOSR 0xB8 -#define AT91_ADC_TSPRESSR 0xBC - #define AT91_ADC_TRGR_9260 AT91_ADC_MR #define AT91_ADC_TRGR_9G45 0x08 #define AT91_ADC_TRGR_9X5 0xC0 -/* Trigger Register bit field */ -#define AT91_ADC_TRGR_TRGPER (0xffff << 16) -#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) -#define AT91_ADC_TRGR_TRGMOD (0x7 << 0) -#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) - #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h index 0151bcf..d374b87 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h @@ -49,11 +49,6 @@ #define AT91SAM9N12_BASE_USART3 0xf8028000 /* - * System Peripherals - */ -#define AT91SAM9N12_BASE_RTC 0xfffffeb0 - -/* * Internal Memory. */ #define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 2fc76c4..c75ee19 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -55,11 +55,6 @@ #define AT91SAM9X5_BASE_USART2 0xf8024000 /* - * System Peripherals - */ -#define AT91SAM9X5_BASE_RTC 0xfffffeb0 - -/* * Internal Memory. */ #define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 25613d8..31096a8 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -73,11 +73,6 @@ #define SAMA5D3_BASE_USART3 0xf8024000 /* - * System Peripherals - */ -#define SAMA5D3_BASE_RTC 0xfffffeb0 - -/* * Internal Memory */ #define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 9986542..15afb5d 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -39,8 +39,6 @@ #include "at91_rstc.h" #include "at91_shdwc.h" -static void (*at91_pm_standby)(void); - static void __init show_reset_status(void) { static char reset[] __initdata = "reset"; @@ -268,8 +266,14 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ - if (at91_pm_standby) - at91_pm_standby(); + if (cpu_is_at91rm9200()) + at91rm9200_standby(); + else if (cpu_is_at91sam9g45()) + at91sam9g45_standby(); + else if (cpu_is_at91sam9263()) + at91sam9263_standby(); + else + at91sam9_standby(); break; case PM_SUSPEND_ON: @@ -310,18 +314,6 @@ static const struct platform_suspend_ops at91_pm_ops = { .end = at91_pm_end, }; -static struct platform_device at91_cpuidle_device = { - .name = "cpuidle-at91", -}; - -void at91_pm_set_standby(void (*at91_standby)(void)) -{ - if (at91_standby) { - at91_cpuidle_device.dev.platform_data = at91_standby; - at91_pm_standby = at91_standby; - } -} - static int __init at91_pm_init(void) { #ifdef CONFIG_AT91_SLOW_CLOCK @@ -333,9 +325,6 @@ static int __init at91_pm_init(void) /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ if (cpu_is_at91rm9200()) at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); - - if (at91_cpuidle_device.dev.platform_data) - platform_device_register(&at91_cpuidle_device); suspend_set_ops(&at91_pm_ops); diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index c5101dc..2f5908f 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -11,17 +11,9 @@ #ifndef __ARCH_ARM_MACH_AT91_PM #define __ARCH_ARM_MACH_AT91_PM -#include <asm/proc-fns.h> - #include <mach/at91_ramc.h> #include <mach/at91rm9200_sdramc.h> -#ifdef CONFIG_PM -extern void at91_pm_set_standby(void (*at91_standby)(void)); -#else -static inline void at91_pm_set_standby(void (*at91_standby)(void)) { } -#endif - /* * The AT91RM9200 goes into self-refresh mode with this command, and will * terminate self-refresh automatically on the next SDRAM access. @@ -53,18 +45,16 @@ static inline void at91rm9200_standby(void) /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ -static inline void at91_ddr_standby(void) +static inline void at91sam9g45_standby(void) { /* Those two values allow us to delay self-refresh activation * to the maximum. */ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; + u32 lpr0, lpr1; + u32 saved_lpr0, saved_lpr1; - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); - lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; - lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - } + saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); + lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; + lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; @@ -72,29 +62,25 @@ static inline void at91_ddr_standby(void) /* self-refresh mode now */ at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); + at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); cpu_do_idle(); at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ -static inline void at91sam9_sdram_standby(void) +static inline void at91sam9263_standby(void) { - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; + u32 lpr0, lpr1; + u32 saved_lpr0, saved_lpr1; - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); - lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; - lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; - } + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; @@ -102,14 +88,27 @@ static inline void at91sam9_sdram_standby(void) /* self-refresh mode now */ at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); cpu_do_idle(); at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); +} + +static inline void at91sam9_standby(void) +{ + u32 saved_lpr, lpr; + + saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR); + + lpr = saved_lpr & ~AT91_SDRAMC_LPCB; + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | + AT91_SDRAMC_LPCB_SELF_REFRESH); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); } #endif diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index a28873f..4012797 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c @@ -95,19 +95,19 @@ static struct clk twi0_clk = { .name = "twi0_clk", .pid = SAMA5D3_ID_TWI0, .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, + .div = AT91_PMC_PCR_DIV2, }; static struct clk twi1_clk = { .name = "twi1_clk", .pid = SAMA5D3_ID_TWI1, .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, + .div = AT91_PMC_PCR_DIV2, }; static struct clk twi2_clk = { .name = "twi2_clk", .pid = SAMA5D3_ID_TWI2, .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, + .div = AT91_PMC_PCR_DIV2, }; static struct clk mmc0_clk = { .name = "mci0_clk", @@ -371,13 +371,7 @@ static void __init sama5d3_map_io(void) at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); } -static void __init sama5d3_initialize(void) -{ - at91_sysirq_mask_rtc(SAMA5D3_BASE_RTC); -} - AT91_SOC_START(sama5d3) .map_io = sama5d3_map_io, .register_clocks = sama5d3_register_clocks, - .init = sama5d3_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 094b345..b17fbcf 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -23,7 +23,6 @@ #include "at91_shdwc.h" #include "soc.h" #include "generic.h" -#include "pm.h" struct at91_init_soc __initdata at91_boot_soc; @@ -377,16 +376,15 @@ static void at91_dt_rstc(void) } static struct of_device_id ramc_ids[] = { - { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, - { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, - { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, + { .compatible = "atmel,at91rm9200-sdramc" }, + { .compatible = "atmel,at91sam9260-sdramc" }, + { .compatible = "atmel,at91sam9g45-ddramc" }, { /*sentinel*/ } }; static void at91_dt_ramc(void) { struct device_node *np; - const struct of_device_id *of_id; np = of_find_matching_node(NULL, ramc_ids); if (!np) @@ -398,12 +396,6 @@ static void at91_dt_ramc(void) /* the controller may have 2 banks */ at91_ramc_base[1] = of_iomap(np, 1); - of_id = of_match_node(ramc_ids, np); - if (!of_id) - pr_warn("AT91: ramc no standby function available\n"); - else - at91_pm_set_standby(of_id->data); - of_node_put(np); } diff --git a/arch/arm/mach-at91/sysirq_mask.c b/arch/arm/mach-at91/sysirq_mask.c deleted file mode 100644 index 2ba694f..0000000 --- a/arch/arm/mach-at91/sysirq_mask.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * sysirq_mask.c - System-interrupt masking - * - * Copyright (C) 2013 Johan Hovold <jhovold@gmail.com> - * - * Functions to disable system interrupts from backup-powered peripherals. - * - * The RTC and RTT-peripherals are generally powered by backup power (VDDBU) - * and are not reset on wake-up, user, watchdog or software reset. This means - * that their interrupts may be enabled during early boot (e.g. after a user - * reset). - * - * As the RTC and RTT share the system-interrupt line with the PIT, an - * interrupt occurring before a handler has been installed would lead to the - * system interrupt being disabled and prevent the system from booting. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <linux/io.h> -#include <mach/at91_rtt.h> - -#include "generic.h" - -#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ -#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */ - -void __init at91_sysirq_mask_rtc(u32 rtc_base) -{ - void __iomem *base; - u32 mask; - - base = ioremap(rtc_base, 64); - if (!base) - return; - - mask = readl_relaxed(base + AT91_RTC_IMR); - if (mask) { - pr_info("AT91: Disabling rtc irq\n"); - writel_relaxed(mask, base + AT91_RTC_IDR); - (void)readl_relaxed(base + AT91_RTC_IMR); /* flush */ - } - - iounmap(base); -} - -void __init at91_sysirq_mask_rtt(u32 rtt_base) -{ - void __iomem *base; - void __iomem *reg; - u32 mode; - - base = ioremap(rtt_base, 16); - if (!base) - return; - - reg = base + AT91_RTT_MR; - - mode = readl_relaxed(reg); - if (mode & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)) { - pr_info("AT91: Disabling rtt irq\n"); - mode &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); - writel_relaxed(mode, reg); - (void)readl_relaxed(reg); /* flush */ - } - - iounmap(base); -} diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 9fe6d88..69d67f7 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -1,16 +1,5 @@ config ARCH_BCM - bool "Broadcom SoC Support" - depends on ARCH_MULTIPLATFORM - help - This enables support for Broadcom ARM based SoC - chips - -if ARCH_BCM - -menu "Broadcom SoC Selection" - -config ARCH_BCM_MOBILE - bool "Broadcom Mobile SoC" if ARCH_MULTI_V7 + bool "Broadcom SoC" if ARCH_MULTI_V7 depends on MMU select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_754322 @@ -20,17 +9,12 @@ config ARCH_BCM_MOBILE select CLKSRC_OF select GENERIC_CLOCKEVENTS select GENERIC_TIME - select GPIO_BCM_KONA + select GPIO_BCM select SPARSE_IRQ select TICK_ONESHOT select CACHE_L2X0 - select HAVE_ARM_ARCH_TIMER help - This enables support for systems based on Broadcom mobile SoCs. + This enables support for system based on Broadcom SoCs. It currently supports the 'BCM281XX' family, which includes BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 variants. - -endmenu - -endif diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index c2ccd5a..e3d0303 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -10,6 +10,6 @@ # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o +obj-$(CONFIG_ARCH_BCM) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c index cb3dc36..8d9f931 100644 --- a/arch/arm/mach-bcm/board_bcm281xx.c +++ b/arch/arm/mach-bcm/board_bcm281xx.c @@ -67,7 +67,8 @@ static void __init board_init(void) static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, }; -DT_MACHINE_START(BCM11351_DT, "BCM281xx Broadcom Application Processor") +DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") + .init_time = clocksource_of_init, .init_machine = board_init, .restart = bcm_kona_restart, .dt_compat = bcm11351_dt_compat, diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c index 70f2f39..40686d7 100644 --- a/arch/arm/mach-bcm2835/bcm2835.c +++ b/arch/arm/mach-bcm2835/bcm2835.c @@ -14,10 +14,11 @@ #include <linux/delay.h> #include <linux/init.h> -#include <linux/irqchip.h> +#include <linux/irqchip/bcm2835.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/clk/bcm2835.h> +#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -130,8 +131,10 @@ static const char * const bcm2835_compat[] = { DT_MACHINE_START(BCM2835, "BCM2835") .map_io = bcm2835_map_io, - .init_irq = irqchip_init, + .init_irq = bcm2835_init_irq, + .handle_irq = bcm2835_handle_irq, .init_machine = bcm2835_init, + .init_time = clocksource_of_init, .restart = bcm2835_restart, .dt_compat = bcm2835_compat MACHINE_END diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 134641d..4ca2f3c 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -29,12 +29,12 @@ #include <linux/clockchips.h> #include <linux/clocksource.h> #include <linux/clk-provider.h> -#include <linux/sched_clock.h> #include <asm/exception.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> +#include <asm/sched_clock.h> #include <asm/system_misc.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index a075b3e..e026b19 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -40,6 +40,7 @@ config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ + select CPU_FREQ_TABLE select CP_INTC config ARCH_DAVINCI_DA8XX diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index d1f45af..c4bdc0a 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -17,24 +17,22 @@ #include <linux/platform_device.h> #include <linux/i2c.h> #include <linux/i2c/pcf857x.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> -#include <linux/platform_data/spi-davinci.h> -#include <linux/platform_data/usb-davinci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/common.h> #include <mach/cp_intc.h> #include <mach/mux.h> +#include <linux/platform_data/mtd-davinci.h> #include <mach/da8xx.h> +#include <linux/platform_data/usb-davinci.h> +#include <linux/platform_data/mtd-davinci-aemif.h> +#include <linux/platform_data/spi-davinci.h> #define DA830_EVM_PHY_ID "" /* @@ -76,7 +74,7 @@ static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler) if (handler != NULL) { da830_evm_usb_ocic_handler = handler; - error = request_irq(irq, da830_evm_usb_ocic_irq, + error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "OHCI over-current indicator", NULL); if (error) @@ -593,10 +591,6 @@ static __init void da830_evm_init(void) struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; - ret = da830_register_gpio(); - if (ret) - pr_warn("da830_evm_init: GPIO init failed: %d\n", ret); - ret = da830_register_edma(da830_edma_rsv); if (ret) pr_warning("da830_evm_init: edma registration failed: %d\n", diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index e0af0ec..dd1fb24 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -18,7 +18,7 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/platform_data/pca953x.h> #include <linux/input.h> #include <linux/input/tps6507x-ts.h> @@ -28,7 +28,6 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/platform_device.h> -#include <linux/platform_data/gpio-davinci.h> #include <linux/platform_data/mtd-davinci.h> #include <linux/platform_data/mtd-davinci-aemif.h> #include <linux/platform_data/spi-davinci.h> @@ -39,7 +38,6 @@ #include <linux/spi/flash.h> #include <linux/wl12xx.h> -#include <mach/common.h> #include <mach/cp_intc.h> #include <mach/da8xx.h> #include <mach/mux.h> @@ -1439,10 +1437,6 @@ static __init void da850_evm_init(void) { int ret; - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - ret = pmic_tps65070_init(); if (ret) pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index ecdc7d4..42b23a3 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -22,17 +22,15 @@ #include <media/tvp514x.h> #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/usb-davinci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <linux/platform_data/i2c-davinci.h> #include <mach/serial.h> -#include <mach/common.h> +#include <linux/platform_data/mtd-davinci.h> +#include <linux/platform_data/mmc-davinci.h> +#include <linux/platform_data/usb-davinci.h> #include "davinci.h" @@ -377,11 +375,6 @@ static struct spi_board_info dm355_evm_spi_info[] __initconst = { static __init void dm355_evm_init(void) { struct clk *aemif; - int ret; - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); gpio_request(1, "dm9000"); gpio_direction_input(1); diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index 43bacbf..65a984c 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -19,16 +19,15 @@ #include <linux/clk.h> #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/usb-davinci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/common.h> +#include <linux/platform_data/i2c-davinci.h> #include <mach/serial.h> +#include <linux/platform_data/mtd-davinci.h> +#include <linux/platform_data/mmc-davinci.h> +#include <linux/platform_data/usb-davinci.h> #include "davinci.h" @@ -235,11 +234,6 @@ static struct spi_board_info dm355_leopard_spi_info[] __initconst = { static __init void dm355_leopard_init(void) { struct clk *aemif; - int ret; - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); gpio_request(9, "dm9000"); gpio_direction_input(9); diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index e08a868..4078ba9 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -18,7 +18,7 @@ #include <linux/i2c.h> #include <linux/io.h> #include <linux/clk.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/leds.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> @@ -743,12 +743,6 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = { static __init void dm365_evm_init(void) { - int ret; - - ret = dm365_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - evm_init_i2c(); davinci_serial_init(dm365_serial_device); diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 987605b7..40bb9b5 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -15,7 +15,7 @@ #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/i2c/pcf857x.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> @@ -754,14 +754,9 @@ static int davinci_phy_fixup(struct phy_device *phydev) static __init void davinci_evm_init(void) { - int ret; struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; - ret = dm644x_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - aemif_clk = clk_get(NULL, "aemif"); clk_prepare_enable(aemif_clk); diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 13d0801..2bc3651 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -22,7 +22,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/i2c/pcf857x.h> #include <media/tvp514x.h> @@ -33,19 +33,17 @@ #include <linux/mtd/partitions.h> #include <linux/clk.h> #include <linux/export.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/mtd-davinci-aemif.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/common.h> -#include <mach/irqs.h> #include <mach/serial.h> +#include <linux/platform_data/i2c-davinci.h> +#include <linux/platform_data/mtd-davinci.h> #include <mach/clock.h> #include <mach/cdce949.h> +#include <linux/platform_data/mtd-davinci-aemif.h> #include "davinci.h" #include "clock.h" @@ -788,13 +786,8 @@ static struct edma_rsv_info dm646x_edma_rsv[] = { static __init void evm_init(void) { - int ret; struct davinci_soc_info *soc_info = &davinci_soc_info; - ret = dm646x_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - evm_init_i2c(); davinci_serial_init(dm646x_serial_device); dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 7aa105b..cd0f587 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -15,7 +15,7 @@ #include <linux/mtd/partitions.h> #include <linux/regulator/machine.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/etherdevice.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index bb680af..46f336f 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -26,18 +26,17 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/mtd/partitions.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/i2c-davinci.h> -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <linux/platform_data/usb-davinci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/common.h> +#include <linux/platform_data/i2c-davinci.h> #include <mach/serial.h> #include <mach/mux.h> +#include <linux/platform_data/mtd-davinci.h> +#include <linux/platform_data/mmc-davinci.h> +#include <linux/platform_data/usb-davinci.h> #include "davinci.h" @@ -170,14 +169,9 @@ static struct davinci_mmc_config davinci_ntosd2_mmc_config = { static __init void davinci_ntosd2_init(void) { - int ret; struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; - ret = dm644x_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - aemif_clk = clk_get(NULL, "aemif"); clk_prepare_enable(aemif_clk); diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index 2aac51d..ab98c75 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -13,12 +13,10 @@ #include <linux/init.h> #include <linux/console.h> #include <linux/gpio.h> -#include <linux/platform_data/gpio-davinci.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/common.h> #include <mach/cp_intc.h> #include <mach/da8xx.h> #include <mach/mux.h> @@ -213,7 +211,7 @@ static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler) hawk_usb_ocic_handler = handler; error = request_irq(irq, omapl138_hawk_usb_ocic_irq, - IRQF_TRIGGER_RISING | + IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "OHCI over-current indicator", NULL); if (error) @@ -292,10 +290,6 @@ static __init void omapl138_hawk_init(void) { int ret; - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - davinci_serial_init(da8xx_serial_device); omapl138_hawk_config_emac(); diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 41c7c96..d843601 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -26,7 +26,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 0813b51..d6c746e 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -11,7 +11,6 @@ #include <linux/gpio.h> #include <linux/init.h> #include <linux/clk.h> -#include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> @@ -21,6 +20,7 @@ #include <mach/common.h> #include <mach/time.h> #include <mach/da8xx.h> +#include <mach/gpio-davinci.h> #include "clock.h" #include "mux.h" @@ -1151,16 +1151,6 @@ static struct davinci_id da830_ids[] = { }, }; -static struct davinci_gpio_platform_data da830_gpio_platform_data = { - .ngpio = 128, - .intc_irq_num = DA830_N_CP_INTC_IRQ, -}; - -int __init da830_register_gpio(void) -{ - return da8xx_register_gpio(&da830_gpio_platform_data); -} - static struct davinci_timer_instance da830_timer_instance[2] = { { .base = DA8XX_TIMER64P0_BASE, @@ -1206,6 +1196,10 @@ static struct davinci_soc_info davinci_soc_info_da830 = { .intc_irq_prios = da830_default_priorities, .intc_irq_num = DA830_N_CP_INTC_IRQ, .timer_info = &da830_timer_info, + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DA8XX_GPIO_BASE, + .gpio_num = 128, + .gpio_irq = IRQ_DA8XX_GPIO0, .emac_pdata = &da8xx_emac_pdata, }; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 352984e..f56e5fb 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -17,7 +17,6 @@ #include <linux/platform_device.h> #include <linux/cpufreq.h> #include <linux/regulator/consumer.h> -#include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> @@ -29,6 +28,7 @@ #include <mach/da8xx.h> #include <mach/cpufreq.h> #include <mach/pm.h> +#include <mach/gpio-davinci.h> #include "clock.h" #include "mux.h" @@ -1281,16 +1281,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config return platform_device_register(&da850_vpif_capture_dev); } -static struct davinci_gpio_platform_data da850_gpio_platform_data = { - .ngpio = 144, - .intc_irq_num = DA850_N_CP_INTC_IRQ, -}; - -int __init da850_register_gpio(void) -{ - return da8xx_register_gpio(&da850_gpio_platform_data); -} - static struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), @@ -1308,6 +1298,10 @@ static struct davinci_soc_info davinci_soc_info_da850 = { .intc_irq_prios = da850_default_priorities, .intc_irq_num = DA850_N_CP_INTC_IRQ, .timer_info = &da850_timer_info, + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DA8XX_GPIO_BASE, + .gpio_num = 144, + .gpio_irq = IRQ_DA8XX_GPIO0, .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 2eebc43..2ab5d57 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -53,9 +53,6 @@ extern void __iomem *davinci_sysmod_base; #define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x)) void davinci_map_sysmod(void); -#define DAVINCI_GPIO_BASE 0x01C67000 -int davinci_gpio_register(struct resource *res, int size, void *pdata); - /* DM355 base addresses */ #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000 #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 @@ -85,7 +82,6 @@ void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); int dm355_init_video(struct vpfe_config *, struct vpbe_config *); -int dm355_gpio_register(void); /* DM365 function declarations */ void dm365_init(void); @@ -96,13 +92,11 @@ void dm365_init_rtc(void); void dm365_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); int dm365_init_video(struct vpfe_config *, struct vpbe_config *); -int dm365_gpio_register(void); /* DM644x function declarations */ void dm644x_init(void); void dm644x_init_asp(struct snd_platform_data *pdata); int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); -int dm644x_gpio_register(void); /* DM646x function declarations */ void dm646x_init(void); @@ -112,7 +106,6 @@ int dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); void dm646x_setup_vpif(struct vpif_display_config *, struct vpif_capture_config *); -int dm646x_gpio_register(void); extern struct platform_device dm365_serial_device[]; extern struct platform_device dm355_serial_device[]; diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index c46eccb..2e473fe 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -665,32 +665,6 @@ int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata) return platform_device_register(&da8xx_lcdc_device); } -static struct resource da8xx_gpio_resources[] = { - { /* registers */ - .start = DA8XX_GPIO_BASE, - .end = DA8XX_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = IRQ_DA8XX_GPIO0, - .end = IRQ_DA8XX_GPIO8, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da8xx_gpio_device = { - .name = "davinci_gpio", - .id = -1, - .num_resources = ARRAY_SIZE(da8xx_gpio_resources), - .resource = da8xx_gpio_resources, -}; - -int __init da8xx_register_gpio(void *pdata) -{ - da8xx_gpio_device.dev.platform_data = pdata; - return platform_device_register(&da8xx_gpio_device); -} - static struct resource da8xx_mmcsd0_resources[] = { { /* registers */ .start = DA8XX_MMCSD0_BASE, diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 3996e98..111573c 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -318,19 +318,6 @@ static void davinci_init_wdt(void) platform_device_register(&davinci_wdt_device); } -static struct platform_device davinci_gpio_device = { - .name = "davinci_gpio", - .id = -1, -}; - -int davinci_gpio_register(struct resource *res, int size, void *pdata) -{ - davinci_gpio_device.resource = res; - davinci_gpio_device.num_resources = size; - davinci_gpio_device.dev.platform_data = pdata; - return platform_device_register(&davinci_gpio_device); -} - /*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/ diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index ef9ff1f..3eaa5f6 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -13,10 +13,8 @@ #include <linux/serial_8250.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> + #include <linux/spi/spi.h> -#include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/spi-davinci.h> #include <asm/mach/map.h> @@ -27,6 +25,9 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <linux/platform_data/spi-davinci.h> +#include <mach/gpio-davinci.h> +#include <linux/platform_data/edma.h> #include "davinci.h" #include "clock.h" @@ -885,30 +886,6 @@ static struct platform_device dm355_vpbe_dev = { }, }; -static struct resource dm355_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = IRQ_DM355_GPIOBNK0, - .end = IRQ_DM355_GPIOBNK6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm355_gpio_platform_data = { - .ngpio = 104, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, -}; - -int __init dm355_gpio_register(void) -{ - return davinci_gpio_register(dm355_gpio_resources, - sizeof(dm355_gpio_resources), - &dm355_gpio_platform_data); -} /*----------------------------------------------------------------------*/ static struct map_desc dm355_io_desc[] = { @@ -1028,6 +1005,10 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .intc_irq_prios = dm355_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm355_timer_info, + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, + .gpio_num = 104, + .gpio_irq = IRQ_DM355_GPIOBNK0, .sram_dma = 0x00010000, .sram_len = SZ_32K, }; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 1511a06..c29e324 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -19,9 +19,6 @@ #include <linux/dma-mapping.h> #include <linux/spi/spi.h> #include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> -#include <linux/platform_data/keyscan-davinci.h> -#include <linux/platform_data/spi-davinci.h> #include <asm/mach/map.h> @@ -32,6 +29,9 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <linux/platform_data/keyscan-davinci.h> +#include <linux/platform_data/spi-davinci.h> +#include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" @@ -698,32 +698,6 @@ void __init dm365_init_spi0(unsigned chipselect_mask, platform_device_register(&dm365_spi0_device); } -static struct resource dm365_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = IRQ_DM365_GPIO0, - .end = IRQ_DM365_GPIO7, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm365_gpio_platform_data = { - .ngpio = 104, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, - .gpio_unbanked = 8, -}; - -int __init dm365_gpio_register(void) -{ - return davinci_gpio_register(dm365_gpio_resources, - sizeof(dm365_gpio_resources), - &dm365_gpio_platform_data); -} - static struct emac_platform_data dm365_emac_pdata = { .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, @@ -1131,6 +1105,11 @@ static struct davinci_soc_info davinci_soc_info_dm365 = { .intc_irq_prios = dm365_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm365_timer_info, + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, + .gpio_num = 104, + .gpio_irq = IRQ_DM365_GPIO0, + .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ .emac_pdata = &dm365_emac_pdata, .sram_dma = 0x00010000, .sram_len = SZ_32K, diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 143a321..4f74682 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -13,7 +13,6 @@ #include <linux/serial_8250.h> #include <linux/platform_device.h> #include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> @@ -24,6 +23,7 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" @@ -771,30 +771,6 @@ static struct platform_device dm644x_vpbe_dev = { }, }; -static struct resource dm644_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = IRQ_GPIOBNK0, - .end = IRQ_GPIOBNK4, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm644_gpio_platform_data = { - .ngpio = 71, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, -}; - -int __init dm644x_gpio_register(void) -{ - return davinci_gpio_register(dm644_gpio_resources, - sizeof(dm644_gpio_resources), - &dm644_gpio_platform_data); -} /*----------------------------------------------------------------------*/ static struct map_desc dm644x_io_desc[] = { @@ -921,6 +897,10 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .intc_irq_prios = dm644x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm644x_timer_info, + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, + .gpio_num = 71, + .gpio_irq = IRQ_GPIOBNK0, .emac_pdata = &dm644x_emac_pdata, .sram_dma = 0x00008000, .sram_len = SZ_16K, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 2a73f29..68f8d1f 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -14,7 +14,6 @@ #include <linux/serial_8250.h> #include <linux/platform_device.h> #include <linux/platform_data/edma.h> -#include <linux/platform_data/gpio-davinci.h> #include <asm/mach/map.h> @@ -25,6 +24,7 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/gpio-davinci.h> #include "davinci.h" #include "clock.h" @@ -748,30 +748,6 @@ static struct platform_device vpif_capture_dev = { .num_resources = ARRAY_SIZE(vpif_capture_resource), }; -static struct resource dm646x_gpio_resources[] = { - { /* registers */ - .start = DAVINCI_GPIO_BASE, - .end = DAVINCI_GPIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* interrupt */ - .start = IRQ_DM646X_GPIOBNK0, - .end = IRQ_DM646X_GPIOBNK2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct davinci_gpio_platform_data dm646x_gpio_platform_data = { - .ngpio = 43, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, -}; - -int __init dm646x_gpio_register(void) -{ - return davinci_gpio_register(dm646x_gpio_resources, - sizeof(dm646x_gpio_resources), - &dm646x_gpio_platform_data); -} /*----------------------------------------------------------------------*/ static struct map_desc dm646x_io_desc[] = { @@ -898,6 +874,10 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { .intc_irq_prios = dm646x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm646x_timer_info, + .gpio_type = GPIO_TYPE_DAVINCI, + .gpio_base = DAVINCI_GPIO_BASE, + .gpio_num = 43, /* Only 33 usable */ + .gpio_irq = IRQ_DM646X_GPIOBNK0, .emac_pdata = &dm646x_emac_pdata, .sram_dma = 0x10010000, .sram_len = SZ_32K, diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 39e58b4..aae5307 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -97,7 +97,6 @@ int da8xx_register_mmcsd0(struct davinci_mmc_config *config); int da850_register_mmcsd1(struct davinci_mmc_config *config); void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); -int da8xx_register_gpio(void *pdata); int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); void __iomem *da8xx_get_mem_ctlr(void); @@ -111,8 +110,6 @@ int da850_register_vpif_capture void da8xx_restart(enum reboot_mode mode, const char *cmd); void da8xx_rproc_reserve_cma(void); int da8xx_register_rproc(void); -int da850_register_gpio(void); -int da830_register_gpio(void); extern struct platform_device da8xx_serial_device[]; extern struct emac_platform_data da8xx_emac_pdata; diff --git a/arch/arm/mach-davinci/include/mach/gpio-davinci.h b/arch/arm/mach-davinci/include/mach/gpio-davinci.h new file mode 100644 index 0000000..1fdd1fd --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/gpio-davinci.h @@ -0,0 +1,91 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DAVINCI_DAVINCI_GPIO_H +#define __DAVINCI_DAVINCI_GPIO_H + +#include <linux/io.h> +#include <linux/spinlock.h> + +#include <asm-generic/gpio.h> + +#include <mach/irqs.h> +#include <mach/common.h> + +#define DAVINCI_GPIO_BASE 0x01C67000 + +enum davinci_gpio_type { + GPIO_TYPE_DAVINCI = 0, + GPIO_TYPE_TNETV107X, +}; + +/* + * basic gpio routines + * + * board-specific init should be done by arch/.../.../board-XXX.c (maybe + * initializing banks together) rather than boot loaders; kexec() won't + * go through boot loaders. + * + * the gpio clock will be turned on when gpios are used, and you may also + * need to pay attention to PINMUX registers to be sure those pins are + * used as gpios, not with other peripherals. + * + * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, + * and maybe for later updates, code may write GPIO(N). These may be + * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip + * may not support all the GPIOs in that range. + * + * GPIOs can also be on external chips, numbered after the ones built-in + * to the DaVinci chip. For now, they won't be usable as IRQ sources. + */ +#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ + +/* Convert GPIO signal to GPIO pin number */ +#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) + +struct davinci_gpio_controller { + struct gpio_chip chip; + int irq_base; + spinlock_t lock; + void __iomem *regs; + void __iomem *set_data; + void __iomem *clr_data; + void __iomem *in_data; +}; + +/* The __gpio_to_controller() and __gpio_mask() functions inline to constants + * with constant parameters; or in outlined code they execute at runtime. + * + * You'd access the controller directly when reading or writing more than + * one gpio value at a time, and to support wired logic where the value + * being driven by the cpu need not match the value read back. + * + * These are NOT part of the cross-platform GPIO interface + */ +static inline struct davinci_gpio_controller * +__gpio_to_controller(unsigned gpio) +{ + struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs; + int index = gpio / 32; + + if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num) + return NULL; + + return ctlrs + index; +} + +static inline u32 __gpio_mask(unsigned gpio) +{ + return 1 << (gpio % 32); +} + +#endif /* __DAVINCI_DAVINCI_GPIO_H */ diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h new file mode 100644 index 0000000..960e9de --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -0,0 +1,88 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DAVINCI_GPIO_H +#define __DAVINCI_GPIO_H + +#include <asm-generic/gpio.h> + +#define __ARM_GPIOLIB_COMPLEX + +/* The inline versions use the static inlines in the driver header */ +#include "gpio-davinci.h" + +/* + * The get/set/clear functions will inline when called with constant + * parameters referencing built-in GPIOs, for low-overhead bitbanging. + * + * gpio_set_value() will inline only on traditional Davinci style controllers + * with distinct set/clear registers. + * + * Otherwise, calls with variable parameters or referencing external + * GPIOs (e.g. on GPIO expander chips) use outlined functions. + */ +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (__builtin_constant_p(value) && gpio < davinci_soc_info.gpio_num) { + struct davinci_gpio_controller *ctlr; + u32 mask; + + ctlr = __gpio_to_controller(gpio); + + if (ctlr->set_data != ctlr->clr_data) { + mask = __gpio_mask(gpio); + if (value) + __raw_writel(mask, ctlr->set_data); + else + __raw_writel(mask, ctlr->clr_data); + return; + } + } + + __gpio_set_value(gpio, value); +} + +/* Returns zero or nonzero; works for gpios configured as inputs OR + * as outputs, at least for built-in GPIOs. + * + * NOTE: for built-in GPIOs, changes in reported values are synchronized + * to the GPIO clock. This is easily seen after calling gpio_set_value() + * and then immediately gpio_get_value(), where the gpio_get_value() will + * return the old value until the GPIO clock ticks and the new value gets + * latched. + */ +static inline int gpio_get_value(unsigned gpio) +{ + struct davinci_gpio_controller *ctlr; + + if (!__builtin_constant_p(gpio) || gpio >= davinci_soc_info.gpio_num) + return __gpio_get_value(gpio); + + ctlr = __gpio_to_controller(gpio); + return __gpio_mask(gpio) & __raw_readl(ctlr->in_data); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + if (__builtin_constant_p(gpio) && gpio < davinci_soc_info.gpio_num) + return 0; + else + return __gpio_cansleep(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + /* don't support the reverse mapping */ + return -ENOSYS; +} + +#endif /* __DAVINCI_GPIO_H */ diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c index 8540ddd..f18928b 100644 --- a/arch/arm/mach-davinci/sram.c +++ b/arch/arm/mach-davinci/sram.c @@ -25,6 +25,7 @@ struct gen_pool *sram_get_gen_pool(void) void *sram_alloc(size_t len, dma_addr_t *dma) { + unsigned long vaddr; dma_addr_t dma_base = davinci_soc_info.sram_dma; if (dma) @@ -32,7 +33,13 @@ void *sram_alloc(size_t len, dma_addr_t *dma) if (!sram_pool || (dma && !dma_base)) return NULL; - return gen_pool_dma_alloc(sram_pool, len, dma); + vaddr = gen_pool_alloc(sram_pool, len); + if (!vaddr) + return NULL; + + if (dma) + *dma = gen_pool_virt_to_phys(sram_pool, vaddr); + return (void *)vaddr; } EXPORT_SYMBOL(sram_alloc); diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 56c6eb5..7a55b5c 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -181,7 +181,7 @@ static struct timer_s timers[] = { .name = "clockevent", .opts = TIMER_OPTS_DISABLED, .irqaction = { - .flags = IRQF_TIMER, + .flags = IRQF_DISABLED | IRQF_TIMER, .handler = timer_interrupt, } }, @@ -190,7 +190,7 @@ static struct timer_s timers[] = { .period = ~0, .opts = TIMER_OPTS_PERIODIC, .irqaction = { - .flags = IRQF_TIMER, + .flags = IRQF_DISABLED | IRQF_TIMER, .handler = freerun_interrupt, } }, @@ -331,6 +331,7 @@ static void davinci_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_davinci = { .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, .set_next_event = davinci_set_next_event, .set_mode = davinci_set_mode, }; @@ -396,10 +397,14 @@ void __init davinci_timer_init(void) /* setup clockevent */ clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; + clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, + clockevent_davinci.shift); + clockevent_davinci.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_davinci); + clockevent_davinci.min_delta_ns = 50000; /* 50 usec */ clockevent_davinci.cpumask = cpumask_of(0); - clockevents_config_and_register(&clockevent_davinci, - davinci_clock_tick_rate, 1, 0xfffffffe); + clockevents_register_device(&clockevent_davinci); for (i=0; i< ARRAY_SIZE(timers); i++) timer32_config(&timers[i]); diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index 49fa9ab..49f72a8 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -10,15 +10,54 @@ #include <linux/init.h> #include <linux/clk-provider.h> +#include <linux/clocksource.h> +#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/platform_data/usb-ehci-orion.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> #include <mach/dove.h> #include <mach/pm.h> #include <plat/common.h> +#include <plat/irq.h> #include "common.h" +/* + * There are still devices that doesn't even know about DT, + * get clock gates here and add a clock lookup. + */ +static void __init dove_legacy_clk_init(void) +{ + struct device_node *np = of_find_compatible_node(NULL, NULL, + "marvell,dove-gating-clock"); + struct of_phandle_args clkspec; + + clkspec.np = np; + clkspec.args_count = 1; + + clkspec.args[0] = CLOCK_GATING_BIT_PCIE0; + orion_clkdev_add("0", "pcie", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_PCIE1; + orion_clkdev_add("1", "pcie", + of_clk_get_from_provider(&clkspec)); +} + +static void __init dove_dt_time_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + +static void __init dove_dt_init_early(void) +{ + mvebu_mbus_init("marvell,dove-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); +} + static void __init dove_dt_init(void) { pr_info("Dove 88AP510 SoC\n"); @@ -26,7 +65,14 @@ static void __init dove_dt_init(void) #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif - BUG_ON(mvebu_mbus_dt_init()); + dove_setup_cpu_wins(); + + /* Setup clocks for legacy devices */ + dove_legacy_clk_init(); + + /* Internal devices not ported to DT yet */ + dove_pcie_init(1, 1); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -37,6 +83,8 @@ static const char * const dove_dt_board_compat[] = { DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") .map_io = dove_map_io, + .init_early = dove_dt_init_early, + .init_time = dove_dt_time_init, .init_machine = dove_dt_init, .restart = dove_restart, .dt_compat = dove_dt_board_compat, diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 39ef3b6..c95dbce 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -212,7 +212,7 @@ static struct clk_lookup clocks[] = { INIT_CK(NULL, "hclk", &clk_h), INIT_CK(NULL, "apb_pclk", &clk_p), INIT_CK(NULL, "pll2", &clk_pll2), - INIT_CK("ohci-platform", NULL, &clk_usb_host), + INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), INIT_CK("ep93xx-keypad", NULL, &clk_keypad), INIT_CK("ep93xx-fb", NULL, &clk_video), INIT_CK("ep93xx-spi.0", NULL, &clk_spi), diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index d95ee28a..3f12b88 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -36,7 +36,6 @@ #include <linux/export.h> #include <linux/irqchip/arm-vic.h> #include <linux/reboot.h> -#include <linux/usb/ohci_pdriver.h> #include <mach/hardware.h> #include <linux/platform_data/video-ep93xx.h> @@ -298,53 +297,25 @@ static struct platform_device ep93xx_rtc_device = { .resource = ep93xx_rtc_resource, }; -/************************************************************************* - * EP93xx OHCI USB Host - *************************************************************************/ - -static struct clk *ep93xx_ohci_host_clock; - -static int ep93xx_ohci_power_on(struct platform_device *pdev) -{ - if (!ep93xx_ohci_host_clock) { - ep93xx_ohci_host_clock = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(ep93xx_ohci_host_clock)) - return PTR_ERR(ep93xx_ohci_host_clock); - } - - return clk_enable(ep93xx_ohci_host_clock); -} - -static void ep93xx_ohci_power_off(struct platform_device *pdev) -{ - clk_disable(ep93xx_ohci_host_clock); -} - -static struct usb_ohci_pdata ep93xx_ohci_pdata = { - .power_on = ep93xx_ohci_power_on, - .power_off = ep93xx_ohci_power_off, - .power_suspend = ep93xx_ohci_power_off, -}; static struct resource ep93xx_ohci_resources[] = { DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), DEFINE_RES_IRQ(IRQ_EP93XX_USB), }; -static u64 ep93xx_ohci_dma_mask = DMA_BIT_MASK(32); static struct platform_device ep93xx_ohci_device = { - .name = "ohci-platform", + .name = "ep93xx-ohci", .id = -1, - .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), - .resource = ep93xx_ohci_resources, .dev = { - .dma_mask = &ep93xx_ohci_dma_mask, + .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &ep93xx_ohci_pdata, }, + .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), + .resource = ep93xx_ohci_resources, }; + /************************************************************************* * EP93xx physmap'ed flash *************************************************************************/ diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f9d67a0..56fe819 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -14,28 +14,19 @@ menu "SAMSUNG EXYNOS SoCs Support" config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y - select ARM_AMBA - select CLKSRC_OF - select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 - select CPU_EXYNOS4210 select GIC_NON_BANKED - select KEYBOARD_SAMSUNG if INPUT_KEYBOARD select HAVE_ARM_SCU if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL - select S5P_DEV_MFC help Samsung EXYNOS4 SoCs based systems config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" - select ARM_AMBA - select CLKSRC_OF select HAVE_ARM_SCU if SMP select HAVE_SMP select PINCTRL - select USB_ARCH_HAS_XHCI help Samsung EXYNOS5 (Cortex-A15) SoC based systems @@ -119,6 +110,35 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +comment "Flattened Device Tree based board for EXYNOS SoCs" + +config MACH_EXYNOS4_DT + bool "Samsung Exynos4 Machine using device tree" + default y + depends on ARCH_EXYNOS4 + select ARM_AMBA + select CLKSRC_OF + select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 + select CPU_EXYNOS4210 + select KEYBOARD_SAMSUNG if INPUT_KEYBOARD + select S5P_DEV_MFC + help + Machine support for Samsung Exynos4 machine with device tree enabled. + Select this if a fdt blob is available for the Exynos4 SoC based board. + Note: This is under development and not all peripherals can be supported + with this machine file. + +config MACH_EXYNOS5_DT + bool "SAMSUNG EXYNOS5 Machine using device tree" + default y + depends on ARCH_EXYNOS5 + select ARM_AMBA + select CLKSRC_OF + select USB_ARCH_HAS_XHCI + help + Machine support for Samsung EXYNOS5 machine with device tree enabled. + Select this if a fdt blob is available for the EXYNOS5 SoC based board. + endmenu endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 8930b66..5369615 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -32,5 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) # machine support -obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o -obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o +obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o +obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 61d2906..ba95e5d 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -26,9 +26,10 @@ #include <linux/export.h> #include <linux/irqdomain.h> #include <linux/of_address.h> +#include <linux/clocksource.h> +#include <linux/clk-provider.h> #include <linux/irqchip/arm-gic.h> #include <linux/irqchip/chained_irq.h> -#include <linux/platform_device.h> #include <asm/proc-fns.h> #include <asm/exception.h> @@ -293,16 +294,6 @@ void exynos5_restart(enum reboot_mode mode, const char *cmd) __raw_writel(val, addr); } -static struct platform_device exynos_cpuidle = { - .name = "exynos_cpuidle", - .id = -1, -}; - -void __init exynos_cpuidle_init(void) -{ - platform_device_register(&exynos_cpuidle); -} - void __init exynos_init_late(void) { if (of_machine_is_compatible("samsung,exynos5440")) @@ -376,6 +367,12 @@ static void __init exynos5_map_io(void) iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); } +void __init exynos_init_time(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + struct bus_type exynos_subsys = { .name = "exynos-core", .dev_name = "exynos-core", diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ff9b6a9..8646a14 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -16,12 +16,12 @@ #include <linux/of.h> void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); +void exynos_init_time(void); struct map_desc; void exynos_init_io(void); void exynos4_restart(enum reboot_mode mode, const char *cmd); void exynos5_restart(enum reboot_mode mode, const char *cmd); -void exynos_cpuidle_init(void); void exynos_init_late(void); void exynos_firmware_init(void); diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ddbfe87..ac139226 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -15,7 +15,6 @@ #include <linux/io.h> #include <linux/export.h> #include <linux/time.h> -#include <linux/platform_device.h> #include <asm/proc-fns.h> #include <asm/smp_scu.h> @@ -193,7 +192,7 @@ static void __init exynos5_core_down_clk(void) __raw_writel(tmp, EXYNOS5_PWR_CTRL2); } -static int exynos_cpuidle_probe(struct platform_device *pdev) +static int __init exynos4_init_cpuidle(void) { int cpu_id, ret; struct cpuidle_device *device; @@ -206,7 +205,7 @@ static int exynos_cpuidle_probe(struct platform_device *pdev) ret = cpuidle_register_driver(&exynos4_idle_driver); if (ret) { - dev_err(&pdev->dev, "failed to register cpuidle driver\n"); + printk(KERN_ERR "CPUidle failed to register driver\n"); return ret; } @@ -220,20 +219,11 @@ static int exynos_cpuidle_probe(struct platform_device *pdev) ret = cpuidle_register_device(device); if (ret) { - dev_err(&pdev->dev, "failed to register cpuidle device\n"); + printk(KERN_ERR "CPUidle register device failed\n"); return ret; } } return 0; } - -static struct platform_driver exynos_cpuidle_driver = { - .probe = exynos_cpuidle_probe, - .driver = { - .name = "exynos_cpuidle", - .owner = THIS_MODULE, - }, -}; - -module_platform_driver(exynos_cpuidle_driver); +device_initcall(exynos4_init_cpuidle); diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 2cdb63e..57344b7 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -44,6 +44,11 @@ #define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) #define S5P_DAC_PHY_ENABLE (1 << 0) +#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) +#define S5P_MIPI_DPHY_ENABLE (1 << 0) +#define S5P_MIPI_DPHY_SRESETN (1 << 1) +#define S5P_MIPI_DPHY_MRESETN (1 << 2) + #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) #define S5P_INFORM2 S5P_PMUREG(0x0808) diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index 4603e6b..0099c6c 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -11,8 +11,12 @@ * published by the Free Software Foundation. */ +#include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/of_fdt.h> +#include <linux/serial_core.h> +#include <linux/memblock.h> +#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <plat/mfc.h> @@ -21,8 +25,6 @@ static void __init exynos4_dt_machine_init(void) { - exynos_cpuidle_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -52,6 +54,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .init_early = exynos_firmware_init, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, + .init_time = exynos_init_time, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart, .reserve = exynos4_reserve, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 1fe075a..f874b77 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -11,10 +11,14 @@ #include <linux/of_platform.h> #include <linux/of_fdt.h> +#include <linux/memblock.h> #include <linux/io.h> +#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <mach/regs-pmu.h> + +#include <plat/cpu.h> #include <plat/mfc.h> #include "common.h" @@ -43,8 +47,6 @@ static void __init exynos5_dt_machine_init(void) } } - exynos_cpuidle_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -74,6 +76,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .map_io = exynos_init_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, + .init_time = exynos_init_time, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index e009168..2739ca2 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/spinlock.h> -#include <video/vga.h> #include <asm/pgtable.h> #include <asm/page.h> @@ -197,8 +196,6 @@ void __init footbridge_map_io(void) iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); } - - vga_base = PCIMEM_BASE; } void footbridge_restart(enum reboot_mode mode, const char *cmd) diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 7c2fdae..3490a24 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -18,6 +18,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/spinlock.h> +#include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> @@ -290,6 +291,7 @@ void __init dc21285_preinit(void) int cfn_mode; pcibios_min_mem = 0x81000000; + vga_base = PCIMEM_BASE; mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c index 1a7235f..b082435 100644 --- a/arch/arm/mach-footbridge/ebsa285.c +++ b/arch/arm/mach-footbridge/ebsa285.c @@ -30,24 +30,21 @@ static const struct { const char *name; const char *trigger; } ebsa285_leds[] = { - { "ebsa285:amber", "cpu0", }, - { "ebsa285:green", "heartbeat", }, + { "ebsa285:amber", "heartbeat", }, + { "ebsa285:green", "cpu0", }, { "ebsa285:red",}, }; -static unsigned char hw_led_state; - static void ebsa285_led_set(struct led_classdev *cdev, enum led_brightness b) { struct ebsa285_led *led = container_of(cdev, struct ebsa285_led, cdev); - if (b == LED_OFF) - hw_led_state |= led->mask; + if (b != LED_OFF) + *XBUS_LEDS |= led->mask; else - hw_led_state &= ~led->mask; - *XBUS_LEDS = hw_led_state; + *XBUS_LEDS &= ~led->mask; } static enum led_brightness ebsa285_led_get(struct led_classdev *cdev) @@ -55,19 +52,18 @@ static enum led_brightness ebsa285_led_get(struct led_classdev *cdev) struct ebsa285_led *led = container_of(cdev, struct ebsa285_led, cdev); - return hw_led_state & led->mask ? LED_OFF : LED_FULL; + return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF; } static int __init ebsa285_leds_init(void) { int i; - if (!machine_is_ebsa285()) + if (machine_is_ebsa285()) return -ENODEV; - /* 3 LEDS all off */ - hw_led_state = XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED; - *XBUS_LEDS = hw_led_state; + /* 3 LEDS All ON */ + *XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED; for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) { struct ebsa285_led *led; diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c index eb1fa5c..1fd2cf0 100644 --- a/arch/arm/mach-footbridge/netwinder-hw.c +++ b/arch/arm/mach-footbridge/netwinder-hw.c @@ -692,14 +692,14 @@ static void netwinder_led_set(struct led_classdev *cdev, unsigned long flags; u32 reg; - raw_spin_lock_irqsave(&nw_gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); reg = nw_gpio_read(); if (b != LED_OFF) reg &= ~led->mask; else reg |= led->mask; nw_gpio_modify_op(led->mask, reg); - raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static enum led_brightness netwinder_led_get(struct led_classdev *cdev) @@ -709,9 +709,9 @@ static enum led_brightness netwinder_led_get(struct led_classdev *cdev) unsigned long flags; u32 reg; - raw_spin_lock_irqsave(&nw_gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); reg = nw_gpio_read(); - raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); + spin_unlock_irqrestore(&nw_gpio_lock, flags); return (reg & led->mask) ? LED_OFF : LED_FULL; } diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index f8cb571..70bfa57 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -21,9 +21,9 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/gpio.h> #define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x)) -#define irq_to_gpio(x) ((x) - GPIO_IRQ_BASE) /* GPIO registers definition */ #define GPIO_DATA_OUT 0x0 diff --git a/arch/arm/mach-gemini/include/mach/gpio.h b/arch/arm/mach-gemini/include/mach/gpio.h new file mode 100644 index 0000000..40a0527 --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/gpio.h @@ -0,0 +1,20 @@ +/* + * Gemini gpiolib specific defines + * + * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __MACH_GPIO_H__ +#define __MACH_GPIO_H__ + +#include <mach/irqs.h> + +#define gpio_to_irq(x) ((x) + GPIO_IRQ_BASE) +#define irq_to_gpio(x) ((x) - GPIO_IRQ_BASE) + +#endif /* __MACH_GPIO_H__ */ diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c index 0a63c4d..21dc5a8 100644 --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -13,8 +13,6 @@ #include <mach/hardware.h> #include <mach/global_reg.h> #include <asm/mach/time.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> /* * Register definitions for the timers @@ -35,89 +33,19 @@ #define TIMER_3_CR_CLOCK (1 << 7) #define TIMER_3_CR_INT (1 << 8) -static unsigned int tick_rate; - -static int gemini_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - u32 cr; - - cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - - /* This may be overdoing it, feel free to test without this */ - cr &= ~TIMER_2_CR_ENABLE; - cr &= ~TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - - /* Set next event */ - writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); - writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); - cr |= TIMER_2_CR_ENABLE; - cr |= TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - - return 0; -} - -static void gemini_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); - u32 cr; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - /* Start the timer */ - writel(period, - TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); - writel(period, - TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); - cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - cr |= TIMER_2_CR_ENABLE; - cr |= TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - /* - * Disable also for oneshot: the set_next() call will - * arm the timer instead. - */ - cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - cr &= ~TIMER_2_CR_ENABLE; - cr &= ~TIMER_2_CR_INT; - writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - break; - default: - break; - } -} - -/* Use TIMER2 as clock event */ -static struct clock_event_device gemini_clockevent = { - .name = "TIMER2", - .rating = 300, /* Reasonably fast and accurate clock event */ - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = gemini_timer_set_next_event, - .set_mode = gemini_timer_set_mode, -}; - /* * IRQ handler for the timer */ static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &gemini_clockevent; + timer_tick(); - evt->event_handler(evt); return IRQ_HANDLED; } static struct irqaction gemini_timer_irq = { .name = "Gemini Timer Tick", - .flags = IRQF_TIMER, + .flags = IRQF_DISABLED | IRQF_TIMER, .handler = gemini_timer_interrupt, }; @@ -126,9 +54,9 @@ static struct irqaction gemini_timer_irq = { */ void __init gemini_timer_init(void) { - u32 reg_v; + unsigned int tick_rate, reg_v; - reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); + reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000; printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000); @@ -154,17 +82,8 @@ void __init gemini_timer_init(void) * Make irqs happen for the system timer */ setup_irq(IRQ_TIMER2, &gemini_timer_irq); - - /* Enable and use TIMER1 as clock source */ - writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); - writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); - writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), - "TIMER1", tick_rate, 300, 32, - clocksource_mmio_readl_up)) - pr_err("timer: failed to initialize gemini clock source\n"); - - /* Configure and register the clockevent */ - clockevents_config_and_register(&gemini_clockevent, tick_rate, - 1, 0xffffffff); + /* Start the timer */ + __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); + __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); + __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); } diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 0aded64..8e8437d 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -4,16 +4,15 @@ config ARCH_HIGHBANK select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_OPP - select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA - select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_764369 select ARM_ERRATA_775420 - select ARM_ERRATA_798181 if SMP + select ARM_ERRATA_798181 select ARM_GIC - select ARM_PSCI select ARM_TIMER_SP804 select CACHE_L2X0 + select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile index 55840f4..8a1ef57 100644 --- a/arch/arm/mach-highbank/Makefile +++ b/arch/arm/mach-highbank/Makefile @@ -3,4 +3,6 @@ obj-y := highbank.o system.o smc.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) +obj-$(CONFIG_SMP) += platsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_PM_SLEEP) += pm.o diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h index 7ec5edc..aea1ec5 100644 --- a/arch/arm/mach-highbank/core.h +++ b/arch/arm/mach-highbank/core.h @@ -3,6 +3,7 @@ #include <linux/reboot.h> +extern void highbank_set_cpu_jump(int cpu, void *jump_addr); extern void highbank_restart(enum reboot_mode, const char *); extern void __iomem *scu_base_addr; @@ -13,5 +14,8 @@ static inline void highbank_pm_init(void) {} #endif extern void highbank_smc1(int fn, int arg); +extern void highbank_cpu_die(unsigned int cpu); + +extern struct smp_operations highbank_smp_ops; #endif diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index b3d7e56..8e63ccd 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -24,9 +24,11 @@ #include <linux/of_platform.h> #include <linux/of_address.h> #include <linux/amba/bus.h> -#include <linux/platform_device.h> +#include <linux/clk-provider.h> -#include <asm/psci.h> +#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <asm/smp_plat.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -47,6 +49,17 @@ static void __init highbank_scu_map_io(void) scu_base_addr = ioremap(base, SZ_4K); } +#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu))) +#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu)) + +void highbank_set_cpu_jump(int cpu, void *jump_addr) +{ + cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); + writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); + __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); + outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), + HB_JUMP_TABLE_PHYS(cpu) + 15); +} static void highbank_l2x0_disable(void) { @@ -70,6 +83,20 @@ static void __init highbank_init_irq(void) } } +static void __init highbank_timer_init(void) +{ + struct device_node *np; + + /* Map system registers */ + np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); + sregs_base = of_iomap(np, 0); + WARN_ON(!sregs_base); + + of_clk_init(NULL); + + clocksource_of_init(); +} + static void highbank_power_off(void) { highbank_set_pwr_shutdown(); @@ -126,19 +153,8 @@ static struct notifier_block highbank_platform_nb = { .notifier_call = highbank_platform_notifier, }; -static struct platform_device highbank_cpuidle_device = { - .name = "cpuidle-calxeda", -}; - static void __init highbank_init(void) { - struct device_node *np; - - /* Map system registers */ - np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); - sregs_base = of_iomap(np, 0); - WARN_ON(!sregs_base); - pm_power_off = highbank_power_off; highbank_pm_init(); @@ -146,9 +162,6 @@ static void __init highbank_init(void) bus_register_notifier(&amba_bustype, &highbank_amba_nb); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - if (psci_ops.cpu_suspend) - platform_device_register(&highbank_cpuidle_device); } static const char *highbank_match[] __initconst = { @@ -161,7 +174,9 @@ DT_MACHINE_START(HIGHBANK, "Highbank") #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) .dma_zone_size = (4ULL * SZ_1G), #endif + .smp = smp_ops(highbank_smp_ops), .init_irq = highbank_init_irq, + .init_time = highbank_timer_init, .init_machine = highbank_init, .dt_compat = highbank_match, .restart = highbank_restart, diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c new file mode 100644 index 0000000..a019e4e --- /dev/null +++ b/arch/arm/mach-highbank/hotplug.c @@ -0,0 +1,37 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/kernel.h> +#include <asm/cacheflush.h> + +#include "core.h" +#include "sysregs.h" + +extern void secondary_startup(void); + +/* + * platform-specific code to shutdown a CPU + * + */ +void __ref highbank_cpu_die(unsigned int cpu) +{ + highbank_set_cpu_jump(cpu, phys_to_virt(0)); + + flush_cache_louis(); + highbank_set_core_pwr(); + + while (1) + cpu_do_idle(); +} diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c new file mode 100644 index 0000000..32d75cf5 --- /dev/null +++ b/arch/arm/mach-highbank/platsmp.c @@ -0,0 +1,68 @@ +/* + * Copyright 2010-2011 Calxeda, Inc. + * Based on platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/smp_scu.h> + +#include "core.h" + +extern void secondary_startup(void); + +static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + highbank_set_cpu_jump(cpu, secondary_startup); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +static void __init highbank_smp_init_cpus(void) +{ + unsigned int i, ncores = 4; + + /* sanity check */ + if (ncores > NR_CPUS) { + printk(KERN_WARNING + "highbank: no. of cores (%d) greater than configured " + "maximum of %d - clipping\n", + ncores, NR_CPUS); + ncores = NR_CPUS; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} + +static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) +{ + if (scu_base_addr) + scu_enable(scu_base_addr); +} + +struct smp_operations highbank_smp_ops __initdata = { + .smp_init_cpus = highbank_smp_init_cpus, + .smp_prepare_cpus = highbank_smp_prepare_cpus, + .smp_boot_secondary = highbank_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = highbank_cpu_die, +#endif +}; diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c index 7f2bd85..04eddb4 100644 --- a/arch/arm/mach-highbank/pm.c +++ b/arch/arm/mach-highbank/pm.c @@ -16,19 +16,27 @@ #include <linux/cpu_pm.h> #include <linux/init.h> +#include <linux/io.h> #include <linux/suspend.h> +#include <asm/cacheflush.h> +#include <asm/proc-fns.h> #include <asm/suspend.h> -#include <asm/psci.h> + +#include "core.h" +#include "sysregs.h" static int highbank_suspend_finish(unsigned long val) { - const struct psci_power_state ps = { - .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, - .affinity_level = 1, - }; + outer_flush_all(); + outer_disable(); + + highbank_set_pwr_suspend(); + + cpu_do_idle(); - return psci_ops.cpu_suspend(ps, __pa(cpu_resume)); + highbank_clear_pwr_request(); + return 0; } static int highbank_pm_enter(suspend_state_t state) @@ -36,11 +44,15 @@ static int highbank_pm_enter(suspend_state_t state) cpu_pm_enter(); cpu_cluster_pm_enter(); + highbank_set_cpu_jump(0, cpu_resume); cpu_suspend(0, highbank_suspend_finish); cpu_cluster_pm_exit(); cpu_pm_exit(); + highbank_smc1(0x102, 0x1); + if (scu_base_addr) + scu_enable(scu_base_addr); return 0; } @@ -51,8 +63,5 @@ static const struct platform_suspend_ops highbank_pm_ops = { void __init highbank_pm_init(void) { - if (!psci_ops.cpu_suspend) - return; - suspend_set_ops(&highbank_pm_ops); } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7a6e6f7..29a8af6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -4,14 +4,13 @@ config ARCH_MXC select ARM_CPU_SUSPEND if PM select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR if !ZBOOT_ROM + select CLKDEV_LOOKUP select CLKSRC_MMIO - select COMMON_CLK select GENERIC_ALLOCATOR select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 select MULTI_IRQ_HANDLER - select SOC_BUS select SPARSE_IRQ select USE_OF help @@ -25,7 +24,7 @@ config MXC_IRQ_PRIOR help Select this if you want to use prioritized IRQ handling. This feature prevents higher priority ISR to be interrupted - by lower priority IRQ. + by lower priority IRQ even IRQF_DISABLED flag is not set. This may be useful in embedded applications, where are strong requirements for timing. Say N here, unless you have a specialized requirement. @@ -93,12 +92,14 @@ config MACH_MX27 config SOC_IMX1 bool select ARCH_MX1 + select COMMON_CLK select CPU_ARM920T select IMX_HAVE_IOMUX_V1 select MXC_AVIC config SOC_IMX21 bool + select COMMON_CLK select CPU_ARM926T select IMX_HAVE_IOMUX_V1 select MXC_AVIC @@ -107,6 +108,7 @@ config SOC_IMX25 bool select ARCH_MX25 select ARCH_MXC_IOMUX_V3 + select COMMON_CLK select CPU_ARM926T select MXC_AVIC @@ -114,6 +116,7 @@ config SOC_IMX27 bool select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP + select COMMON_CLK select CPU_ARM926T select IMX_HAVE_IOMUX_V1 select MACH_MX27 @@ -121,6 +124,7 @@ config SOC_IMX27 config SOC_IMX31 bool + select COMMON_CLK select CPU_V6 select IMX_HAVE_PLATFORM_MXC_RNGA select MXC_AVIC @@ -129,6 +133,7 @@ config SOC_IMX31 config SOC_IMX35 bool select ARCH_MXC_IOMUX_V3 + select COMMON_CLK select CPU_V6K select HAVE_EPIT select MXC_AVIC @@ -139,6 +144,7 @@ config SOC_IMX5 select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARCH_MXC_IOMUX_V3 + select COMMON_CLK select CPU_V7 select MXC_TZIC @@ -785,6 +791,7 @@ config SOC_IMX6Q select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 select ARM_GIC + select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -794,8 +801,6 @@ config SOC_IMX6Q select HAVE_IMX_SRC select HAVE_SMP select MFD_SYSCON - select MIGHT_HAVE_PCI - select PCI_DOMAINS if PCI select PINCTRL select PINCTRL_IMX6Q select PL310_ERRATA_588369 if CACHE_PL310 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 1789e2b..5383c58 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -102,8 +102,6 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o -# i.MX6SL reuses i.MX6Q code -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o endif # i.MX5 based machines diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 4a40bbb..ad3b755 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -16,7 +16,6 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "common.h" -#include "hardware.h" #define REG_SET 0x4 #define REG_CLR 0x8 @@ -27,7 +26,6 @@ #define ANADIG_USB1_CHRG_DETECT 0x1b0 #define ANADIG_USB2_CHRG_DETECT 0x210 #define ANADIG_DIGPROG 0x260 -#define ANADIG_DIGPROG_IMX6SL 0x280 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 @@ -78,38 +76,21 @@ static void imx_anatop_usb_chrg_detect_disable(void) BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); } -void __init imx_init_revision_from_anatop(void) +u32 imx_anatop_get_digprog(void) { struct device_node *np; void __iomem *anatop_base; - unsigned int revision; - u32 digprog; - u16 offset = ANADIG_DIGPROG; + static u32 digprog; + + if (digprog) + return digprog; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); WARN_ON(!anatop_base); - if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) - offset = ANADIG_DIGPROG_IMX6SL; - digprog = readl_relaxed(anatop_base + offset); - iounmap(anatop_base); - - switch (digprog & 0xff) { - case 0: - revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - revision = IMX_CHIP_REVISION_1_2; - break; - default: - revision = IMX_CHIP_REVISION_UNKNOWN; - } + digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG); - mxc_set_cpu_type(digprog >> 16 & 0xff); - imx_set_soc_revision(revision); + return digprog; } void __init imx_anatop_init(void) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index ce37af2..7c0dc45 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -11,12 +11,8 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/clkdev.h> -#include <linux/clk-provider.h> #include <linux/of.h> #include <linux/err.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> #include "crm-regs-imx5.h" #include "clk.h" @@ -135,6 +131,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, { int i; + of_clk_init(NULL); + clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); @@ -467,17 +465,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, return 0; } -static void __init mx51_clocks_init_dt(struct device_node *np) -{ - mx51_clocks_init(0, 0, 0, 0); -} -CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); - -static void __init mx53_clocks_init(struct device_node *np) +int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, + unsigned long rate_ckih1, unsigned long rate_ckih2) { - int i, irq; + int i; unsigned long r; - void __iomem *base; + struct device_node *np; clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); @@ -536,11 +529,12 @@ static void __init mx53_clocks_init(struct device_node *np) pr_err("i.MX53 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); + np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm"); clk_data.clks = clk; clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(0, 0, 0, 0); + mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); @@ -563,6 +557,9 @@ static void __init mx53_clocks_init(struct device_node *np) clk_set_rate(clk[esdhc_a_podf], 200000000); clk_set_rate(clk[esdhc_b_podf], 200000000); + /* System timer */ + mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); + clk_prepare_enable(clk[iim_gate]); imx_print_silicon_rev("i.MX53", mx53_revision()); clk_disable_unprepare(clk[iim_gate]); @@ -570,10 +567,15 @@ static void __init mx53_clocks_init(struct device_node *np) r = clk_round_rate(clk[usboh3_per_gate], 54000000); clk_set_rate(clk[usboh3_per_gate], r); - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); + return 0; +} + +int __init mx51_clocks_init_dt(void) +{ + return mx51_clocks_init(0, 0, 0, 0); +} + +int __init mx53_clocks_init_dt(void) +{ + return mx53_clocks_init(0, 0, 0, 0); } -CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 04cfd0f..9181a24 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -14,6 +14,7 @@ #include <linux/types.h> #include <linux/clk.h> #include <linux/clkdev.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> @@ -24,6 +25,155 @@ #include "common.h" #include "hardware.h" +#define CCR 0x0 +#define BM_CCR_WB_COUNT (0x7 << 16) +#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) +#define BM_CCR_RBC_EN (0x1 << 27) + +#define CCGR0 0x68 +#define CCGR1 0x6c +#define CCGR2 0x70 +#define CCGR3 0x74 +#define CCGR4 0x78 +#define CCGR5 0x7c +#define CCGR6 0x80 +#define CCGR7 0x84 + +#define CLPCR 0x54 +#define BP_CLPCR_LPM 0 +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) +#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_STBY_COUNT (0x3 << 9) +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) +#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) +#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) +#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) +#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) +#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) +#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) +#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) +#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) + +#define CGPR 0x64 +#define BM_CGPR_CHICKEN_BIT (0x1 << 17) + +static void __iomem *ccm_base; + +void imx6q_set_chicken_bit(void) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val |= BM_CGPR_CHICKEN_BIT; + writel_relaxed(val, ccm_base + CGPR); +} + +static void imx6q_enable_rbc(bool enable) +{ + u32 val; + static bool last_rbc_mode; + + if (last_rbc_mode == enable) + return; + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpc_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_EN; + val |= enable ? BM_CCR_RBC_EN : 0; + writel_relaxed(val, ccm_base + CCR); + + /* configure RBC count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_BYPASS_COUNT; + val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; + writel(val, ccm_base + CCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpc_restore_all(); + + last_rbc_mode = enable; +} + +static void imx6q_enable_wb(bool enable) +{ + u32 val; + static bool last_wb_mode; + + if (last_wb_mode == enable) + return; + + /* configure well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configure well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); + + last_wb_mode = enable; +} + +int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) +{ + u32 val = readl_relaxed(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + switch (mode) { + case WAIT_CLOCKED: + imx6q_enable_wb(false); + imx6q_enable_rbc(false); + break; + case WAIT_UNCLOCKED: + val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; + break; + case STOP_POWER_ON: + val |= 0x2 << BP_CLPCR_LPM; + break; + case WAIT_UNCLOCKED_POWER_OFF: + val |= 0x1 << BP_CLPCR_LPM; + val &= ~BM_CLPCR_VSTBY; + val &= ~BM_CLPCR_SBYOS; + break; + case STOP_POWER_OFF: + val |= 0x2 << BP_CLPCR_LPM; + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + imx6q_enable_wb(true); + imx6q_enable_rbc(true); + break; + default: + return -EINVAL; + } + + writel_relaxed(val, ccm_base + CLPCR); + + return 0; +} + static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; @@ -32,7 +182,7 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; -static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; +static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; static const char *gpu_axi_sels[] = { "axi", "ahb", }; static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; @@ -46,7 +196,7 @@ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; static const char *pcie_axi_sels[] = { "axi", "ahb", }; -static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; +static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; @@ -55,7 +205,7 @@ static const char *vdo_axi_sels[] = { "axi", "ahb", }; static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", - "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; + "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; static const char *cko2_sels[] = { "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", @@ -67,11 +217,6 @@ static const char *cko2_sels[] = { "uart_serial", "spdif", "asrc", "hsi_tx", }; static const char *cko_sels[] = { "cko1", "cko2", }; -static const char *lvds_sels[] = { - "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", - "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", - "pcie_ref", "sata_ref", -}; enum mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, @@ -106,8 +251,7 @@ enum mx6q_clks { ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, - spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, - lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max + spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max }; static struct clk *clk[clk_max]; @@ -122,14 +266,13 @@ static struct clk_div_table clk_enet_ref_table[] = { { .val = 1, .div = 10, }, { .val = 2, .div = 5, }, { .val = 3, .div = 4, }, - { /* sentinel */ } }; static struct clk_div_table post_div_table[] = { { .val = 2, .div = 1, }, { .val = 1, .div = 2, }, { .val = 0, .div = 4, }, - { /* sentinel */ } + { } }; static struct clk_div_table video_div_table[] = { @@ -137,7 +280,7 @@ static struct clk_div_table video_div_table[] = { { .val = 1, .div = 2, }, { .val = 2, .div = 1, }, { .val = 3, .div = 4, }, - { /* sentinel */ } + { } }; static void __init imx6q_clocks_init(struct device_node *ccm_node) @@ -157,7 +300,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) WARN_ON(!base); /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) { post_div_table[1].div = 1; post_div_table[2].div = 1; video_div_table[1].div = 1; @@ -199,18 +342,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); - clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); - - /* - * lvds1_gate and lvds2_gate are pseudo-gates. Both can be - * independently configured as clock inputs or outputs. We treat - * the "output_enable" bit as a gate, even though it's really just - * enabling clock output. - */ - clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); - clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); - /* name parent_name reg idx */ clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); @@ -228,15 +359,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); - clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); np = ccm_node; base = of_iomap(np, 0); WARN_ON(!base); - - imx6q_pm_set_ccm_base(base); + ccm_base = base; /* name reg shift width parent_names num_parents */ clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); @@ -299,7 +428,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); - clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); + clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); @@ -444,8 +573,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); - if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || - cpu_is_imx6dl()) { + if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); } @@ -475,9 +603,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (ret) pr_warn("failed to set up CLKO: %d\n", ret); - /* All existing boards with PCIe use LVDS1 */ - if (IS_ENABLED(CONFIG_PCI_IMX6)) - clk_set_parent(clk[lvds1_sel], clk[sata_ref]); + /* Set initial power mode */ + imx6q_set_lpm(WAIT_CLOCKED); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); base = of_iomap(np, 0); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index c0c4ef5..a5c3c5d 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -127,9 +127,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) base = of_iomap(np, 0); WARN_ON(!base); - /* Reuse imx6q pm code */ - imx6q_pm_set_ccm_base(base); - /* name reg shift width parent_names num_parents */ clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 6136405..f6640b6 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -12,7 +12,6 @@ #include <linux/clk.h> #include <linux/clk-provider.h> -#include <linux/delay.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/jiffies.h> @@ -46,49 +45,33 @@ struct clk_pllv3 { #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) -static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(10); - u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; - - /* No need to wait for lock when pll is not powered up */ - if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) - return 0; - - /* Wait for PLL to lock */ - do { - if (readl_relaxed(pll->base) & BM_PLL_LOCK) - break; - if (time_after(jiffies, timeout)) - break; - usleep_range(50, 500); - } while (1); - - return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; -} - static int clk_pllv3_prepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); + unsigned long timeout; u32 val; - int ret; val = readl_relaxed(pll->base); + val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= BM_PLL_POWER; else val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); - ret = clk_pllv3_wait_lock(pll); - if (ret) - return ret; - - val = readl_relaxed(pll->base); - val &= ~BM_PLL_BYPASS; - writel_relaxed(val, pll->base); + timeout = jiffies + msecs_to_jiffies(10); + /* Wait for PLL to lock */ + do { + if (readl_relaxed(pll->base) & BM_PLL_LOCK) + break; + if (time_after(jiffies, timeout)) + break; + } while (1); - return 0; + if (readl_relaxed(pll->base) & BM_PLL_LOCK) + return 0; + else + return -ETIMEDOUT; } static void clk_pllv3_unprepare(struct clk_hw *hw) @@ -163,7 +146,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, val |= div; writel_relaxed(val, pll->base); - return clk_pllv3_wait_lock(pll); + return 0; } static const struct clk_ops clk_pllv3_ops = { @@ -219,7 +202,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, val |= div; writel_relaxed(val, pll->base); - return clk_pllv3_wait_lock(pll); + return 0; } static const struct clk_ops clk_pllv3_sys_ops = { @@ -293,7 +276,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); - return clk_pllv3_wait_lock(pll); + return 0; } static const struct clk_ops clk_pllv3_av_ops = { diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 24a7899..4517fd7 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -13,73 +13,74 @@ #include <linux/reboot.h> -struct irq_data; struct platform_device; struct pt_regs; struct clk; enum mxc_cpu_pwr_mode; -void mx1_map_io(void); -void mx21_map_io(void); -void mx25_map_io(void); -void mx27_map_io(void); -void mx31_map_io(void); -void mx35_map_io(void); -void mx51_map_io(void); -void mx53_map_io(void); -void imx1_init_early(void); -void imx21_init_early(void); -void imx25_init_early(void); -void imx27_init_early(void); -void imx31_init_early(void); -void imx35_init_early(void); -void imx51_init_early(void); -void imx53_init_early(void); -void mxc_init_irq(void __iomem *); -void tzic_init_irq(void __iomem *); -void mx1_init_irq(void); -void mx21_init_irq(void); -void mx25_init_irq(void); -void mx27_init_irq(void); -void mx31_init_irq(void); -void mx35_init_irq(void); -void mx51_init_irq(void); -void mx53_init_irq(void); -void imx1_soc_init(void); -void imx21_soc_init(void); -void imx25_soc_init(void); -void imx27_soc_init(void); -void imx31_soc_init(void); -void imx35_soc_init(void); -void imx51_soc_init(void); -void imx51_init_late(void); -void imx53_init_late(void); -void epit_timer_init(void __iomem *base, int irq); -void mxc_timer_init(void __iomem *, int); -int mx1_clocks_init(unsigned long fref); -int mx21_clocks_init(unsigned long lref, unsigned long fref); -int mx25_clocks_init(void); -int mx27_clocks_init(unsigned long fref); -int mx31_clocks_init(unsigned long fref); -int mx35_clocks_init(void); -int mx51_clocks_init(unsigned long ckil, unsigned long osc, +extern void mx1_map_io(void); +extern void mx21_map_io(void); +extern void mx25_map_io(void); +extern void mx27_map_io(void); +extern void mx31_map_io(void); +extern void mx35_map_io(void); +extern void mx51_map_io(void); +extern void mx53_map_io(void); +extern void imx1_init_early(void); +extern void imx21_init_early(void); +extern void imx25_init_early(void); +extern void imx27_init_early(void); +extern void imx31_init_early(void); +extern void imx35_init_early(void); +extern void imx51_init_early(void); +extern void imx53_init_early(void); +extern void mxc_init_irq(void __iomem *); +extern void tzic_init_irq(void __iomem *); +extern void mx1_init_irq(void); +extern void mx21_init_irq(void); +extern void mx25_init_irq(void); +extern void mx27_init_irq(void); +extern void mx31_init_irq(void); +extern void mx35_init_irq(void); +extern void mx51_init_irq(void); +extern void mx53_init_irq(void); +extern void imx1_soc_init(void); +extern void imx21_soc_init(void); +extern void imx25_soc_init(void); +extern void imx27_soc_init(void); +extern void imx31_soc_init(void); +extern void imx35_soc_init(void); +extern void imx51_soc_init(void); +extern void imx51_init_late(void); +extern void imx53_init_late(void); +extern void epit_timer_init(void __iomem *base, int irq); +extern void mxc_timer_init(void __iomem *, int); +extern int mx1_clocks_init(unsigned long fref); +extern int mx21_clocks_init(unsigned long lref, unsigned long fref); +extern int mx25_clocks_init(void); +extern int mx27_clocks_init(unsigned long fref); +extern int mx31_clocks_init(unsigned long fref); +extern int mx35_clocks_init(void); +extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -int mx25_clocks_init_dt(void); -int mx27_clocks_init_dt(void); -int mx31_clocks_init_dt(void); -struct platform_device *mxc_register_gpio(char *name, int id, +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); +extern int mx25_clocks_init_dt(void); +extern int mx27_clocks_init_dt(void); +extern int mx31_clocks_init_dt(void); +extern int mx51_clocks_init_dt(void); +extern int mx53_clocks_init_dt(void); +extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); -void mxc_set_cpu_type(unsigned int type); -void mxc_restart(enum reboot_mode, const char *); -void mxc_arch_reset_init(void __iomem *); -void mxc_arch_reset_init_dt(void); -int mx53_revision(void); -void imx_set_aips(void __iomem *); -int mxc_device_init(void); -void imx_set_soc_revision(unsigned int rev); -unsigned int imx_get_soc_revision(void); -void imx_init_revision_from_anatop(void); -struct device *imx_soc_device_init(void); +extern void mxc_set_cpu_type(unsigned int type); +extern void mxc_restart(enum reboot_mode, const char *); +extern void mxc_arch_reset_init(void __iomem *); +extern void mxc_arch_reset_init_dt(void); +extern int mx53_revision(void); +extern int imx6q_revision(void); +extern int mx53_display_revision(void); +extern void imx_set_aips(void __iomem *); +extern int mxc_device_init(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -96,8 +97,8 @@ enum mx3_cpu_pwr_mode { MX3_SLEEP, }; -void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); -void imx_print_silicon_rev(const char *cpu, int srev); +extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); +extern void imx_print_silicon_rev(const char *cpu, int srev); void avic_handle_irq(struct pt_regs *); void tzic_handle_irq(struct pt_regs *); @@ -111,56 +112,54 @@ void tzic_handle_irq(struct pt_regs *); #define imx51_handle_irq tzic_handle_irq #define imx53_handle_irq tzic_handle_irq -void imx_enable_cpu(int cpu, bool enable); -void imx_set_cpu_jump(int cpu, void *jump_addr); -u32 imx_get_cpu_arg(int cpu); -void imx_set_cpu_arg(int cpu, u32 arg); -void v7_cpu_resume(void); +extern void imx_enable_cpu(int cpu, bool enable); +extern void imx_set_cpu_jump(int cpu, void *jump_addr); +extern u32 imx_get_cpu_arg(int cpu); +extern void imx_set_cpu_arg(int cpu, u32 arg); +extern void v7_cpu_resume(void); #ifdef CONFIG_SMP -void v7_secondary_startup(void); -void imx_scu_map_io(void); -void imx_smp_prepare(void); -void imx_scu_standby_enable(void); +extern void v7_secondary_startup(void); +extern void imx_scu_map_io(void); +extern void imx_smp_prepare(void); +extern void imx_scu_standby_enable(void); #else static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} static inline void imx_scu_standby_enable(void) {} #endif -void imx_src_init(void); -void imx_gpc_init(void); -void imx_gpc_pre_suspend(void); -void imx_gpc_post_resume(void); -void imx_gpc_mask_all(void); -void imx_gpc_restore_all(void); -void imx_gpc_irq_mask(struct irq_data *d); -void imx_gpc_irq_unmask(struct irq_data *d); -void imx_anatop_init(void); -void imx_anatop_pre_suspend(void); -void imx_anatop_post_resume(void); -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_chicken_bit(void); - -void imx_cpu_die(unsigned int cpu); -int imx_cpu_kill(unsigned int cpu); +extern void imx_src_init(void); +extern void imx_src_prepare_restart(void); +extern void imx_gpc_init(void); +extern void imx_gpc_pre_suspend(void); +extern void imx_gpc_post_resume(void); +extern void imx_gpc_mask_all(void); +extern void imx_gpc_restore_all(void); +extern void imx_anatop_init(void); +extern void imx_anatop_pre_suspend(void); +extern void imx_anatop_post_resume(void); +extern u32 imx_anatop_get_digprog(void); +extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); +extern void imx6q_set_chicken_bit(void); + +extern void imx_cpu_die(unsigned int cpu); +extern int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_PM -void imx6q_pm_init(void); -void imx6q_pm_set_ccm_base(void __iomem *base); -void imx5_pm_init(void); +extern void imx6q_pm_init(void); +extern void imx5_pm_init(void); #else static inline void imx6q_pm_init(void) {} -static inline void imx6q_pm_set_ccm_base(void __iomem *base) {} static inline void imx5_pm_init(void) {} #endif #ifdef CONFIG_NEON -int mx51_neon_fixup(void); +extern int mx51_neon_fixup(void); #else static inline int mx51_neon_fixup(void) { return 0; } #endif #ifdef CONFIG_CACHE_L2X0 -void imx_init_l2cache(void); +extern void imx_init_l2cache(void); #else static inline void imx_init_l2cache(void) {} #endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index ba3b498..e70e3ac 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -1,9 +1,6 @@ -#include <linux/err.h> + #include <linux/module.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/slab.h> -#include <linux/sys_soc.h> #include "hardware.h" #include "common.h" @@ -11,23 +8,11 @@ unsigned int __mxc_cpu_type; EXPORT_SYMBOL(__mxc_cpu_type); -static unsigned int imx_soc_revision; - void mxc_set_cpu_type(unsigned int type) { __mxc_cpu_type = type; } -void imx_set_soc_revision(unsigned int rev) -{ - imx_soc_revision = rev; -} - -unsigned int imx_get_soc_revision(void) -{ - return imx_soc_revision; -} - void imx_print_silicon_rev(const char *cpu, int srev) { if (srev == IMX_CHIP_REVISION_UNKNOWN) @@ -59,81 +44,3 @@ void __init imx_set_aips(void __iomem *base) reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); } - -struct device * __init imx_soc_device_init(void) -{ - struct soc_device_attribute *soc_dev_attr; - struct soc_device *soc_dev; - struct device_node *root; - const char *soc_id; - int ret; - - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return NULL; - - soc_dev_attr->family = "Freescale i.MX"; - - root = of_find_node_by_path("/"); - ret = of_property_read_string(root, "model", &soc_dev_attr->machine); - of_node_put(root); - if (ret) - goto free_soc; - - switch (__mxc_cpu_type) { - case MXC_CPU_MX1: - soc_id = "i.MX1"; - break; - case MXC_CPU_MX21: - soc_id = "i.MX21"; - break; - case MXC_CPU_MX25: - soc_id = "i.MX25"; - break; - case MXC_CPU_MX27: - soc_id = "i.MX27"; - break; - case MXC_CPU_MX31: - soc_id = "i.MX31"; - break; - case MXC_CPU_MX35: - soc_id = "i.MX35"; - break; - case MXC_CPU_MX51: - soc_id = "i.MX51"; - break; - case MXC_CPU_MX53: - soc_id = "i.MX53"; - break; - case MXC_CPU_IMX6SL: - soc_id = "i.MX6SL"; - break; - case MXC_CPU_IMX6DL: - soc_id = "i.MX6DL"; - break; - case MXC_CPU_IMX6Q: - soc_id = "i.MX6Q"; - break; - default: - soc_id = "Unknown"; - } - soc_dev_attr->soc_id = soc_id; - - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", - (imx_soc_revision >> 4) & 0xf, - imx_soc_revision & 0xf); - if (!soc_dev_attr->revision) - goto free_soc; - - soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) - goto free_rev; - - return soc_device_to_device(soc_dev); - -free_rev: - kfree(soc_dev_attr->revision); -free_soc: - kfree(soc_dev_attr); - return NULL; -} diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c index 074b1a8..e02de18 100644 --- a/arch/arm/mach-imx/epit.c +++ b/arch/arm/mach-imx/epit.c @@ -171,7 +171,7 @@ static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) static struct irqaction epit_timer_irq = { .name = "i.MX EPIT Timer Tick", - .flags = IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = epit_timer_interrupt, }; diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 586e017..44a65e9 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -90,7 +90,7 @@ void imx_gpc_restore_all(void) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); } -void imx_gpc_irq_unmask(struct irq_data *d) +static void imx_gpc_irq_unmask(struct irq_data *d) { void __iomem *reg; u32 val; @@ -105,7 +105,7 @@ void imx_gpc_irq_unmask(struct irq_data *d) writel_relaxed(val, reg); } -void imx_gpc_irq_mask(struct irq_data *d) +static void imx_gpc_irq_mask(struct irq_data *d) { void __iomem *reg; u32 val; diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index b35e99c..3daf1ed 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c @@ -52,9 +52,7 @@ void imx_cpu_die(unsigned int cpu) * the register being cleared to kill the cpu. */ imx_set_cpu_arg(cpu, ~0); - - while (1) - cpu_do_idle(); + cpu_do_idle(); } int imx_cpu_kill(unsigned int cpu) diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index bece8a6..53e43e5 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -34,11 +34,17 @@ static const char *imx51_dt_board_compat[] __initdata = { NULL }; +static void __init imx51_timer_init(void) +{ + mx51_clocks_init_dt(); +} + DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, .handle_irq = imx51_handle_irq, + .init_time = imx51_timer_init, .init_machine = imx51_dt_init, .init_late = imx51_init_late, .dt_compat = imx51_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 58b864a..368a6e3 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -404,7 +404,8 @@ static int armadillo5x0_sdhc1_init(struct device *dev, /* When supported the trigger type have to be BOTH */ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), - detect_irq, IRQF_TRIGGER_FALLING, + detect_irq, + IRQF_DISABLED | IRQF_TRIGGER_FALLING, "sdhc-detect", data); if (ret) diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index c9c4d8d..98c5894 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -36,11 +36,17 @@ static const char *imx53_dt_board_compat[] __initdata = { NULL }; +static void __init imx53_timer_init(void) +{ + mx53_clocks_init_dt(); +} + DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") .map_io = mx53_map_io, .init_early = imx53_init_early, .init_irq = mx53_init_irq, .handle_irq = imx53_handle_irq, + .init_time = imx53_timer_init, .init_machine = imx53_dt_init, .init_late = imx53_init_late, .dt_compat = imx53_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index d0cfb22..90372a2 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -11,8 +11,11 @@ */ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/clkdev.h> +#include <linux/clocksource.h> #include <linux/cpu.h> +#include <linux/delay.h> #include <linux/export.h> #include <linux/init.h> #include <linux/io.h> @@ -22,7 +25,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/pm_opp.h> +#include <linux/opp.h> #include <linux/phy.h> #include <linux/reboot.h> #include <linux/regmap.h> @@ -37,6 +40,64 @@ #include "cpuidle.h" #include "hardware.h" +static u32 chip_revision; + +int imx6q_revision(void) +{ + return chip_revision; +} + +static void __init imx6q_init_revision(void) +{ + u32 rev = imx_anatop_get_digprog(); + + switch (rev & 0xff) { + case 0: + chip_revision = IMX_CHIP_REVISION_1_0; + break; + case 1: + chip_revision = IMX_CHIP_REVISION_1_1; + break; + case 2: + chip_revision = IMX_CHIP_REVISION_1_2; + break; + default: + chip_revision = IMX_CHIP_REVISION_UNKNOWN; + } + + mxc_set_cpu_type(rev >> 16 & 0xff); +} + +static void imx6q_restart(enum reboot_mode mode, const char *cmd) +{ + struct device_node *np; + void __iomem *wdog_base; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); + wdog_base = of_iomap(np, 0); + if (!wdog_base) + goto soft; + + imx_src_prepare_restart(); + + /* enable wdog */ + writew_relaxed(1 << 2, wdog_base); + /* write twice to ensure the request will not get ignored */ + writew_relaxed(1 << 2, wdog_base); + + /* wait for reset to assert ... */ + mdelay(500); + + pr_err("Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); + +soft: + /* we'll take a jump through zero as a poor second */ + soft_restart(0); +} + /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { @@ -131,20 +192,9 @@ static void __init imx6q_1588_init(void) static void __init imx6q_init_machine(void) { - struct device *parent; - - imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx_get_soc_revision()); - - mxc_arch_reset_init_dt(); - - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - imx6q_enet_phy_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); imx_anatop_init(); imx6q_pm_init(); @@ -176,7 +226,7 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) val = readl_relaxed(base + OCOTP_CFG3); val >>= OCOTP_CFG3_SPEED_SHIFT; if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) - if (dev_pm_opp_disable(cpu_dev, 1200000000)) + if (opp_disable(cpu_dev, 1200000000)) pr_warn("failed to disable 1.2 GHz OPP\n"); put_node: @@ -219,7 +269,7 @@ static void __init imx6q_init_late(void) * WAIT mode is broken on TO 1.0 and 1.1, so there is no point * to run cpuidle on them. */ - if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) + if (imx6q_revision() > IMX_CHIP_REVISION_1_1) imx6q_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { @@ -236,13 +286,21 @@ static void __init imx6q_map_io(void) static void __init imx6q_init_irq(void) { - imx_init_revision_from_anatop(); + imx6q_init_revision(); imx_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init(); } +static void __init imx6q_timer_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", + imx6q_revision()); +} + static const char *imx6q_dt_compat[] __initdata = { "fsl,imx6dl", "fsl,imx6q", @@ -253,8 +311,9 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, + .init_time = imx6q_timer_init, .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, - .restart = mxc_restart, + .restart = imx6q_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 2f952e3..0d75dc5 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -7,60 +7,35 @@ * */ +#include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> -#include <linux/mfd/syscon.h> -#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> -#include <linux/regmap.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include "common.h" -static void __init imx6sl_fec_init(void) -{ - struct regmap *gpr; - - /* set FEC clock from internal PLL clock source */ - gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); - if (!IS_ERR(gpr)) { - regmap_update_bits(gpr, IOMUXC_GPR1, - IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, - IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); - } else { - pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); - } -} - static void __init imx6sl_init_machine(void) { - struct device *parent; - mxc_arch_reset_init_dt(); - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); - - imx6sl_fec_init(); - imx_anatop_init(); - /* Reuse imx6q pm code */ - imx6q_pm_init(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static void __init imx6sl_init_irq(void) { - imx_init_revision_from_anatop(); imx_init_l2cache(); imx_src_init(); imx_gpc_init(); irqchip_init(); } +static void __init imx6sl_timer_init(void) +{ + of_clk_init(NULL); +} + static const char *imx6sl_dt_compat[] __initdata = { "fsl,imx6sl", NULL, @@ -69,6 +44,7 @@ static const char *imx6sl_dt_compat[] __initdata = { DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") .map_io = debug_ll_io_init, .init_irq = imx6sl_init_irq, + .init_time = imx6sl_timer_init, .init_machine = imx6sl_init_machine, .dt_compat = imx6sl_dt_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 50044a2..1ed9161 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -311,7 +311,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev, } ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), - detect_irq, + detect_irq, IRQF_DISABLED | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-detect", data); if (ret) { diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index c5f9567..19bb644 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -20,7 +20,7 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/dma-mapping.h> #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 639a3df..bc0261e 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -23,7 +23,7 @@ #include <linux/smsc911x.h> #include <linux/interrupt.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/delay.h> #include <linux/spi/spi.h> #include <linux/irq.h> @@ -371,7 +371,8 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, #endif ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq, - IRQF_TRIGGER_FALLING, "sdhc-detect", data); + IRQF_DISABLED | IRQF_TRIGGER_FALLING, + "sdhc-detect", data); if (ret) goto err_gpio_free_2; diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 592ddbe..e805ac2 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -18,7 +18,7 @@ */ #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/io.h> #include <linux/mtd/plat-ram.h> #include <linux/mtd/physmap.h> diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index ac504b6..b726cb1 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -24,7 +24,7 @@ #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index af0cb8a..816991d 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -8,7 +8,9 @@ */ #include <linux/of_platform.h> +#include <linux/clocksource.h> #include <linux/irqchip.h> +#include <linux/clk-provider.h> #include <asm/mach/arch.h> #include <asm/hardware/cache-l2x0.h> @@ -26,6 +28,12 @@ static void __init vf610_init_irq(void) irqchip_init(); } +static void __init vf610_init_time(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + static const char *vf610_dt_compat[] __initdata = { "fsl,vf610", NULL, @@ -33,6 +41,7 @@ static const char *vf610_dt_compat[] __initdata = { DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") .init_irq = vf610_init_irq, + .init_time = vf610_init_time, .init_machine = vf610_init_machine, .dt_compat = vf610_dt_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 8825d12..0910761 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -29,7 +29,7 @@ #include <asm/mach/time.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/mfd/mc13xxx.h> #include "common.h" diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index d1d5260..eb3cce3 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/pinctrl/machine.h> -#include <linux/of_address.h> #include <asm/mach/map.h> @@ -89,15 +88,8 @@ void __init imx51_init_early(void) void __init imx53_init_early(void) { - struct device_node *np; - void __iomem *base; - mxc_set_cpu_type(MXC_CPU_MX53); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc"); - base = of_iomap(np, 0); - WARN_ON(!base); - mxc_iomux_v3_init(base); + mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); imx_src_init(); } @@ -108,14 +100,7 @@ void __init mx51_init_irq(void) void __init mx53_init_irq(void) { - struct device_node *np; - void __iomem *base; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic"); - base = of_iomap(np, 0); - WARN_ON(!base); - - tzic_init_irq(base); + tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); } static struct sdma_platform_data imx51_sdma_pdata __initdata = { diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c index 649fe49..d4361b8 100644 --- a/arch/arm/mach-imx/mx31lilly-db.c +++ b/arch/arm/mach-imx/mx31lilly-db.c @@ -130,7 +130,8 @@ static int mxc_mmc1_init(struct device *dev, gpio_direction_input(gpio_wp); ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), - detect_irq, IRQF_TRIGGER_FALLING, + detect_irq, + IRQF_DISABLED | IRQF_TRIGGER_FALLING, "MMC detect", data); if (ret) goto exit_free_wp; diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index b08ab3a..8629e5b 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -34,7 +34,6 @@ #define MXC_CPU_MX35 35 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 -#define MXC_CPU_IMX6SL 0x60 #define MXC_CPU_IMX6DL 0x61 #define MXC_CPU_IMX6Q 0x63 @@ -153,11 +152,6 @@ extern unsigned int __mxc_cpu_type; #endif #ifndef __ASSEMBLY__ -static inline bool cpu_is_imx6sl(void) -{ - return __mxc_cpu_type == MXC_CPU_IMX6SL; -} - static inline bool cpu_is_imx6dl(void) { return __mxc_cpu_type == MXC_CPU_IMX6DL; diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index aecd9f8..2049427 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -10,15 +10,9 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/irq.h> -#include <linux/mfd/syscon.h> -#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/regmap.h> #include <linux/suspend.h> #include <asm/cacheflush.h> #include <asm/proc-fns.h> @@ -28,147 +22,6 @@ #include "common.h" #include "hardware.h" -#define CCR 0x0 -#define BM_CCR_WB_COUNT (0x7 << 16) -#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) -#define BM_CCR_RBC_EN (0x1 << 27) - -#define CLPCR 0x54 -#define BP_CLPCR_LPM 0 -#define BM_CLPCR_LPM (0x3 << 0) -#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) -#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define BM_CLPCR_SBYOS (0x1 << 6) -#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define BM_CLPCR_VSTBY (0x1 << 8) -#define BP_CLPCR_STBY_COUNT 9 -#define BM_CLPCR_STBY_COUNT (0x3 << 9) -#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) -#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) -#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) -#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) -#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) -#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) -#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) -#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) -#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) -#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) - -#define CGPR 0x64 -#define BM_CGPR_CHICKEN_BIT (0x1 << 17) - -static void __iomem *ccm_base; - -void imx6q_set_chicken_bit(void) -{ - u32 val = readl_relaxed(ccm_base + CGPR); - - val |= BM_CGPR_CHICKEN_BIT; - writel_relaxed(val, ccm_base + CGPR); -} - -static void imx6q_enable_rbc(bool enable) -{ - u32 val; - - /* - * need to mask all interrupts in GPC before - * operating RBC configurations - */ - imx_gpc_mask_all(); - - /* configure RBC enable bit */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_EN; - val |= enable ? BM_CCR_RBC_EN : 0; - writel_relaxed(val, ccm_base + CCR); - - /* configure RBC count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_BYPASS_COUNT; - val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; - writel(val, ccm_base + CCR); - - /* - * need to delay at least 2 cycles of CKIL(32K) - * due to hardware design requirement, which is - * ~61us, here we use 65us for safe - */ - udelay(65); - - /* restore GPC interrupt mask settings */ - imx_gpc_restore_all(); -} - -static void imx6q_enable_wb(bool enable) -{ - u32 val; - - /* configure well bias enable bit */ - val = readl_relaxed(ccm_base + CLPCR); - val &= ~BM_CLPCR_WB_PER_AT_LPM; - val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; - writel_relaxed(val, ccm_base + CLPCR); - - /* configure well bias count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_WB_COUNT; - val |= enable ? BM_CCR_WB_COUNT : 0; - writel_relaxed(val, ccm_base + CCR); -} - -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -{ - struct irq_desc *iomuxc_irq_desc; - u32 val = readl_relaxed(ccm_base + CLPCR); - - val &= ~BM_CLPCR_LPM; - switch (mode) { - case WAIT_CLOCKED: - break; - case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; - val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; - break; - case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; - break; - case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; - break; - case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) { - val |= BM_CLPCR_BYPASS_PMIC_READY; - val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; - } else { - val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; - } - break; - default: - return -EINVAL; - } - - /* - * Unmask the always pending IOMUXC interrupt #32 as wakeup source to - * deassert dsm_request signal, so that we can ensure dsm_request - * is not asserted when we're going to write CLPCR register to set LPM. - * After setting up LPM bits, we need to mask this wakeup source. - */ - iomuxc_irq_desc = irq_to_desc(32); - imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); - writel_relaxed(val, ccm_base + CLPCR); - imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data); - - return 0; -} - static int imx6q_suspend_finish(unsigned long val) { cpu_do_idle(); @@ -180,19 +33,14 @@ static int imx6q_pm_enter(suspend_state_t state) switch (state) { case PM_SUSPEND_MEM: imx6q_set_lpm(STOP_POWER_OFF); - imx6q_enable_wb(true); - imx6q_enable_rbc(true); imx_gpc_pre_suspend(); imx_anatop_pre_suspend(); imx_set_cpu_jump(0, v7_cpu_resume); /* Zzz ... */ cpu_suspend(0, imx6q_suspend_finish); - if (cpu_is_imx6q() || cpu_is_imx6dl()) - imx_smp_prepare(); + imx_smp_prepare(); imx_anatop_post_resume(); imx_gpc_post_resume(); - imx6q_enable_rbc(false); - imx6q_enable_wb(false); imx6q_set_lpm(WAIT_CLOCKED); break; default: @@ -207,29 +55,7 @@ static const struct platform_suspend_ops imx6q_pm_ops = { .valid = suspend_valid_only_mem, }; -void __init imx6q_pm_set_ccm_base(void __iomem *base) -{ - ccm_base = base; -} - void __init imx6q_pm_init(void) { - struct regmap *gpr; - - WARN_ON(!ccm_base); - - /* - * Force IOMUXC irq pending, so that the interrupt to GPC can be - * used to deassert dsm_request signal when the signal gets - * asserted unexpectedly. - */ - gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); - if (!IS_ERR(gpr)) - regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, - IMX6Q_GPR1_GINT); - - /* Set initial power mode */ - imx6q_set_lpm(WAIT_CLOCKED); - suspend_set_ops(&imx6q_pm_ops); } diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 45f7f4e..10a6b1a 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -91,7 +91,6 @@ void imx_enable_cpu(int cpu, bool enable) spin_lock(&scr_lock); val = readl_relaxed(src_base + SRC_SCR); val = enable ? val | mask : val & ~mask; - val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); writel_relaxed(val, src_base + SRC_SCR); spin_unlock(&scr_lock); } @@ -115,6 +114,21 @@ void imx_set_cpu_arg(int cpu, u32 arg) writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); } +void imx_src_prepare_restart(void) +{ + u32 val; + + /* clear enable bits of secondary cores */ + spin_lock(&scr_lock); + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); + spin_unlock(&scr_lock); + + /* clear persistent entry register of primary core */ + writel_relaxed(0, src_base + SRC_GPR1); +} + void __init imx_src_init(void) { struct device_node *np; diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 5e3027d..80c177c 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -52,15 +52,6 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); - /* - * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be - * written twice), we add another two writes to ensure there must be at - * least two writes happen in the same one 32kHz clock period. We save - * the target check here, since the writes shouldn't be a huge burden - * for other platforms. - */ - __raw_writew(wcr_enable, wdog_base); - __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 9b6638a..cd46529 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -250,7 +250,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) static struct irqaction mxc_timer_irq = { .name = "i.MX Timer Tick", - .flags = IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = mxc_timer_interrupt, }; diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 00ddf20..4cdfd73 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -22,30 +22,77 @@ #include <linux/amba/serial.h> #include <linux/io.h> #include <linux/stat.h> -#include <linux/of.h> -#include <linux/of_address.h> #include <mach/hardware.h> #include <mach/platform.h> +#include <mach/cm.h> +#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/time.h> #include <asm/pgtable.h> -#include "cm.h" #include "common.h" -static DEFINE_RAW_SPINLOCK(cm_lock); -static void __iomem *cm_base; +#ifdef CONFIG_ATAGS -/** - * cm_get - get the value from the CM_CTRL register - */ -u32 cm_get(void) +#define INTEGRATOR_RTC_IRQ { IRQ_RTCINT } +#define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 } +#define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 } +#define KMI0_IRQ { IRQ_KMIINT0 } +#define KMI1_IRQ { IRQ_KMIINT1 } + +static AMBA_APB_DEVICE(rtc, "rtc", 0, + INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL); + +static AMBA_APB_DEVICE(uart0, "uart0", 0, + INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL); + +static AMBA_APB_DEVICE(uart1, "uart1", 0, + INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL); + +static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL); +static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL); + +static struct amba_device *amba_devs[] __initdata = { + &rtc_device, + &uart0_device, + &uart1_device, + &kmi0_device, + &kmi1_device, +}; + +int __init integrator_init(bool is_cp) { - return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); + int i; + + /* + * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to + * hard-code them. The Integator/CP and forward have proper cell IDs. + * Else we leave them undefined to the bus driver can autoprobe them. + */ + if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) { + rtc_device.periphid = 0x00041030; + uart0_device.periphid = 0x00041010; + uart1_device.periphid = 0x00041010; + kmi0_device.periphid = 0x00041050; + kmi1_device.periphid = 0x00041050; + uart0_device.dev.platform_data = &ap_uart_data; + uart1_device.dev.platform_data = &ap_uart_data; + } + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + + return 0; } +#endif + +static DEFINE_RAW_SPINLOCK(cm_lock); + /** * cm_control - update the CM_CTRL register. * @mask: bits to change @@ -57,80 +104,12 @@ void cm_control(u32 mask, u32 set) u32 val; raw_spin_lock_irqsave(&cm_lock, flags); - val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; - writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); + val = readl(CM_CTRL) & ~mask; + writel(val | set, CM_CTRL); raw_spin_unlock_irqrestore(&cm_lock, flags); } -static const char *integrator_arch_str(u32 id) -{ - switch ((id >> 16) & 0xff) { - case 0x00: - return "ASB little-endian"; - case 0x01: - return "AHB little-endian"; - case 0x03: - return "AHB-Lite system bus, bi-endian"; - case 0x04: - return "AHB"; - case 0x08: - return "AHB system bus, ASB processor bus"; - default: - return "Unknown"; - } -} - -static const char *integrator_fpga_str(u32 id) -{ - switch ((id >> 12) & 0xf) { - case 0x01: - return "XC4062"; - case 0x02: - return "XC4085"; - case 0x03: - return "XVC600"; - case 0x04: - return "EPM7256AE (Altera PLD)"; - default: - return "Unknown"; - } -} - -void cm_clear_irqs(void) -{ - /* disable core module IRQs */ - writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + - IRQ_ENABLE_CLEAR); -} - -static const struct of_device_id cm_match[] = { - { .compatible = "arm,core-module-integrator"}, - { }, -}; - -void cm_init(void) -{ - struct device_node *cm = of_find_matching_node(NULL, cm_match); - u32 val; - - if (!cm) { - pr_crit("no core module node found in device tree\n"); - return; - } - cm_base = of_iomap(cm, 0); - if (!cm_base) { - pr_crit("could not remap core module\n"); - return; - } - cm_clear_irqs(); - val = readl(cm_base + INTEGRATOR_HDR_ID_OFFSET); - pr_info("Detected ARM core module:\n"); - pr_info(" Manufacturer: %02x\n", (val >> 24)); - pr_info(" Architecture: %s\n", integrator_arch_str(val)); - pr_info(" FPGA: %s\n", integrator_fpga_str(val)); - pr_info(" Build: %02x\n", (val >> 4) & 0xFF); - pr_info(" Rev: %c\n", ('A' + (val & 0x03))); -} +EXPORT_SYMBOL(cm_control); /* * We need to stop things allocating the low memory; ideally we need a @@ -166,7 +145,27 @@ static ssize_t intcp_get_arch(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", integrator_arch_str(integrator_id)); + const char *arch; + + switch ((integrator_id >> 16) & 0xff) { + case 0x00: + arch = "ASB little-endian"; + break; + case 0x01: + arch = "AHB little-endian"; + break; + case 0x03: + arch = "AHB-Lite system bus, bi-endian"; + break; + case 0x04: + arch = "AHB"; + break; + default: + arch = "Unknown"; + break; + } + + return sprintf(buf, "%s\n", arch); } static struct device_attribute intcp_arch_attr = @@ -176,7 +175,24 @@ static ssize_t intcp_get_fpga(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", integrator_fpga_str(integrator_id)); + const char *fpga; + + switch ((integrator_id >> 12) & 0xf) { + case 0x01: + fpga = "XC4062"; + break; + case 0x02: + fpga = "XC4085"; + break; + case 0x04: + fpga = "EPM7256AE (Altera PLD)"; + break; + default: + fpga = "Unknown"; + break; + } + + return sprintf(buf, "%s\n", fpga); } static struct device_attribute intcp_fpga_attr = diff --git a/arch/arm/mach-integrator/cm.h b/arch/arm/mach-integrator/include/mach/cm.h index 4ecff7b..202e6a5 100644 --- a/arch/arm/mach-integrator/cm.h +++ b/arch/arm/mach-integrator/include/mach/cm.h @@ -1,12 +1,9 @@ /* - * access the core module control register. + * update the core module control register. */ -u32 cm_get(void); void cm_control(u32, u32); -struct device_node; -void cm_init(void); -void cm_clear_irqs(void); +#define CM_CTRL __io_address(INTEGRATOR_HDR_CTRL) #define CM_CTRL_LED (1 << 0) #define CM_CTRL_nMBDET (1 << 1) diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h new file mode 100644 index 0000000..eff0ada --- /dev/null +++ b/arch/arm/mach-integrator/include/mach/irqs.h @@ -0,0 +1,81 @@ +/* + * arch/arm/mach-integrator/include/mach/irqs.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Interrupt numbers, all of the above are just static reservations + * used so they can be encoded into device resources. They will finally + * be done away with when switching to device tree. + */ +#define IRQ_PIC_START 64 +#define IRQ_SOFTINT (IRQ_PIC_START+0) +#define IRQ_UARTINT0 (IRQ_PIC_START+1) +#define IRQ_UARTINT1 (IRQ_PIC_START+2) +#define IRQ_KMIINT0 (IRQ_PIC_START+3) +#define IRQ_KMIINT1 (IRQ_PIC_START+4) +#define IRQ_TIMERINT0 (IRQ_PIC_START+5) +#define IRQ_TIMERINT1 (IRQ_PIC_START+6) +#define IRQ_TIMERINT2 (IRQ_PIC_START+7) +#define IRQ_RTCINT (IRQ_PIC_START+8) +#define IRQ_AP_EXPINT0 (IRQ_PIC_START+9) +#define IRQ_AP_EXPINT1 (IRQ_PIC_START+10) +#define IRQ_AP_EXPINT2 (IRQ_PIC_START+11) +#define IRQ_AP_EXPINT3 (IRQ_PIC_START+12) +#define IRQ_AP_PCIINT0 (IRQ_PIC_START+13) +#define IRQ_AP_PCIINT1 (IRQ_PIC_START+14) +#define IRQ_AP_PCIINT2 (IRQ_PIC_START+15) +#define IRQ_AP_PCIINT3 (IRQ_PIC_START+16) +#define IRQ_AP_V3INT (IRQ_PIC_START+17) +#define IRQ_AP_CPINT0 (IRQ_PIC_START+18) +#define IRQ_AP_CPINT1 (IRQ_PIC_START+19) +#define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20) +#define IRQ_AP_APCINT (IRQ_PIC_START+21) +#define IRQ_CP_CLCDCINT (IRQ_PIC_START+22) +#define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23) +#define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24) +#define IRQ_CP_AACIINT (IRQ_PIC_START+25) +#define IRQ_CP_CPPLDINT (IRQ_PIC_START+26) +#define IRQ_CP_ETHINT (IRQ_PIC_START+27) +#define IRQ_CP_TSPENINT (IRQ_PIC_START+28) +#define IRQ_PIC_END (IRQ_PIC_START+28) + +#define IRQ_CIC_START (IRQ_PIC_END+1) +#define IRQ_CM_SOFTINT (IRQ_CIC_START+0) +#define IRQ_CM_COMMRX (IRQ_CIC_START+1) +#define IRQ_CM_COMMTX (IRQ_CIC_START+2) +#define IRQ_CIC_END (IRQ_CIC_START+2) + +/* + * IntegratorCP only + */ +#define IRQ_SIC_START (IRQ_CIC_END+1) +#define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0) +#define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1) +#define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2) +#define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3) +#define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4) +#define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5) +#define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6) +#define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7) +#define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8) +#define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9) +#define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10) +#define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11) +#define IRQ_SIC_END (IRQ_SIC_START+11) diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index d50dc2d..d9e95e6 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -51,13 +51,13 @@ #include <asm/mach-types.h> #include <mach/lm.h> +#include <mach/irqs.h> #include <asm/mach/arch.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include "cm.h" #include "common.h" #include "pci_v3.h" @@ -146,7 +146,7 @@ static int irq_suspend(void) static void irq_resume(void) { /* disable all irq sources */ - cm_clear_irqs(); + writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); @@ -402,6 +402,8 @@ void __init ap_init_early(void) { } +#ifdef CONFIG_OF + static void __init ap_of_timer_init(void) { struct device_node *node; @@ -448,7 +450,8 @@ static const struct of_device_id fpga_irq_of_match[] __initconst = { static void __init ap_init_irq_of(void) { - cm_init(); + /* disable core module IRQs */ + writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); of_irq_init(fpga_irq_of_match); integrator_clk_init(false); } @@ -470,11 +473,6 @@ static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; -static const struct of_device_id ap_syscon_match[] = { - { .compatible = "arm,integrator-ap-syscon"}, - { }, -}; - static void __init ap_init_of(void) { unsigned long sc_dec; @@ -491,8 +489,7 @@ static void __init ap_init_of(void) root = of_find_node_by_path("/"); if (!root) return; - - syscon = of_find_matching_node(root, ap_syscon_match); + syscon = of_find_node_by_path("/syscon"); if (!syscon) return; @@ -544,7 +541,7 @@ static void __init ap_init_of(void) lmdev->resource.start = 0xc0000000 + 0x10000000 * i; lmdev->resource.end = lmdev->resource.start + 0x0fffffff; lmdev->resource.flags = IORESOURCE_MEM; - lmdev->irq = irq_of_parse_and_map(syscon, i); + lmdev->irq = IRQ_AP_EXPINT0 + i; lmdev->id = i; lm_device_register(lmdev); @@ -567,3 +564,136 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") .restart = integrator_restart, .dt_compat = ap_dt_board_compat, MACHINE_END + +#endif + +#ifdef CONFIG_ATAGS + +/* + * For the ATAG boot some static mappings are needed. This will + * go away with the ATAG support down the road. + */ + +static struct map_desc ap_io_desc_atag[] __initdata = { + { + .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, +}; + +static void __init ap_map_io_atag(void) +{ + iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag)); + ap_map_io(); +} + +/* + * This is where non-devicetree initialization code is collected and stashed + * for eventual deletion. + */ + +static struct platform_device pci_v3_device = { + .name = "pci-v3", + .id = 0, +}; + +static struct resource cfi_flash_resource = { + .start = INTEGRATOR_FLASH_BASE, + .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device cfi_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ap_flash_data, + }, + .num_resources = 1, + .resource = &cfi_flash_resource, +}; + +static void __init ap_timer_init(void) +{ + struct clk *clk; + unsigned long rate; + + clk = clk_get_sys("ap_timer", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + + writel(0, TIMER0_VA_BASE + TIMER_CTRL); + writel(0, TIMER1_VA_BASE + TIMER_CTRL); + writel(0, TIMER2_VA_BASE + TIMER_CTRL); + + integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE); + integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE, + IRQ_TIMERINT1); +} + +#define INTEGRATOR_SC_VALID_INT 0x003fffff + +static void __init ap_init_irq(void) +{ + /* Disable all interrupts initially. */ + /* Do the core module ones */ + writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); + + /* do the header card stuff next */ + writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); + writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); + + fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, + -1, INTEGRATOR_SC_VALID_INT, NULL); + integrator_clk_init(false); +} + +static void __init ap_init(void) +{ + unsigned long sc_dec; + int i; + + platform_device_register(&pci_v3_device); + platform_device_register(&cfi_flash_device); + + ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); + sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); + for (i = 0; i < 4; i++) { + struct lm_device *lmdev; + + if ((sc_dec & (16 << i)) == 0) + continue; + + lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); + if (!lmdev) + continue; + + lmdev->resource.start = 0xc0000000 + 0x10000000 * i; + lmdev->resource.end = lmdev->resource.start + 0x0fffffff; + lmdev->resource.flags = IORESOURCE_MEM; + lmdev->irq = IRQ_AP_EXPINT0 + i; + lmdev->id = i; + + lm_device_register(lmdev); + } + + integrator_init(false); +} + +MACHINE_START(INTEGRATOR, "ARM-Integrator") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .atag_offset = 0x100, + .reserve = integrator_reserve, + .map_io = ap_map_io_atag, + .init_early = ap_init_early, + .init_irq = ap_init_irq, + .handle_irq = fpga_handle_irq, + .init_time = ap_timer_init, + .init_machine = ap_init, + .restart = integrator_restart, +MACHINE_END + +#endif diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 4fc0a19..8c60fcb 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -36,7 +36,9 @@ #include <asm/hardware/arm_timer.h> #include <asm/hardware/icst.h> +#include <mach/cm.h> #include <mach/lm.h> +#include <mach/irqs.h> #include <asm/mach/arch.h> #include <asm/mach/irq.h> @@ -48,7 +50,6 @@ #include <plat/clcd.h> #include <plat/sched_clock.h> -#include "cm.h" #include "common.h" /* Base address to the CP controller */ @@ -198,8 +199,7 @@ static struct mmci_platform_data mmc_data = { static void cp_clcd_enable(struct clcd_fb *fb) { struct fb_var_screeninfo *var = &fb->fb.var; - u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2 - | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1; + u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2; if (var->bits_per_pixel <= 8 || (var->bits_per_pixel == 16 && var->green.length == 5)) @@ -249,6 +249,7 @@ static void __init intcp_init_early(void) #endif } +#ifdef CONFIG_OF static const struct of_device_id fpga_irq_of_match[] __initconst = { { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, { /* Sentinel */ } @@ -256,7 +257,6 @@ static const struct of_device_id fpga_irq_of_match[] __initconst = { static void __init intcp_init_irq_of(void) { - cm_init(); of_irq_init(fpga_irq_of_match); integrator_clk_init(true); } @@ -287,11 +287,6 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; -static const struct of_device_id intcp_syscon_match[] = { - { .compatible = "arm,integrator-cp-syscon"}, - { }, -}; - static void __init intcp_init_of(void) { struct device_node *root; @@ -306,8 +301,7 @@ static void __init intcp_init_of(void) root = of_find_node_by_path("/"); if (!root) return; - - cpcon = of_find_matching_node(root, intcp_syscon_match); + cpcon = of_find_node_by_path("/cpcon"); if (!cpcon) return; @@ -360,3 +354,175 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") .restart = integrator_restart, .dt_compat = intcp_dt_board_compat, MACHINE_END + +#endif + +#ifdef CONFIG_ATAGS + +/* + * For the ATAG boot some static mappings are needed. This will + * go away with the ATAG support down the road. + */ + +static struct map_desc intcp_io_desc_atag[] __initdata = { + { + .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE), + .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, +}; + +static void __init intcp_map_io_atag(void) +{ + iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag)); + intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE); + intcp_map_io(); +} + + +/* + * This is where non-devicetree initialization code is collected and stashed + * for eventual deletion. + */ + +#define INTCP_FLASH_SIZE SZ_32M + +static struct resource intcp_flash_resource = { + .start = INTCP_PA_FLASH_BASE, + .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device intcp_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &intcp_flash_data, + }, + .num_resources = 1, + .resource = &intcp_flash_resource, +}; + +#define INTCP_ETH_SIZE 0x10 + +static struct resource smc91x_resources[] = { + [0] = { + .start = INTEGRATOR_CP_ETH_BASE, + .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CP_ETHINT, + .end = IRQ_CP_ETHINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *intcp_devs[] __initdata = { + &intcp_flash_device, + &smc91x_device, +}; + +#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) +#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) +#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) + +static void __init intcp_init_irq(void) +{ + u32 pic_mask, cic_mask, sic_mask; + + /* These masks are for the HW IRQ registers */ + pic_mask = ~((~0u) << (11 - 0)); + pic_mask |= (~((~0u) << (29 - 22))) << 22; + cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); + sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); + + /* + * Disable all interrupt sources + */ + writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); + writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); + writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); + writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); + + fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, + -1, pic_mask, NULL); + + fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, + -1, cic_mask, NULL); + + fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, + IRQ_CP_CPPLDINT, sic_mask, NULL); + + integrator_clk_init(true); +} + +#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) + +static void __init cp_timer_init(void) +{ + writel(0, TIMER0_VA_BASE + TIMER_CTRL); + writel(0, TIMER1_VA_BASE + TIMER_CTRL); + writel(0, TIMER2_VA_BASE + TIMER_CTRL); + + sp804_clocksource_init(TIMER2_VA_BASE, "timer2"); + sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); +} + +#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } +#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } + +static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE, + INTEGRATOR_CP_MMC_IRQS, &mmc_data); + +static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE, + INTEGRATOR_CP_AACI_IRQS, NULL); + +static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE, + { IRQ_CP_CLCDCINT }, &clcd_data); + +static struct amba_device *amba_devs[] __initdata = { + &mmc_device, + &aaci_device, + &clcd_device, +}; + +static void __init intcp_init(void) +{ + int i; + + platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + integrator_init(true); +} + +MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .atag_offset = 0x100, + .reserve = integrator_reserve, + .map_io = intcp_map_io_atag, + .init_early = intcp_init_early, + .init_irq = intcp_init_irq, + .handle_irq = fpga_handle_irq, + .init_time = cp_timer_init, + .init_machine = intcp_init, + .restart = integrator_restart, +MACHINE_END + +#endif diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c index cb6ac58..7a7f6d3 100644 --- a/arch/arm/mach-integrator/leds.c +++ b/arch/arm/mach-integrator/leds.c @@ -11,11 +11,10 @@ #include <linux/slab.h> #include <linux/leds.h> +#include <mach/cm.h> #include <mach/hardware.h> #include <mach/platform.h> -#include "cm.h" - #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) #define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE) @@ -79,7 +78,7 @@ static void cm_led_set(struct led_classdev *cdev, static enum led_brightness cm_led_get(struct led_classdev *cdev) { - u32 reg = cm_get(); + u32 reg = readl(CM_CTRL); return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF; } diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index c5e01b2..bef1005 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -36,6 +36,7 @@ #include <mach/hardware.h> #include <mach/platform.h> +#include <mach/irqs.h> #include <asm/mach/map.h> #include <asm/signal.h> @@ -604,7 +605,7 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) return 1; } -static irqreturn_t v3_irq(int irq, void *devid) +static irqreturn_t v3_irq(int dummy, void *devid) { #ifdef CONFIG_DEBUG_LL struct pt_regs *regs = get_irq_regs(); @@ -614,7 +615,7 @@ static irqreturn_t v3_irq(int irq, void *devid) extern void printascii(const char *); sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " - "ISTAT=%02x\n", irq, pc, instr, + "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, v3_readb(V3_LB_ISTAT)); @@ -808,6 +809,21 @@ static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) return pci_common_swizzle(dev, pinp); } +static int irq_tab[4] __initdata = { + IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 +}; + +/* + * map the specified device/slot/pin to an IRQ. This works out such + * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. + */ +static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int intnr = ((slot - 9) + (pin - 1)) & 3; + + return irq_tab[intnr]; +} + static struct hw_pci pci_v3 __initdata = { .swizzle = pci_v3_swizzle, .setup = pci_v3_setup, @@ -817,27 +833,32 @@ static struct hw_pci pci_v3 __initdata = { .postinit = pci_v3_postinit, }; -static int __init pci_v3_probe(struct platform_device *pdev) +#ifdef CONFIG_OF + +static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct of_irq oirq; + int ret; + + ret = of_irq_map_pci(dev, &oirq); + if (ret) { + dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret); + /* Proper return code 0 == NO_IRQ */ + return 0; + } + + return irq_create_of_mapping(oirq.controller, oirq.specifier, + oirq.size); +} + +static int __init pci_v3_dtprobe(struct platform_device *pdev, + struct device_node *np) { - struct device_node *np = pdev->dev.of_node; struct of_pci_range_parser parser; struct of_pci_range range; struct resource *res; int irq, ret; - /* Remap the Integrator system controller */ - ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100); - if (!ap_syscon_base) { - dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); - return -ENODEV; - } - - /* Device tree probe path */ - if (!np) { - dev_err(&pdev->dev, "no device tree node for PCIv3\n"); - return -ENODEV; - } - if (of_pci_range_parser_init(&parser, np)) return -EINVAL; @@ -898,7 +919,77 @@ static int __init pci_v3_probe(struct platform_device *pdev) return -EINVAL; } - pci_v3.map_irq = of_irq_parse_and_map_pci; + pci_v3.map_irq = pci_v3_map_irq_dt; + pci_common_init_dev(&pdev->dev, &pci_v3); + + return 0; +} + +#else + +static inline int pci_v3_dtprobe(struct platform_device *pdev, + struct device_node *np) +{ + return -EINVAL; +} + +#endif + +static int __init pci_v3_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int ret; + + /* Remap the Integrator system controller */ + ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); + if (!ap_syscon_base) { + dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); + return -ENODEV; + } + + /* Device tree probe path */ + if (np) + return pci_v3_dtprobe(pdev, np); + + pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); + if (!pci_v3_base) { + dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); + return -ENODEV; + } + + ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); + if (ret) { + dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", + ret); + return -ENODEV; + } + + conf_mem.name = "PCIv3 config"; + conf_mem.start = PHYS_PCI_CONFIG_BASE; + conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1; + conf_mem.flags = IORESOURCE_MEM; + + io_mem.name = "PCIv3 I/O"; + io_mem.start = PHYS_PCI_IO_BASE; + io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; + io_mem.flags = IORESOURCE_MEM; + + non_mem_pci = 0x00000000; + non_mem_pci_sz = SZ_256M; + non_mem.name = "PCIv3 non-prefetched mem"; + non_mem.start = PHYS_PCI_MEM_BASE; + non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1; + non_mem.flags = IORESOURCE_MEM; + + pre_mem_pci = 0x10000000; + pre_mem_pci_sz = SZ_256M; + pre_mem.name = "PCIv3 prefetched mem"; + pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M; + pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1; + pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + pci_v3.map_irq = pci_v3_map_irq; + pci_common_init_dev(&pdev->dev, &pci_v3); return 0; diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h index a86fd0e..6d3782d 100644 --- a/arch/arm/mach-iop13xx/include/mach/adma.h +++ b/arch/arm/mach-iop13xx/include/mach/adma.h @@ -218,6 +218,20 @@ iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) #define iop_chan_pq_slot_count iop_chan_xor_slot_count #define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->dest_addr; +} + +static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->q_dest_addr; +} + static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, struct iop_adma_chan *chan) { @@ -336,6 +350,18 @@ iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, hw_desc->desc_ctrl = u_desc_ctrl.value; } +static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = hw_desc->desc_ctrl; + return u_desc_ctrl.field.pq_xfer_en; +} + static inline void iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, unsigned long flags) diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 177cd07..31fbb6c 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -32,7 +32,6 @@ #include <asm/mach/time.h> #include <asm/mach-types.h> #include <mach/time.h> -#include "gpio-iop32x.h" static void __init em7210_timer_init(void) { @@ -184,7 +183,6 @@ void em7210_power_off(void) static void __init em7210_init_machine(void) { - register_iop32x_gpio(); platform_device_register(&em7210_serial_device); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 547b234..ac30470 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -34,7 +34,6 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <mach/time.h> -#include "gpio-iop32x.h" /* * GLAN Tank timer tick configuration. @@ -188,7 +187,6 @@ static void glantank_power_off(void) static void __init glantank_init_machine(void) { - register_iop32x_gpio(); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&glantank_flash_device); diff --git a/arch/arm/mach-iop32x/gpio-iop32x.h b/arch/arm/mach-iop32x/gpio-iop32x.h deleted file mode 100644 index 3c7309c..0000000 --- a/arch/arm/mach-iop32x/gpio-iop32x.h +++ /dev/null @@ -1,10 +0,0 @@ -static struct resource iop32x_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x07c4), 0x10), -}; - -static inline void register_iop32x_gpio(void) -{ - platform_device_register_simple("gpio-iop", 0, - iop32x_gpio_res, - ARRAY_SIZE(iop32x_gpio_res)); -} diff --git a/arch/arm/mach-iop32x/include/mach/gpio.h b/arch/arm/mach-iop32x/include/mach/gpio.h new file mode 100644 index 0000000..708f4ec --- /dev/null +++ b/arch/arm/mach-iop32x/include/mach/gpio.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_IOP32X_GPIO_H +#define __ASM_ARCH_IOP32X_GPIO_H + +#include <asm/hardware/iop3xx-gpio.h> + +#endif diff --git a/arch/arm/mach-iop32x/include/mach/iop32x.h b/arch/arm/mach-iop32x/include/mach/iop32x.h index 56ec864..941f363 100644 --- a/arch/arm/mach-iop32x/include/mach/iop32x.h +++ b/arch/arm/mach-iop32x/include/mach/iop32x.h @@ -19,6 +19,7 @@ * Peripherals that are shared between the iop32x and iop33x but * located at different addresses. */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c4 + (reg)) #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) #include <asm/hardware/iop3xx.h> diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 0e1392b..f2cd296 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -37,7 +37,6 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <mach/time.h> -#include "gpio-iop32x.h" /* * Until March of 2007 iq31244 platforms and ep80219 platforms shared the @@ -284,7 +283,6 @@ void ep80219_power_off(void) static void __init iq31244_init_machine(void) { - register_iop32x_gpio(); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iq31244_flash_device); diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 66782ff..015435d 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -33,7 +33,6 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <mach/time.h> -#include "gpio-iop32x.h" /* * IQ80321 timer tick configuration. @@ -171,7 +170,6 @@ static struct platform_device iq80321_serial_device = { static void __init iq80321_init_machine(void) { - register_iop32x_gpio(); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iq80321_flash_device); diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index c1cd80e..0691443 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -30,7 +30,6 @@ #include <linux/platform_device.h> #include <linux/reboot.h> #include <linux/io.h> -#include <linux/gpio.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach/arch.h> @@ -41,7 +40,6 @@ #include <asm/page.h> #include <asm/pgtable.h> #include <mach/time.h> -#include "gpio-iop32x.h" /* * N2100 timer tick configuration. @@ -290,14 +288,8 @@ static void n2100_power_off(void) static void n2100_restart(enum reboot_mode mode, const char *cmd) { - int ret; - - ret = gpio_direction_output(N2100_HARDWARE_RESET, 0); - if (ret) { - pr_crit("could not drive reset GPIO low\n"); - return; - } - /* Wait for reset to happen */ + gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW); + gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT); while (1) ; } @@ -307,7 +299,7 @@ static struct timer_list power_button_poll_timer; static void power_button_poll(unsigned long dummy) { - if (gpio_get_value(N2100_POWER_BUTTON) == 0) { + if (gpio_line_get(N2100_POWER_BUTTON) == 0) { ctrl_alt_del(); return; } @@ -316,37 +308,9 @@ static void power_button_poll(unsigned long dummy) add_timer(&power_button_poll_timer); } -static int __init n2100_request_gpios(void) -{ - int ret; - - if (!machine_is_n2100()) - return 0; - - ret = gpio_request(N2100_HARDWARE_RESET, "reset"); - if (ret) - pr_err("could not request reset GPIO\n"); - - ret = gpio_request(N2100_POWER_BUTTON, "power"); - if (ret) - pr_err("could not request power GPIO\n"); - else { - ret = gpio_direction_input(N2100_POWER_BUTTON); - if (ret) - pr_err("could not set power GPIO as input\n"); - } - /* Set up power button poll timer */ - init_timer(&power_button_poll_timer); - power_button_poll_timer.function = power_button_poll; - power_button_poll_timer.expires = jiffies + (HZ / 10); - add_timer(&power_button_poll_timer); - return 0; -} -device_initcall(n2100_request_gpios); static void __init n2100_init_machine(void) { - register_iop32x_gpio(); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&n2100_flash_device); platform_device_register(&n2100_serial_device); @@ -357,6 +321,11 @@ static void __init n2100_init_machine(void) ARRAY_SIZE(n2100_i2c_devices)); pm_power_off = n2100_power_off; + + init_timer(&power_button_poll_timer); + power_button_poll_timer.function = power_button_poll; + power_button_poll_timer.expires = jiffies + (HZ / 10); + add_timer(&power_button_poll_timer); } MACHINE_START(N2100, "Thecus N2100") diff --git a/arch/arm/mach-iop33x/include/mach/gpio.h b/arch/arm/mach-iop33x/include/mach/gpio.h new file mode 100644 index 0000000..ddd55bb --- /dev/null +++ b/arch/arm/mach-iop33x/include/mach/gpio.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_IOP33X_GPIO_H +#define __ASM_ARCH_IOP33X_GPIO_H + +#include <asm/hardware/iop3xx-gpio.h> + +#endif diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h index c951226..a89c0a2 100644 --- a/arch/arm/mach-iop33x/include/mach/iop33x.h +++ b/arch/arm/mach-iop33x/include/mach/iop33x.h @@ -18,6 +18,7 @@ * Peripherals that are shared between the iop32x and iop33x but * located at different addresses. */ +#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg)) #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) #include <asm/hardware/iop3xx.h> diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index e2cb65c..c43304a 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -122,15 +122,8 @@ static struct platform_device iq80331_flash_device = { .resource = &iq80331_flash_resource, }; -static struct resource iq80331_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10), -}; - static void __init iq80331_init_machine(void) { - platform_device_register_simple("gpio-iop", 0, - iq80331_gpio_res, - ARRAY_SIZE(iq80331_gpio_res)); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iop33x_uart0_device); diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 0b6269d..8192987 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -122,15 +122,8 @@ static struct platform_device iq80332_flash_device = { .resource = &iq80332_flash_resource, }; -static struct resource iq80332_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10), -}; - static void __init iq80332_init_machine(void) { - platform_device_register_simple("gpio-iop", 0, - iq80332_gpio_res, - ARRAY_SIZE(iq80332_gpio_res)); platform_device_register(&iop3xx_i2c0_device); platform_device_register(&iop3xx_i2c1_device); platform_device_register(&iop33x_uart0_device); diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index c342dc4..30e1ebe 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -1,5 +1,9 @@ if ARCH_IXP4XX +config ARCH_SUPPORTS_BIG_ENDIAN + bool + default y + menu "Intel IXP4xx Implementation Options" comment "IXP4xx Platforms" diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 9edaf47..5327dec 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -81,44 +81,6 @@ void __init ixp4xx_map_io(void) iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); } -/* - * GPIO-functions - */ -/* - * The following converted to the real HW bits the gpio_line_config - */ -/* GPIO pin types */ -#define IXP4XX_GPIO_OUT 0x1 -#define IXP4XX_GPIO_IN 0x2 - -/* GPIO signal types */ -#define IXP4XX_GPIO_LOW 0 -#define IXP4XX_GPIO_HIGH 1 - -/* GPIO Clocks */ -#define IXP4XX_GPIO_CLK_0 14 -#define IXP4XX_GPIO_CLK_1 15 - -static void gpio_line_config(u8 line, u32 direction) -{ - if (direction == IXP4XX_GPIO_IN) - *IXP4XX_GPIO_GPOER |= (1 << line); - else - *IXP4XX_GPIO_GPOER &= ~(1 << line); -} - -static void gpio_line_get(u8 line, int *value) -{ - *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1; -} - -static void gpio_line_set(u8 line, int value) -{ - if (value == IXP4XX_GPIO_HIGH) - *IXP4XX_GPIO_GPOUTR |= (1 << line); - else if (value == IXP4XX_GPIO_LOW) - *IXP4XX_GPIO_GPOUTR &= ~(1 << line); -} /************************************************************************* * IXP4xx chipset IRQ handling @@ -155,6 +117,17 @@ static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) return -EINVAL; } +int irq_to_gpio(unsigned int irq) +{ + int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; + + if (gpio == -1) + return -EINVAL; + + return gpio; +} +EXPORT_SYMBOL(irq_to_gpio); + static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type) { int line = irq2gpio[d->irq]; diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index 736dc69..63de1b3 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -26,7 +26,6 @@ #include <linux/reboot.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> -#include <linux/gpio.h> #include <mach/hardware.h> @@ -162,8 +161,11 @@ static struct platform_device *dsmg600_devices[] __initdata = { static void dsmg600_power_off(void) { - /* enable the pwr cntl and drive it high */ - gpio_direction_output(DSMG600_PO_GPIO, 1); + /* enable the pwr cntl gpio */ + gpio_line_config(DSMG600_PO_GPIO, IXP4XX_GPIO_OUT); + + /* poweroff */ + gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH); } /* This is used to make sure the power-button pusher is serious. The button @@ -200,7 +202,7 @@ static void dsmg600_power_handler(unsigned long data) ctrl_alt_del(); /* Change the state of the power LED to "blink" */ - gpio_set_value(DSMG600_LED_PWR_GPIO, 0); + gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW); } else { power_button_countdown = PBUTTON_HOLDDOWN_COUNT; } @@ -226,40 +228,6 @@ static void __init dsmg600_timer_init(void) ixp4xx_timer_init(); } -static int __init dsmg600_gpio_init(void) -{ - if (!machine_is_dsmg600()) - return 0; - - gpio_request(DSMG600_RB_GPIO, "reset button"); - if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, - IRQF_DISABLED | IRQF_TRIGGER_LOW, - "DSM-G600 reset button", NULL) < 0) { - - printk(KERN_DEBUG "Reset Button IRQ %d not available\n", - gpio_to_irq(DSMG600_RB_GPIO)); - } - - /* - * The power button on the D-Link DSM-G600 is on GPIO 15, but - * it cannot handle interrupts on that GPIO line. So we'll - * have to poll it with a kernel timer. - */ - - /* Make sure that the power button GPIO is set up as an input */ - gpio_request(DSMG600_PB_GPIO, "power button"); - gpio_direction_input(DSMG600_PB_GPIO); - /* Request poweroff GPIO line */ - gpio_request(DSMG600_PO_GPIO, "power off button"); - - /* Set the initial value for the power button IRQ handler */ - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; - - mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); - return 0; -} -device_initcall(dsmg600_gpio_init); - static void __init dsmg600_init(void) { ixp4xx_sys_init(); @@ -283,6 +251,27 @@ static void __init dsmg600_init(void) platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices)); pm_power_off = dsmg600_power_off; + + if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, + IRQF_DISABLED | IRQF_TRIGGER_LOW, + "DSM-G600 reset button", NULL) < 0) { + + printk(KERN_DEBUG "Reset Button IRQ %d not available\n", + gpio_to_irq(DSMG600_RB_GPIO)); + } + + /* The power button on the D-Link DSM-G600 is on GPIO 15, but + * it cannot handle interrupts on that GPIO line. So we'll + * have to poll it with a kernel timer. + */ + + /* Make sure that the power button GPIO is set up as an input */ + gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN); + + /* Set the initial value for the power button IRQ handler */ + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + + mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); } MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h index 75c4c65..4c4c6a6 100644 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h @@ -131,5 +131,44 @@ struct pci_sys_data; extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); extern struct pci_ops ixp4xx_ops; +/* + * GPIO-functions + */ +/* + * The following converted to the real HW bits the gpio_line_config + */ +/* GPIO pin types */ +#define IXP4XX_GPIO_OUT 0x1 +#define IXP4XX_GPIO_IN 0x2 + +/* GPIO signal types */ +#define IXP4XX_GPIO_LOW 0 +#define IXP4XX_GPIO_HIGH 1 + +/* GPIO Clocks */ +#define IXP4XX_GPIO_CLK_0 14 +#define IXP4XX_GPIO_CLK_1 15 + +static inline void gpio_line_config(u8 line, u32 direction) +{ + if (direction == IXP4XX_GPIO_IN) + *IXP4XX_GPIO_GPOER |= (1 << line); + else + *IXP4XX_GPIO_GPOER &= ~(1 << line); +} + +static inline void gpio_line_get(u8 line, int *value) +{ + *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1; +} + +static inline void gpio_line_set(u8 line, int value) +{ + if (value == IXP4XX_GPIO_HIGH) + *IXP4XX_GPIO_GPOUTR |= (1 << line); + else if (value == IXP4XX_GPIO_LOW) + *IXP4XX_GPIO_GPOUTR &= ~(1 << line); +} + #endif // __ASSEMBLY__ diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index e7b8bef..22d688b 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -20,7 +20,6 @@ #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/delay.h> -#include <linux/gpio.h> #include <asm/types.h> #include <asm/setup.h> #include <asm/memory.h> @@ -81,10 +80,10 @@ ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) if (ctrl & NAND_CTRL_CHANGE) { if (ctrl & NAND_NCE) { - gpio_set_value(IXDP425_NAND_NCE_PIN, 0); + gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW); udelay(5); } else - gpio_set_value(IXDP425_NAND_NCE_PIN, 1); + gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH); offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; @@ -228,8 +227,7 @@ static void __init ixdp425_init(void) ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3), ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1; - gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin"); - gpio_direction_output(IXDP425_NAND_NCE_PIN, 0); + gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT); /* Configure expansion bus for NAND Flash */ *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 507cb52..ed667ce 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -184,8 +184,11 @@ static void nas100d_power_off(void) { /* This causes the box to drop the power and go dead. */ - /* enable the pwr cntl gpio and assert power off */ - gpio_direction_output(NAS100D_PO_GPIO, 1); + /* enable the pwr cntl gpio */ + gpio_line_config(NAS100D_PO_GPIO, IXP4XX_GPIO_OUT); + + /* do the deed */ + gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH); } /* This is used to make sure the power-button pusher is serious. The button @@ -222,7 +225,7 @@ static void nas100d_power_handler(unsigned long data) ctrl_alt_del(); /* Change the state of the power LED to "blink" */ - gpio_set_value(NAS100D_LED_PWR_GPIO, 0); + gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW); } else { power_button_countdown = PBUTTON_HOLDDOWN_COUNT; } @@ -239,33 +242,6 @@ static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init nas100d_gpio_init(void) -{ - if (!machine_is_nas100d()) - return 0; - - /* - * The power button on the Iomega NAS100d is on GPIO 14, but - * it cannot handle interrupts on that GPIO line. So we'll - * have to poll it with a kernel timer. - */ - - /* Request the power off GPIO */ - gpio_request(NAS100D_PO_GPIO, "power off"); - - /* Make sure that the power button GPIO is set up as an input */ - gpio_request(NAS100D_PB_GPIO, "power button"); - gpio_direction_input(NAS100D_PB_GPIO); - - /* Set the initial value for the power button IRQ handler */ - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; - - mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); - - return 0; -} -device_initcall(nas100d_gpio_init); - static void __init nas100d_init(void) { uint8_t __iomem *f; @@ -302,6 +278,19 @@ static void __init nas100d_init(void) gpio_to_irq(NAS100D_RB_GPIO)); } + /* The power button on the Iomega NAS100d is on GPIO 14, but + * it cannot handle interrupts on that GPIO line. So we'll + * have to poll it with a kernel timer. + */ + + /* Make sure that the power button GPIO is set up as an input */ + gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN); + + /* Set the initial value for the power button IRQ handler */ + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + + mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); + /* * Map in a portion of the flash and read the MAC address. * Since it is stored in BE in the flash itself, we need to diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index ba5f1cd..7e55236 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -197,8 +197,11 @@ static void nslu2_power_off(void) { /* This causes the box to drop the power and go dead. */ - /* enable the pwr cntl gpio and assert power off */ - gpio_direction_output(NSLU2_PO_GPIO, 1); + /* enable the pwr cntl gpio */ + gpio_line_config(NSLU2_PO_GPIO, IXP4XX_GPIO_OUT); + + /* do the deed */ + gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH); } static irqreturn_t nslu2_power_handler(int irq, void *dev_id) @@ -220,16 +223,6 @@ static irqreturn_t nslu2_reset_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init nslu2_gpio_init(void) -{ - if (!machine_is_nslu2()) - return 0; - - /* Request the power off GPIO */ - return gpio_request(NSLU2_PO_GPIO, "power off"); -} -device_initcall(nslu2_gpio_init); - static void __init nslu2_timer_init(void) { /* The xtal on this machine is non-standard. */ diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index f20c53e..366d1a3 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -9,8 +9,6 @@ config ARCH_KEYSTONE select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_ERRATA_798181 if SMP - select COMMON_CLK_KEYSTONE - select TI_EDMA help Support for boards based on the Texas Instruments Keystone family of SoCs. diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index 25d9239..ddc52b0 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -4,6 +4,3 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) obj-$(CONFIG_SMP) += platsmp.o - -# PM domain driver for Keystone SOCs -obj-$(CONFIG_ARCH_KEYSTONE) += pm_domain.o diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c index 5cf0683..c1229615 100644 --- a/arch/arm/mach-keystone/platsmp.c +++ b/arch/arm/mach-keystone/platsmp.c @@ -17,6 +17,7 @@ #include <linux/io.h> #include <asm/smp_plat.h> +#include <asm/prom.h> #include "keystone.h" diff --git a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c deleted file mode 100644 index 2962523..0000000 --- a/arch/arm/mach-keystone/pm_domain.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * PM domain driver for Keystone2 devices - * - * Copyright 2013 Texas Instruments, Inc. - * Santosh Shilimkar <santosh.shillimkar@ti.com> - * - * Based on Kevins work on DAVINCI SOCs - * Kevin Hilman <khilman@linaro.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/pm_runtime.h> -#include <linux/pm_clock.h> -#include <linux/platform_device.h> -#include <linux/clk-provider.h> -#include <linux/of.h> - -#ifdef CONFIG_PM_RUNTIME -static int keystone_pm_runtime_suspend(struct device *dev) -{ - int ret; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - if (ret) - return ret; - - ret = pm_clk_suspend(dev); - if (ret) { - pm_generic_runtime_resume(dev); - return ret; - } - - return 0; -} - -static int keystone_pm_runtime_resume(struct device *dev) -{ - dev_dbg(dev, "%s\n", __func__); - - pm_clk_resume(dev); - - return pm_generic_runtime_resume(dev); -} -#endif - -static struct dev_pm_domain keystone_pm_domain = { - .ops = { - SET_RUNTIME_PM_OPS(keystone_pm_runtime_suspend, - keystone_pm_runtime_resume, NULL) - USE_PLATFORM_PM_SLEEP_OPS - }, -}; - -static struct pm_clk_notifier_block platform_domain_notifier = { - .pm_domain = &keystone_pm_domain, -}; - -static struct of_device_id of_keystone_table[] = { - {.compatible = "ti,keystone"}, - { /* end of list */ }, -}; - -int __init keystone_pm_runtime_init(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, of_keystone_table); - if (!np) - return 0; - - of_clk_init(NULL); - pm_clk_add_notifier(&platform_bus_type, &platform_domain_notifier); - - return 0; -} -subsys_initcall(keystone_pm_runtime_init); diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 144b511..d1f8e3d 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,7 +1,5 @@ obj-y += common.o pcie.o obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o -obj-$(CONFIG_PM) += pm.o - obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 9caa4fe..82d3ad8 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -13,10 +13,9 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_net.h> #include <linux/of_platform.h> #include <linux/clk-provider.h> +#include <linux/clocksource.h> #include <linux/dma-mapping.h> #include <linux/irqchip.h> #include <linux/kexec.h> @@ -45,6 +44,14 @@ static void __init kirkwood_legacy_clk_init(void) clkspec.np = np; clkspec.args_count = 1; + clkspec.args[0] = CGC_BIT_PEX0; + orion_clkdev_add("0", "pcie", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_PEX1; + orion_clkdev_add("1", "pcie", + of_clk_get_from_provider(&clkspec)); + /* * The ethernet interfaces forget the MAC address assigned by * u-boot if the clocks are turned off. Until proper DT support @@ -59,83 +66,17 @@ static void __init kirkwood_legacy_clk_init(void) clk_prepare_enable(clk); } -#define MV643XX_ETH_MAC_ADDR_LOW 0x0414 -#define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 - -static void __init kirkwood_dt_eth_fixup(void) +static void __init kirkwood_dt_time_init(void) { - struct device_node *np; + of_clk_init(NULL); + clocksource_of_init(); +} - /* - * The ethernet interfaces forget the MAC address assigned by u-boot - * if the clocks are turned off. Usually, u-boot on kirkwood boards - * has no DT support to properly set local-mac-address property. - * As a workaround, we get the MAC address from mv643xx_eth registers - * and update the port device node if no valid MAC address is set. - */ - for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") { - struct device_node *pnp = of_get_parent(np); - struct clk *clk; - struct property *pmac; - void __iomem *io; - u8 *macaddr; - u32 reg; - - if (!pnp) - continue; - - /* skip disabled nodes or nodes with valid MAC address*/ - if (!of_device_is_available(pnp) || of_get_mac_address(np)) - goto eth_fixup_skip; - - clk = of_clk_get(pnp, 0); - if (IS_ERR(clk)) - goto eth_fixup_skip; - - io = of_iomap(pnp, 0); - if (!io) - goto eth_fixup_no_map; - - /* ensure port clock is not gated to not hang CPU */ - clk_prepare_enable(clk); - - /* store MAC address register contents in local-mac-address */ - pr_err(FW_INFO "%s: local-mac-address is not set\n", - np->full_name); - - pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); - if (!pmac) - goto eth_fixup_no_mem; - - pmac->value = pmac + 1; - pmac->length = 6; - pmac->name = kstrdup("local-mac-address", GFP_KERNEL); - if (!pmac->name) { - kfree(pmac); - goto eth_fixup_no_mem; - } - - macaddr = pmac->value; - reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH); - macaddr[0] = (reg >> 24) & 0xff; - macaddr[1] = (reg >> 16) & 0xff; - macaddr[2] = (reg >> 8) & 0xff; - macaddr[3] = reg & 0xff; - - reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW); - macaddr[4] = (reg >> 8) & 0xff; - macaddr[5] = reg & 0xff; - - of_update_property(np, pmac); - -eth_fixup_no_mem: - iounmap(io); - clk_disable_unprepare(clk); -eth_fixup_no_map: - clk_put(clk); -eth_fixup_skip: - of_node_put(pnp); - } +static void __init kirkwood_dt_init_early(void) +{ + mvebu_mbus_init("marvell,kirkwood-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); } static void __init kirkwood_dt_init(void) @@ -151,16 +92,16 @@ static void __init kirkwood_dt_init(void) writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); BUG_ON(mvebu_mbus_dt_init()); + kirkwood_setup_wins(); kirkwood_l2_init(); kirkwood_cpufreq_init(); - kirkwood_cpuidle_init(); + /* Setup clocks for legacy devices */ kirkwood_legacy_clk_init(); - kirkwood_pm_init(); - kirkwood_dt_eth_fixup(); + kirkwood_cpuidle_init(); #ifdef CONFIG_KEXEC kexec_reinit = kirkwood_enable_pcie; @@ -180,6 +121,8 @@ static const char * const kirkwood_dt_board_compat[] = { DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ .map_io = kirkwood_map_io, + .init_early = kirkwood_dt_init_early, + .init_time = kirkwood_dt_time_init, .init_machine = kirkwood_dt_init, .restart = kirkwood_restart, .dt_compat = kirkwood_dt_board_compat, diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3407a5..1767611 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -721,7 +721,6 @@ void __init kirkwood_init(void) kirkwood_xor1_init(); kirkwood_crypto_init(); - kirkwood_pm_init(); kirkwood_cpuidle_init(); #ifdef CONFIG_KEXEC kexec_reinit = kirkwood_enable_pcie; diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 05fd648..1296de9 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -58,12 +58,6 @@ void kirkwood_cpufreq_init(void); void kirkwood_restart(enum reboot_mode, const char *); void kirkwood_clk_init(void); -#ifdef CONFIG_PM -void kirkwood_pm_init(void); -#else -static inline void kirkwood_pm_init(void) {}; -#endif - /* board init functions for boards not fully converted to fdt */ #ifdef CONFIG_MACH_MV88F6281GTW_GE_DT void mv88f6281gtw_ge_init(void); diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 8b9d1c9..91242c9 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -78,6 +78,4 @@ #define CGC_TDM (1 << 20) #define CGC_RESERVED (0x6 << 21) -#define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118) - #endif diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c index 8e3e433..4894959 100644 --- a/arch/arm/mach-kirkwood/lacie_v2-common.c +++ b/arch/arm/mach-kirkwood/lacie_v2-common.c @@ -12,7 +12,7 @@ #include <linux/spi/flash.h> #include <linux/spi/spi.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/gpio.h> #include <asm/mach/time.h> #include <mach/kirkwood.h> diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c deleted file mode 100644 index 8783a71..0000000 --- a/arch/arm/mach-kirkwood/pm.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Power Management driver for Marvell Kirkwood SoCs - * - * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> - * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, - * version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/suspend.h> -#include <linux/io.h> -#include <mach/bridge-regs.h> - -static void __iomem *ddr_operation_base; - -static void kirkwood_low_power(void) -{ - u32 mem_pm_ctrl; - - mem_pm_ctrl = readl(MEMORY_PM_CTRL); - - /* Set peripherals to low-power mode */ - writel_relaxed(~0, MEMORY_PM_CTRL); - - /* Set DDR in self-refresh */ - writel_relaxed(0x7, ddr_operation_base); - - /* - * Set CPU in wait-for-interrupt state. - * This disables the CPU core clocks, - * the array clocks, and also the L2 controller. - */ - cpu_do_idle(); - - writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL); -} - -static int kirkwood_suspend_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_STANDBY: - kirkwood_low_power(); - break; - default: - return -EINVAL; - } - return 0; -} - -static int kirkwood_pm_valid_standby(suspend_state_t state) -{ - return state == PM_SUSPEND_STANDBY; -} - -static const struct platform_suspend_ops kirkwood_suspend_ops = { - .enter = kirkwood_suspend_enter, - .valid = kirkwood_pm_valid_standby, -}; - -int __init kirkwood_pm_init(void) -{ - ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); - suspend_set_ops(&kirkwood_suspend_ops); - return 0; -} diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h new file mode 100644 index 0000000..13219eb --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -0,0 +1,8 @@ +#ifndef __ASM_MACH_GPIO_H +#define __ASM_MACH_GPIO_H + +#include <asm-generic/gpio.h> + +#include <mach/cputype.h> + +#endif /* __ASM_MACH_GPIO_H */ diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index cfadd97..7022329 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -191,6 +191,7 @@ static struct pxa3xx_nand_platform_data dkb_nand_info = { #define SCLK_SOURCE_SELECT(x) (x << 30) /* 0x0 ~ 0x3 */ /* link config */ #define CFG_DUMBMODE(mode) (mode << 28) /* 0x0 ~ 0x6*/ +#define CFG_GRA_SWAPRB(x) (x << 0) /* 1: rbswap enabled */ static struct mmp_mach_path_config dkb_disp_config[] = { [0] = { .name = "mmp-parallel", @@ -198,7 +199,8 @@ static struct mmp_mach_path_config dkb_disp_config[] = { .output_type = PATH_OUT_PARALLEL, .path_config = CFG_IOPADMODE(0x1) | SCLK_SOURCE_SELECT(0x1), - .link_config = CFG_DUMBMODE(0x2), + .link_config = CFG_DUMBMODE(0x2) + | CFG_GRA_SWAPRB(0x1), }, }; diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 2586c28..905efc8 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -1,12 +1,12 @@ if ARCH_MSM comment "Qualcomm MSM SoC Type" - depends on ARCH_MSM_DT + depends on (ARCH_MSM8X60 || ARCH_MSM8960) choice prompt "Qualcomm MSM SoC Type" default ARCH_MSM7X00A - depends on !ARCH_MSM_DT + depends on !(ARCH_MSM8X60 || ARCH_MSM8960) config ARCH_MSM7X00A bool "MSM7x00A / MSM7x01A" @@ -49,6 +49,7 @@ config ARCH_MSM8X60 select GPIO_MSM_V2 select HAVE_SMP select MSM_SCM if SMP + select USE_OF config ARCH_MSM8960 bool "MSM8960" @@ -57,11 +58,6 @@ config ARCH_MSM8960 select HAVE_SMP select GPIO_MSM_V2 select MSM_SCM if SMP - -config ARCH_MSM_DT - def_bool y - depends on (ARCH_MSM8X60 || ARCH_MSM8960) - select SPARSE_IRQ select USE_OF config MSM_HAS_DEBUG_UART_HS @@ -72,7 +68,6 @@ config MSM_SOC_REV_A config ARCH_MSM_ARM11 bool - config ARCH_MSM_SCORPION bool @@ -80,7 +75,6 @@ config MSM_VIC bool menu "Qualcomm MSM Board Type" - depends on !ARCH_MSM_DT config MACH_HALIBUT depends on ARCH_MSM @@ -128,7 +122,6 @@ config MSM_SMD config MSM_GPIOMUX bool - depends on !ARCH_MSM_DT help Support for MSM V1 TLMM GPIOMUX architecture. diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 7ed4c1b..d872634 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o -obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o +obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o +obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c new file mode 100644 index 0000000..c294689 --- /dev/null +++ b/arch/arm/mach-msm/board-dt-8660.c @@ -0,0 +1,48 @@ +/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/of.h> +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" + +static void __init msm8x60_init_late(void) +{ + smd_debugfs_init(); +} + +static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { + {} +}; + +static void __init msm8x60_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + msm_auxdata_lookup, NULL); +} + +static const char *msm8x60_fluid_match[] __initdata = { + "qcom,msm8660-fluid", + "qcom,msm8660-surf", + NULL +}; + +DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") + .smp = smp_ops(msm_smp_ops), + .init_machine = msm8x60_dt_init, + .init_late = msm8x60_init_late, + .dt_compat = msm8x60_fluid_match, +MACHINE_END diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt-8960.c index 16e6183..d4ca52c 100644 --- a/arch/arm/mach-msm/board-dt.c +++ b/arch/arm/mach-msm/board-dt-8960.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved. +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,7 +11,6 @@ */ #include <linux/init.h> -#include <linux/of.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> @@ -19,14 +18,18 @@ #include "common.h" -static const char * const msm_dt_match[] __initconst = { - "qcom,msm8660-fluid", - "qcom,msm8660-surf", +static void __init msm_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const msm8960_dt_match[] __initconst = { "qcom,msm8960-cdp", NULL }; -DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") +DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), - .dt_compat = msm_dt_match, + .init_machine = msm_dt_init, + .dt_compat = msm8960_dt_match, MACHINE_END diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h new file mode 100644 index 0000000..81ab2a6 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8960.h @@ -0,0 +1,277 @@ +/* Copyright (c) 2011 Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_MSM_IRQS_8960_H +#define __ASM_ARCH_MSM_IRQS_8960_H + +/* MSM ACPU Interrupt Numbers */ + +/* 0-15: STI/SGI (software triggered/generated interrupts) + 16-31: PPI (private peripheral interrupts) + 32+: SPI (shared peripheral interrupts) */ + +#define GIC_PPI_START 16 +#define GIC_SPI_START 32 + +#define INT_VGIC (GIC_PPI_START + 0) +#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) +#define INT_GP_TIMER_EXP (GIC_PPI_START + 2) +#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) +#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) +#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) +#define AVS_SVICINT (GIC_PPI_START + 6) +#define AVS_SVICINTSWDONE (GIC_PPI_START + 7) +#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) +#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) +#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10) +#define SC_AVSCPUXDOWN (GIC_PPI_START + 11) +#define SC_AVSCPUXUP (GIC_PPI_START + 12) +#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) +#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) +/* PPI 15 is unused */ + +#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) +#define SC_SICL2IRPTREQ (GIC_SPI_START + 1) +#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2) +#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3) +#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) +#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) +#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) +#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) +#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) +#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) +#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) +#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) +#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) +#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) +#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14) +#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15) +#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16) +#define SPDM_RT_1_IRQ (GIC_SPI_START + 17) +#define SPDM_DIAG_IRQ (GIC_SPI_START + 18) +#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) +#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) +#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) +#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) +#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) +#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) +#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) +#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) +#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27) +#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28) +#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) +#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) +#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) +#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) +#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) +#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) +#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35) +#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36) +#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) +#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) +#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) +#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) +#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) +#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) +#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) +#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) +#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) +#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) +#define VPE_IRQ (GIC_SPI_START + 47) +#define VFE_IRQ (GIC_SPI_START + 48) +#define VCODEC_IRQ (GIC_SPI_START + 49) +#define TV_ENC_IRQ (GIC_SPI_START + 50) +#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) +#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) +#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) +#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) +#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) +#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) +#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) +#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) +#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) +#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) +#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) +#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) +#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) +#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) +#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) +#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) +#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) +#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) +#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) +#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) +#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) +#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) +#define ROT_IRQ (GIC_SPI_START + 73) +#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) +#define MDP_IRQ (GIC_SPI_START + 75) +#define JPEGD_IRQ (GIC_SPI_START + 76) +#define JPEG_IRQ (GIC_SPI_START + 77) +#define MMSS_IMEM_IRQ (GIC_SPI_START + 78) +#define HDMI_IRQ (GIC_SPI_START + 79) +#define GFX3D_IRQ (GIC_SPI_START + 80) +#define GFX2D0_IRQ (GIC_SPI_START + 81) +#define DSI1_IRQ (GIC_SPI_START + 82) +#define CSI_1_IRQ (GIC_SPI_START + 83) +#define CSI_0_IRQ (GIC_SPI_START + 84) +#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) +#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) +#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) +#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) +#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) +#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) +#define TOP_IMEM_IRQ (GIC_SPI_START + 91) +#define FABRIC_SYS_IRQ (GIC_SPI_START + 92) +#define FABRIC_APPS_IRQ (GIC_SPI_START + 93) +#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) +#define SDC4_BAM_IRQ (GIC_SPI_START + 95) +#define SDC3_BAM_IRQ (GIC_SPI_START + 96) +#define SDC2_BAM_IRQ (GIC_SPI_START + 97) +#define SDC1_BAM_IRQ (GIC_SPI_START + 98) +#define FABRIC_SPS_IRQ (GIC_SPI_START + 99) +#define USB1_HS_IRQ (GIC_SPI_START + 100) +#define SDC4_IRQ_0 (GIC_SPI_START + 101) +#define SDC3_IRQ_0 (GIC_SPI_START + 102) +#define SDC2_IRQ_0 (GIC_SPI_START + 103) +#define SDC1_IRQ_0 (GIC_SPI_START + 104) +#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) +#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) +#define SPS_MTI_0 (GIC_SPI_START + 107) +#define SPS_MTI_1 (GIC_SPI_START + 108) +#define SPS_MTI_2 (GIC_SPI_START + 109) +#define SPS_MTI_3 (GIC_SPI_START + 110) +#define SPS_MTI_4 (GIC_SPI_START + 111) +#define SPS_MTI_5 (GIC_SPI_START + 112) +#define SPS_MTI_6 (GIC_SPI_START + 113) +#define SPS_MTI_7 (GIC_SPI_START + 114) +#define SPS_MTI_8 (GIC_SPI_START + 115) +#define SPS_MTI_9 (GIC_SPI_START + 116) +#define SPS_MTI_10 (GIC_SPI_START + 117) +#define SPS_MTI_11 (GIC_SPI_START + 118) +#define SPS_MTI_12 (GIC_SPI_START + 119) +#define SPS_MTI_13 (GIC_SPI_START + 120) +#define SPS_MTI_14 (GIC_SPI_START + 121) +#define SPS_MTI_15 (GIC_SPI_START + 122) +#define SPS_MTI_16 (GIC_SPI_START + 123) +#define SPS_MTI_17 (GIC_SPI_START + 124) +#define SPS_MTI_18 (GIC_SPI_START + 125) +#define SPS_MTI_19 (GIC_SPI_START + 126) +#define SPS_MTI_20 (GIC_SPI_START + 127) +#define SPS_MTI_21 (GIC_SPI_START + 128) +#define SPS_MTI_22 (GIC_SPI_START + 129) +#define SPS_MTI_23 (GIC_SPI_START + 130) +#define SPS_MTI_24 (GIC_SPI_START + 131) +#define SPS_MTI_25 (GIC_SPI_START + 132) +#define SPS_MTI_26 (GIC_SPI_START + 133) +#define SPS_MTI_27 (GIC_SPI_START + 134) +#define SPS_MTI_28 (GIC_SPI_START + 135) +#define SPS_MTI_29 (GIC_SPI_START + 136) +#define SPS_MTI_30 (GIC_SPI_START + 137) +#define SPS_MTI_31 (GIC_SPI_START + 138) +#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139) +#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140) +#define USB2_IRQ (GIC_SPI_START + 141) +#define USB1_IRQ (GIC_SPI_START + 142) +#define TSSC_SSBI_IRQ (GIC_SPI_START + 143) +#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) +#define TSSC_PENUP_IRQ (GIC_SPI_START + 145) +#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146) +#define GSBI1_QUP_IRQ (GIC_SPI_START + 147) +#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148) +#define GSBI2_QUP_IRQ (GIC_SPI_START + 149) +#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) +#define GSBI3_QUP_IRQ (GIC_SPI_START + 151) +#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) +#define GSBI4_QUP_IRQ (GIC_SPI_START + 153) +#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) +#define GSBI5_QUP_IRQ (GIC_SPI_START + 155) +#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156) +#define GSBI6_QUP_IRQ (GIC_SPI_START + 157) +#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158) +#define GSBI7_QUP_IRQ (GIC_SPI_START + 159) +#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160) +#define GSBI8_QUP_IRQ (GIC_SPI_START + 161) +#define TSIF_TSPP_IRQ (GIC_SPI_START + 162) +#define TSIF_BAM_IRQ (GIC_SPI_START + 163) +#define TSIF2_IRQ (GIC_SPI_START + 164) +#define TSIF1_IRQ (GIC_SPI_START + 165) +#define DSI2_IRQ (GIC_SPI_START + 166) +#define ISPIF_IRQ (GIC_SPI_START + 167) +#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) +#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) +#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170) +#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171) +#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172) +#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173) +#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) +#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) +#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) +#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) +#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) +#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) +#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) +#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) +#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) +#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) +#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) +#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) +#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186) +#define SDC5_BAM_IRQ (GIC_SPI_START + 187) +#define SDC5_IRQ_0 (GIC_SPI_START + 188) +#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189) +#define GSBI9_QUP_IRQ (GIC_SPI_START + 190) +#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191) +#define GSBI10_QUP_IRQ (GIC_SPI_START + 192) +#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193) +#define GSBI11_QUP_IRQ (GIC_SPI_START + 194) +#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195) +#define GSBI12_QUP_IRQ (GIC_SPI_START + 196) +#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197) +#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198) +#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199) +#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200) +#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201) +#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202) +#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203) +#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204) +#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205) +#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206) +#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207) +#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208) +#define A2_BAM_IRQ (GIC_SPI_START + 209) +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) +#define GFX2D1_IRQ (GIC_SPI_START + 212) +#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213) +#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214) +#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215) +#define QDSS_ETB_IRQ (GIC_SPI_START + 216) +#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217) +#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) +#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) +#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) +#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) +#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) +#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) +#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) +#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225) +#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226) + +/* For now, use the maximum number of interrupts until a pending GIC issue + * is sorted out */ +#define NR_MSM_IRQS 1020 +#define NR_BOARD_IRQS 0 +#define NR_GPIO_IRQS 0 + +#endif + diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h new file mode 100644 index 0000000..f65841c --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -0,0 +1,258 @@ +/* Copyright (c) 2010 Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_IRQS_8X60_H +#define __ASM_ARCH_MSM_IRQS_8X60_H + +/* MSM ACPU Interrupt Numbers */ + +/* 0-15: STI/SGI (software triggered/generated interrupts) + * 16-31: PPI (private peripheral interrupts) + * 32+: SPI (shared peripheral interrupts) + */ + +#define GIC_PPI_START 16 +#define GIC_SPI_START 32 + +#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0) +#define INT_GP_TIMER_EXP (GIC_PPI_START + 1) +#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2) +#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3) +#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4) +#define AVS_SVICINT (GIC_PPI_START + 5) +#define AVS_SVICINTSWDONE (GIC_PPI_START + 6) +#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7) +#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8) +#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9) +#define SC_AVSCPUXDOWN (GIC_PPI_START + 10) +#define SC_AVSCPUXUP (GIC_PPI_START + 11) +#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12) +/* PPI 13 to 15 are unused */ + + +#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) +#define SC_SICL2IRPTREQ (GIC_SPI_START + 1) +#define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2) +#define NC (GIC_SPI_START + 3) +#define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) +#define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) +#define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) +#define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) +#define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) +#define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) +#define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) +#define TLMM_SCSS_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) +#define TLMM_SCSS_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) +#define TLMM_SCSS_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) +#define PM8058_SEC_IRQ_N (GIC_SPI_START + 14) +#define PM8901_SEC_IRQ_N (GIC_SPI_START + 15) +#define TLMM_SCSS_SUMMARY_IRQ (GIC_SPI_START + 16) +#define SPDM_RT_1_IRQ (GIC_SPI_START + 17) +#define SPDM_DIAG_IRQ (GIC_SPI_START + 18) +#define RPM_SCSS_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) +#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) +#define RPM_SCSS_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) +#define RPM_SCSS_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) +#define RPM_SCSS_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) +#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) +#define RPM_SCSS_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) +#define RPM_SCSS_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) +#define SSBI2_2_SC_CPU0_SECURE_INT (GIC_SPI_START + 27) +#define SSBI2_2_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 28) +#define SSBI2_1_SC_CPU0_SECURE_INT (GIC_SPI_START + 29) +#define SSBI2_1_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 30) +#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) +#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) +#define MARM_FIQ (GIC_SPI_START + 33) +#define MARM_IRQ (GIC_SPI_START + 34) +#define MARM_L2CC_IRQ (GIC_SPI_START + 35) +#define MARM_WDOG_EXPIRED (GIC_SPI_START + 36) +#define MARM_SCSS_GP_IRQ_0 (GIC_SPI_START + 37) +#define MARM_SCSS_GP_IRQ_1 (GIC_SPI_START + 38) +#define MARM_SCSS_GP_IRQ_2 (GIC_SPI_START + 39) +#define MARM_SCSS_GP_IRQ_3 (GIC_SPI_START + 40) +#define MARM_SCSS_GP_IRQ_4 (GIC_SPI_START + 41) +#define MARM_SCSS_GP_IRQ_5 (GIC_SPI_START + 42) +#define MARM_SCSS_GP_IRQ_6 (GIC_SPI_START + 43) +#define MARM_SCSS_GP_IRQ_7 (GIC_SPI_START + 44) +#define MARM_SCSS_GP_IRQ_8 (GIC_SPI_START + 45) +#define MARM_SCSS_GP_IRQ_9 (GIC_SPI_START + 46) +#define VPE_IRQ (GIC_SPI_START + 47) +#define VFE_IRQ (GIC_SPI_START + 48) +#define VCODEC_IRQ (GIC_SPI_START + 49) +#define TV_ENC_IRQ (GIC_SPI_START + 50) +#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) +#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) +#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) +#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) +#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) +#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) +#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) +#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) +#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) +#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) +#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) +#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) +#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) +#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) +#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) +#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) +#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) +#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) +#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) +#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) +#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) +#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) +#define ROT_IRQ (GIC_SPI_START + 73) +#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) +#define MDP_IRQ (GIC_SPI_START + 75) +#define JPEGD_IRQ (GIC_SPI_START + 76) +#define JPEG_IRQ (GIC_SPI_START + 77) +#define MMSS_IMEM_IRQ (GIC_SPI_START + 78) +#define HDMI_IRQ (GIC_SPI_START + 79) +#define GFX3D_IRQ (GIC_SPI_START + 80) +#define GFX2D0_IRQ (GIC_SPI_START + 81) +#define DSI_IRQ (GIC_SPI_START + 82) +#define CSI_1_IRQ (GIC_SPI_START + 83) +#define CSI_0_IRQ (GIC_SPI_START + 84) +#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) +#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) +#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) +#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) +#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) +#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) +#define TOP_IMEM_IRQ (GIC_SPI_START + 91) +#define FABRIC_SYS_IRQ (GIC_SPI_START + 92) +#define FABRIC_APPS_IRQ (GIC_SPI_START + 93) +#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) +#define SDC4_BAM_IRQ (GIC_SPI_START + 95) +#define SDC3_BAM_IRQ (GIC_SPI_START + 96) +#define SDC2_BAM_IRQ (GIC_SPI_START + 97) +#define SDC1_BAM_IRQ (GIC_SPI_START + 98) +#define FABRIC_SPS_IRQ (GIC_SPI_START + 99) +#define USB1_HS_IRQ (GIC_SPI_START + 100) +#define SDC4_IRQ_0 (GIC_SPI_START + 101) +#define SDC3_IRQ_0 (GIC_SPI_START + 102) +#define SDC2_IRQ_0 (GIC_SPI_START + 103) +#define SDC1_IRQ_0 (GIC_SPI_START + 104) +#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) +#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) +#define SPS_MTI_0 (GIC_SPI_START + 107) +#define SPS_MTI_1 (GIC_SPI_START + 108) +#define SPS_MTI_2 (GIC_SPI_START + 109) +#define SPS_MTI_3 (GIC_SPI_START + 110) +#define SPS_MTI_4 (GIC_SPI_START + 111) +#define SPS_MTI_5 (GIC_SPI_START + 112) +#define SPS_MTI_6 (GIC_SPI_START + 113) +#define SPS_MTI_7 (GIC_SPI_START + 114) +#define SPS_MTI_8 (GIC_SPI_START + 115) +#define SPS_MTI_9 (GIC_SPI_START + 116) +#define SPS_MTI_10 (GIC_SPI_START + 117) +#define SPS_MTI_11 (GIC_SPI_START + 118) +#define SPS_MTI_12 (GIC_SPI_START + 119) +#define SPS_MTI_13 (GIC_SPI_START + 120) +#define SPS_MTI_14 (GIC_SPI_START + 121) +#define SPS_MTI_15 (GIC_SPI_START + 122) +#define SPS_MTI_16 (GIC_SPI_START + 123) +#define SPS_MTI_17 (GIC_SPI_START + 124) +#define SPS_MTI_18 (GIC_SPI_START + 125) +#define SPS_MTI_19 (GIC_SPI_START + 126) +#define SPS_MTI_20 (GIC_SPI_START + 127) +#define SPS_MTI_21 (GIC_SPI_START + 128) +#define SPS_MTI_22 (GIC_SPI_START + 129) +#define SPS_MTI_23 (GIC_SPI_START + 130) +#define SPS_MTI_24 (GIC_SPI_START + 131) +#define SPS_MTI_25 (GIC_SPI_START + 132) +#define SPS_MTI_26 (GIC_SPI_START + 133) +#define SPS_MTI_27 (GIC_SPI_START + 134) +#define SPS_MTI_28 (GIC_SPI_START + 135) +#define SPS_MTI_29 (GIC_SPI_START + 136) +#define SPS_MTI_30 (GIC_SPI_START + 137) +#define SPS_MTI_31 (GIC_SPI_START + 138) +#define UXMC_EBI2_WR_ER_DONE_IRQ (GIC_SPI_START + 139) +#define UXMC_EBI2_OP_DONE_IRQ (GIC_SPI_START + 140) +#define USB2_IRQ (GIC_SPI_START + 141) +#define USB1_IRQ (GIC_SPI_START + 142) +#define TSSC_SSBI_IRQ (GIC_SPI_START + 143) +#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) +#define TSSC_PENUP_IRQ (GIC_SPI_START + 145) +#define INT_UART1DM_IRQ (GIC_SPI_START + 146) +#define GSBI1_QUP_IRQ (GIC_SPI_START + 147) +#define INT_UART2DM_IRQ (GIC_SPI_START + 148) +#define GSBI2_QUP_IRQ (GIC_SPI_START + 149) +#define INT_UART3DM_IRQ (GIC_SPI_START + 150) +#define GSBI3_QUP_IRQ (GIC_SPI_START + 151) +#define INT_UART4DM_IRQ (GIC_SPI_START + 152) +#define GSBI4_QUP_IRQ (GIC_SPI_START + 153) +#define INT_UART5DM_IRQ (GIC_SPI_START + 154) +#define GSBI5_QUP_IRQ (GIC_SPI_START + 155) +#define INT_UART6DM_IRQ (GIC_SPI_START + 156) +#define GSBI6_QUP_IRQ (GIC_SPI_START + 157) +#define INT_UART7DM_IRQ (GIC_SPI_START + 158) +#define GSBI7_QUP_IRQ (GIC_SPI_START + 159) +#define INT_UART8DM_IRQ (GIC_SPI_START + 160) +#define GSBI8_QUP_IRQ (GIC_SPI_START + 161) +#define TSIF_TSPP_IRQ (GIC_SPI_START + 162) +#define TSIF_BAM_IRQ (GIC_SPI_START + 163) +#define TSIF2_IRQ (GIC_SPI_START + 164) +#define TSIF1_IRQ (GIC_SPI_START + 165) +#define INT_ADM1_MASTER (GIC_SPI_START + 166) +#define INT_ADM1_AARM (GIC_SPI_START + 167) +#define INT_ADM1_SD2 (GIC_SPI_START + 168) +#define INT_ADM1_SD3 (GIC_SPI_START + 169) +#define INT_ADM0_MASTER (GIC_SPI_START + 170) +#define INT_ADM0_AARM (GIC_SPI_START + 171) +#define INT_ADM0_SD2 (GIC_SPI_START + 172) +#define INT_ADM0_SD3 (GIC_SPI_START + 173) +#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) +#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) +#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) +#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) +#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) +#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) +#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) +#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) +#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) +#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) +#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) +#define HSDDRX_SMICH0_IRQ (GIC_SPI_START + 185) +#define HSDDRX_EBI1_IRQ (GIC_SPI_START + 186) +#define SDC5_BAM_IRQ (GIC_SPI_START + 187) +#define SDC5_IRQ_0 (GIC_SPI_START + 188) +#define INT_UART9DM_IRQ (GIC_SPI_START + 189) +#define GSBI9_QUP_IRQ (GIC_SPI_START + 190) +#define INT_UART10DM_IRQ (GIC_SPI_START + 191) +#define GSBI10_QUP_IRQ (GIC_SPI_START + 192) +#define INT_UART11DM_IRQ (GIC_SPI_START + 193) +#define GSBI11_QUP_IRQ (GIC_SPI_START + 194) +#define INT_UART12DM_IRQ (GIC_SPI_START + 195) +#define GSBI12_QUP_IRQ (GIC_SPI_START + 196) + +/*SPI 197 to 209 arent used in 8x60*/ +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) + +/*SPI 212 to 216 arent used in 8x60*/ +#define SMPSS_SPARE_1 (GIC_SPI_START + 217) +#define SMPSS_SPARE_2 (GIC_SPI_START + 218) +#define SMPSS_SPARE_3 (GIC_SPI_START + 219) +#define SMPSS_SPARE_4 (GIC_SPI_START + 220) +#define SMPSS_SPARE_5 (GIC_SPI_START + 221) +#define SMPSS_SPARE_6 (GIC_SPI_START + 222) +#define SMPSS_SPARE_7 (GIC_SPI_START + 223) + +#define NR_GPIO_IRQS 173 +#define NR_MSM_IRQS 256 +#define NR_BOARD_IRQS 0 + +#endif diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 164d355..3cd78b1 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h @@ -24,6 +24,11 @@ #elif defined(CONFIG_ARCH_QSD8X50) #include "irqs-8x50.h" #include "sirc.h" +#elif defined(CONFIG_ARCH_MSM8X60) +#include "irqs-8x60.h" +#elif defined(CONFIG_ARCH_MSM8960) +/* TODO: Make these not generic. */ +#include "irqs-8960.h" #elif defined(CONFIG_ARCH_MSM_ARM11) #include "irqs-7x00.h" #else diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 1e9c338..696fb73 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -274,6 +274,7 @@ static void __init msm_dt_timer_init(struct device_node *np) pr_err("Unknown frequency\n"); return; } + of_node_put(np); event_base = base + 0x4; sts_base = base + 0x88; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 5e269d7..9eb63d7 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,6 +1,5 @@ config ARCH_MVEBU bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 - select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index ee7598f..5476669 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -20,8 +20,6 @@ #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4 -#include <asm/assembler.h> - .text /* * r0: Coherency fabric base register address @@ -31,7 +29,6 @@ ENTRY(ll_set_cpu_coherent) /* Create bit by cpu index */ mov r3, #(1 << 24) lsl r1, r3, r1 -ARM_BE8(rev r1, r1) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index 3dd80df..8a1b0c9 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -21,16 +21,12 @@ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/assembler.h> - /* * Armada XP specific entry point for secondary CPUs. * We add the CPU to the coherency fabric and then jump to secondary * startup */ ENTRY(armada_xp_secondary_startup) - ARM_BE8(setend be ) @ go BE8 if entered LE - /* Get coherency fabric base physical address */ adr r0, 1f ldr r1, [r0] diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 1dc5acd..98f6e2a 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -13,6 +13,8 @@ #include <linux/clk.h> #include <linux/clk/mxs.h> #include <linux/clkdev.h> +#include <linux/clocksource.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/gpio.h> @@ -330,11 +332,6 @@ static void __init crystalfontz_init(void) update_fec_mac_prop(OUI_CRYSTALFONTZ); } -static void __init m28cu3_init(void) -{ - update_fec_mac_prop(OUI_DENX); -} - static const char __init *mxs_get_soc_id(void) { struct device_node *np; @@ -462,8 +459,6 @@ static void __init mxs_machine_init(void) apx4devkit_init(); else if (of_machine_is_compatible("crystalfontz,cfa10036")) crystalfontz_init(); - else if (of_machine_is_compatible("msr,m28cu3")) - m28cu3_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); @@ -495,6 +490,16 @@ static void mxs_restart(enum reboot_mode mode, const char *cmd) soft_restart(0); } +static void __init mxs_timer_init(void) +{ + if (of_machine_is_compatible("fsl,imx23")) + mx23_clocks_init(); + else + mx28_clocks_init(); + of_clk_init(NULL); + clocksource_of_init(); +} + static const char *mxs_dt_compat[] __initdata = { "fsl,imx28", "fsl,imx23", @@ -503,6 +508,7 @@ static const char *mxs_dt_compat[] __initdata = { DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") .handle_irq = icoll_handle_irq, + .init_time = mxs_timer_init, .init_machine = mxs_machine_init, .init_late = mxs_pm_init, .dt_compat = mxs_dt_compat, diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index cce2c9d..13e0df9 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -25,11 +25,15 @@ #include <linux/slab.h> #include <linux/irq.h> #include <linux/dma-mapping.h> +#include <linux/platform_data/clk-nomadik.h> +#include <linux/clocksource.h> #include <linux/of_irq.h> #include <linux/of_gpio.h> #include <linux/of_address.h> #include <linux/of_platform.h> +#include <linux/mtd/fsmc.h> #include <linux/gpio.h> +#include <linux/amba/mmci.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -109,6 +113,50 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd) writel(1, srcbase + 0x18); } +/* Initial value for SRC control register: all timers use MXTAL/8 source */ +#define SRC_CR_INIT_MASK 0x00007fff +#define SRC_CR_INIT_VAL 0x2aaa8000 + +static void __init cpu8815_timer_init_of(void) +{ + struct device_node *mtu; + void __iomem *base; + int irq; + u32 src_cr; + + /* We need this to be up now */ + nomadik_clk_init(); + + mtu = of_find_node_by_path("/mtu@101e2000"); + if (!mtu) + return; + base = of_iomap(mtu, 0); + if (WARN_ON(!base)) + return; + irq = irq_of_parse_and_map(mtu, 0); + + pr_info("Remapped MTU @ %p, irq: %d\n", base, irq); + + /* Configure timer sources in "system reset controller" ctrl reg */ + src_cr = readl(base); + src_cr &= SRC_CR_INIT_MASK; + src_cr |= SRC_CR_INIT_VAL; + writel(src_cr, base); + + clocksource_of_init(); +} + +static struct fsmc_nand_timings cpu8815_nand_timings = { + .thiz = 0, + .thold = 0x10, + .twait = 0x0A, + .tset = 0, +}; + +static struct fsmc_nand_platform_data cpu8815_nand_data = { + .nand_timings = &cpu8815_nand_timings, +}; + /* * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects * to simply request an IRQ passed as a resource. So the GPIO pin needs @@ -142,6 +190,15 @@ static int __init cpu8815_eth_init(void) device_initcall(cpu8815_eth_init); /* + * TODO: + * cannot be set from device tree, convert to a proper DT + * binding. + */ +static struct mmci_platform_data mmcsd_plat_data = { + .ocr_mask = MMC_VDD_29_30, +}; + +/* * This GPIO pin turns on a line that is used to detect card insertion * on this board. */ @@ -175,13 +232,24 @@ static int __init cpu8815_mmcsd_init(void) } device_initcall(cpu8815_mmcsd_init); + +/* These are mostly to get the right device names for the clock lookups */ +static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE, + NULL, &cpu8815_nand_data), + OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE, + NULL, &mmcsd_plat_data), + { /* sentinel */ }, +}; + static void __init cpu8815_init_of(void) { #ifdef CONFIG_CACHE_L2X0 /* At full speed latency must be >=2, so 0x249 in low bits */ l2x0_of_init(0x00730249, 0xfe000fff); #endif - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + cpu8815_auxdata_lookup, NULL); } static const char * cpu8815_board_compat[] = { @@ -191,6 +259,7 @@ static const char * cpu8815_board_compat[] = { DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815") .map_io = cpu8815_map_io, + .init_time = cpu8815_timer_init_of, .init_machine = cpu8815_init_of, .restart = cpu8815_restart, .dt_compat = cpu8815_board_compat, diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c index 4b2ed2e..99e2609 100644 --- a/arch/arm/mach-nspire/nspire.c +++ b/arch/arm/mach-nspire/nspire.c @@ -14,9 +14,11 @@ #include <linux/of_platform.h> #include <linux/irqchip.h> #include <linux/irqchip/arm-vic.h> +#include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/amba/bus.h> #include <linux/amba/clcd.h> +#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -63,6 +65,12 @@ static void __init nspire_init(void) nspire_auxdata, NULL); } +static void __init nspire_init_time(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + static void nspire_restart(char mode, const char *cmd) { void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K); @@ -75,6 +83,7 @@ static void nspire_restart(char mode, const char *cmd) DT_MACHINE_START(NSPIRE, "TI-NSPIRE") .dt_compat = nspire_dt_match, .map_io = nspire_map_io, + .init_time = nspire_init_time, .init_machine = nspire_init, .restart = nspire_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index d68909b..a7ce692 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -300,7 +300,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = { #ifdef CONFIG_OMAP_OSK_MISTRAL #include <linux/input.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index 732f8ee..abec019 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -46,9 +46,6 @@ static inline void omap7xx_map_io(void) void omap1510_fpga_init_irq(void); void omap15xx_map_io(void); #else -static inline void omap1510_fpga_init_irq(void) -{ -} static inline void omap15xx_map_io(void) { } diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 3c0e422..8bd71b2 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -135,7 +135,8 @@ static struct irq_chip omap_fpga_irq = { * mask_ack routine for all of the FPGA interrupts has been changed from * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt * being serviced is left unmasked. We can do this because the FPGA cascade - * interrupt is run with all interrupts masked. + * interrupt is installed with the IRQF_DISABLED flag, which leaves all + * interrupts masked at the CPU while an FPGA interrupt handler executes. * * Limited testing indicates that this workaround appears to be effective * for the smc9194 Ethernet driver used on the Innovator. It should work diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index 312a092..02b3eb2 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c @@ -25,7 +25,7 @@ #define OMAP1510_GPIO_BASE 0xFFFCE000 /* gpio1 */ -static struct resource omap15xx_mpu_gpio_resources[] = { +static struct __initdata resource omap15xx_mpu_gpio_resources[] = { { .start = OMAP1_MPUIO_VBASE, .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, @@ -48,7 +48,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = { .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE, }; -static struct omap_gpio_platform_data omap15xx_mpu_gpio_config = { +static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { .is_mpuio = true, .bank_width = 16, .bank_stride = 1, @@ -66,7 +66,7 @@ static struct platform_device omap15xx_mpu_gpio = { }; /* gpio2 */ -static struct resource omap15xx_gpio_resources[] = { +static struct __initdata resource omap15xx_gpio_resources[] = { { .start = OMAP1510_GPIO_BASE, .end = OMAP1510_GPIO_BASE + SZ_2K - 1, @@ -90,7 +90,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = { .pinctrl = OMAP1510_GPIO_PIN_CONTROL, }; -static struct omap_gpio_platform_data omap15xx_gpio_config = { +static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { .bank_width = 16, .regs = &omap15xx_gpio_regs, }; diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 6e6ec93..b9952a2 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -31,7 +31,7 @@ #define SYSCONFIG_WORD 0x14 /* mpu gpio */ -static struct resource omap16xx_mpu_gpio_resources[] = { +static struct __initdata resource omap16xx_mpu_gpio_resources[] = { { .start = OMAP1_MPUIO_VBASE, .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, @@ -54,7 +54,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = { .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE, }; -static struct omap_gpio_platform_data omap16xx_mpu_gpio_config = { +static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { .is_mpuio = true, .bank_width = 16, .bank_stride = 1, @@ -72,7 +72,7 @@ static struct platform_device omap16xx_mpu_gpio = { }; /* gpio1 */ -static struct resource omap16xx_gpio1_resources[] = { +static struct __initdata resource omap16xx_gpio1_resources[] = { { .start = OMAP1610_GPIO1_BASE, .end = OMAP1610_GPIO1_BASE + SZ_2K - 1, @@ -100,7 +100,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = { .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2, }; -static struct omap_gpio_platform_data omap16xx_gpio1_config = { +static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { .bank_width = 16, .regs = &omap16xx_gpio_regs, }; @@ -116,7 +116,7 @@ static struct platform_device omap16xx_gpio1 = { }; /* gpio2 */ -static struct resource omap16xx_gpio2_resources[] = { +static struct __initdata resource omap16xx_gpio2_resources[] = { { .start = OMAP1610_GPIO2_BASE, .end = OMAP1610_GPIO2_BASE + SZ_2K - 1, @@ -128,7 +128,7 @@ static struct resource omap16xx_gpio2_resources[] = { }, }; -static struct omap_gpio_platform_data omap16xx_gpio2_config = { +static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { .bank_width = 16, .regs = &omap16xx_gpio_regs, }; @@ -144,7 +144,7 @@ static struct platform_device omap16xx_gpio2 = { }; /* gpio3 */ -static struct resource omap16xx_gpio3_resources[] = { +static struct __initdata resource omap16xx_gpio3_resources[] = { { .start = OMAP1610_GPIO3_BASE, .end = OMAP1610_GPIO3_BASE + SZ_2K - 1, @@ -156,7 +156,7 @@ static struct resource omap16xx_gpio3_resources[] = { }, }; -static struct omap_gpio_platform_data omap16xx_gpio3_config = { +static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { .bank_width = 16, .regs = &omap16xx_gpio_regs, }; @@ -172,7 +172,7 @@ static struct platform_device omap16xx_gpio3 = { }; /* gpio4 */ -static struct resource omap16xx_gpio4_resources[] = { +static struct __initdata resource omap16xx_gpio4_resources[] = { { .start = OMAP1610_GPIO4_BASE, .end = OMAP1610_GPIO4_BASE + SZ_2K - 1, @@ -184,7 +184,7 @@ static struct resource omap16xx_gpio4_resources[] = { }, }; -static struct omap_gpio_platform_data omap16xx_gpio4_config = { +static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { .bank_width = 16, .regs = &omap16xx_gpio_regs, }; @@ -199,7 +199,7 @@ static struct platform_device omap16xx_gpio4 = { .resource = omap16xx_gpio4_resources, }; -static struct platform_device *omap16xx_gpio_dev[] __initdata = { +static struct __initdata platform_device * omap16xx_gpio_dev[] = { &omap16xx_mpu_gpio, &omap16xx_gpio1, &omap16xx_gpio2, diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index 4612d25..f5819b2 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c @@ -30,7 +30,7 @@ #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE /* mpu gpio */ -static struct resource omap7xx_mpu_gpio_resources[] = { +static struct __initdata resource omap7xx_mpu_gpio_resources[] = { { .start = OMAP1_MPUIO_VBASE, .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, @@ -53,7 +53,7 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = { .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1, }; -static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = { +static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { .is_mpuio = true, .bank_width = 16, .bank_stride = 2, @@ -71,7 +71,7 @@ static struct platform_device omap7xx_mpu_gpio = { }; /* gpio1 */ -static struct resource omap7xx_gpio1_resources[] = { +static struct __initdata resource omap7xx_gpio1_resources[] = { { .start = OMAP7XX_GPIO1_BASE, .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1, @@ -94,7 +94,7 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = { .irqctrl = OMAP7XX_GPIO_INT_CONTROL, }; -static struct omap_gpio_platform_data omap7xx_gpio1_config = { +static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { .bank_width = 32, .regs = &omap7xx_gpio_regs, }; @@ -110,7 +110,7 @@ static struct platform_device omap7xx_gpio1 = { }; /* gpio2 */ -static struct resource omap7xx_gpio2_resources[] = { +static struct __initdata resource omap7xx_gpio2_resources[] = { { .start = OMAP7XX_GPIO2_BASE, .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1, @@ -122,7 +122,7 @@ static struct resource omap7xx_gpio2_resources[] = { }, }; -static struct omap_gpio_platform_data omap7xx_gpio2_config = { +static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { .bank_width = 32, .regs = &omap7xx_gpio_regs, }; @@ -138,7 +138,7 @@ static struct platform_device omap7xx_gpio2 = { }; /* gpio3 */ -static struct resource omap7xx_gpio3_resources[] = { +static struct __initdata resource omap7xx_gpio3_resources[] = { { .start = OMAP7XX_GPIO3_BASE, .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1, @@ -150,7 +150,7 @@ static struct resource omap7xx_gpio3_resources[] = { }, }; -static struct omap_gpio_platform_data omap7xx_gpio3_config = { +static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { .bank_width = 32, .regs = &omap7xx_gpio_regs, }; @@ -166,7 +166,7 @@ static struct platform_device omap7xx_gpio3 = { }; /* gpio4 */ -static struct resource omap7xx_gpio4_resources[] = { +static struct __initdata resource omap7xx_gpio4_resources[] = { { .start = OMAP7XX_GPIO4_BASE, .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1, @@ -178,7 +178,7 @@ static struct resource omap7xx_gpio4_resources[] = { }, }; -static struct omap_gpio_platform_data omap7xx_gpio4_config = { +static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { .bank_width = 32, .regs = &omap7xx_gpio_regs, }; @@ -194,7 +194,7 @@ static struct platform_device omap7xx_gpio4 = { }; /* gpio5 */ -static struct resource omap7xx_gpio5_resources[] = { +static struct __initdata resource omap7xx_gpio5_resources[] = { { .start = OMAP7XX_GPIO5_BASE, .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1, @@ -206,7 +206,7 @@ static struct resource omap7xx_gpio5_resources[] = { }, }; -static struct omap_gpio_platform_data omap7xx_gpio5_config = { +static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { .bank_width = 32, .regs = &omap7xx_gpio_regs, }; @@ -222,7 +222,7 @@ static struct platform_device omap7xx_gpio5 = { }; /* gpio6 */ -static struct resource omap7xx_gpio6_resources[] = { +static struct __initdata resource omap7xx_gpio6_resources[] = { { .start = OMAP7XX_GPIO6_BASE, .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1, @@ -234,7 +234,7 @@ static struct resource omap7xx_gpio6_resources[] = { }, }; -static struct omap_gpio_platform_data omap7xx_gpio6_config = { +static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { .bank_width = 32, .regs = &omap7xx_gpio_regs, }; @@ -249,7 +249,7 @@ static struct platform_device omap7xx_gpio6 = { .resource = omap7xx_gpio6_resources, }; -static struct platform_device *omap7xx_gpio_dev[] __initdata = { +static struct __initdata platform_device * omap7xx_gpio_dev[] = { &omap7xx_mpu_gpio, &omap7xx_gpio1, &omap7xx_gpio2, diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 40a1ae3..358b82c 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -628,6 +628,7 @@ static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) static struct irqaction omap_wakeup_irq = { .name = "peripheral wakeup", + .flags = IRQF_DISABLED, .handler = omap_wakeup_interrupt }; diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 6b5f298..80603d2 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -160,7 +160,7 @@ static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id) static struct irqaction omap_mpu_timer1_irq = { .name = "mpu_timer1", - .flags = IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = omap_mpu_timer1_interrupt, }; diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 107e7ab..0b74246 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -156,7 +156,7 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) static struct irqaction omap_32k_timer_irq = { .name = "32KHz timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = omap_32k_timer_interrupt, }; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dc21df1..b5fb5f7 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -8,6 +8,7 @@ config ARCH_OMAP2 select CPU_V6 select MULTI_IRQ_HANDLER select SOC_HAS_OMAP2_SDRC + select COMMON_CLK config ARCH_OMAP3 bool "TI OMAP3" @@ -21,6 +22,7 @@ config ARCH_OMAP3 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select SOC_HAS_OMAP2_SDRC + select COMMON_CLK select USB_ARCH_HAS_EHCI if USB_SUPPORT config ARCH_OMAP4 @@ -43,6 +45,7 @@ config ARCH_OMAP4 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT + select COMMON_CLK select ARM_ERRATA_754322 select ARM_ERRATA_775420 @@ -56,6 +59,7 @@ config SOC_OMAP5 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP + select COMMON_CLK select HAVE_ARM_ARCH_TIMER select ARM_ERRATA_798181 if SMP @@ -66,6 +70,7 @@ config SOC_AM33XX select ARM_CPU_SUSPEND if PM select CPU_V7 select MULTI_IRQ_HANDLER + select COMMON_CLK config SOC_AM43XX bool "TI AM43x" @@ -74,6 +79,7 @@ config SOC_AM43XX select ARCH_OMAP2PLUS select MULTI_IRQ_HANDLER select ARM_GIC + select COMMON_CLK select MACH_OMAP_GENERIC config ARCH_OMAP2PLUS @@ -83,11 +89,11 @@ config ARCH_OMAP2PLUS select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP select ARCH_REQUIRE_GPIOLIB + select CLKDEV_LOOKUP select CLKSRC_MMIO - select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select MACH_OMAP_GENERIC + select HAVE_CLK select OMAP_DM_TIMER select PINCTRL select PROC_DEVICETREE if PROC_FS @@ -181,11 +187,16 @@ config OMAP_PACKAGE_CUS config OMAP_PACKAGE_CBP bool -comment "OMAP Legacy Platform Data Board Type" +comment "OMAP Board Type" depends on ARCH_OMAP2PLUS config MACH_OMAP_GENERIC - bool + bool "Generic OMAP2+ board" + depends on ARCH_OMAP2PLUS + default y + help + Support for generic TI OMAP2+ boards using Flattened Device Tree. + More information at Documentation/devicetree config MACH_OMAP2_TUSB6010 bool @@ -249,6 +260,12 @@ config MACH_OVERO default y select OMAP_PACKAGE_CBB +config MACH_OMAP3EVM + bool "OMAP 3530 EVM board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 @@ -297,12 +314,33 @@ config MACH_NOKIA_N8X0 select MACH_NOKIA_N810_WIMAX select OMAP_PACKAGE_ZAC +config MACH_NOKIA_RM680 + bool "Nokia N950 (RM-680) / N9 (RM-696) phones" + depends on ARCH_OMAP3 + default y + select MACH_NOKIA_RM696 + select OMAP_PACKAGE_CBB + config MACH_NOKIA_RX51 bool "Nokia N900 (RX-51) phone" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB +config MACH_OMAP_ZOOM2 + bool "OMAP3 Zoom2 board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + +config MACH_OMAP_ZOOM3 + bool "OMAP3630 Zoom3 board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBP + select REGULATOR_FIXED_VOLTAGE if REGULATOR + config MACH_CM_T35 bool "CompuLab CM-T35/CM-T3730 modules" depends on ARCH_OMAP3 @@ -319,12 +357,31 @@ config MACH_CM_T3517 config MACH_CM_T3730 bool +config MACH_IGEP0020 + bool "IGEP v2 board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + +config MACH_IGEP0030 + bool "IGEP OMAP3 module" + depends on ARCH_OMAP3 + default y + select MACH_IGEP0020 + select OMAP_PACKAGE_CBB + config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CUS +config MACH_OMAP_3630SDP + bool "OMAP3630 SDP board" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBP + config MACH_TI8168EVM bool "TI8168 Evaluation Module" depends on SOC_TI81XX diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index adcef40..afb457c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -8,7 +8,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ # Common support obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ - omap_device.o sram.o drm.o + omap_device.o sram.o omap-2-3-common = irq.o hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ @@ -19,11 +19,11 @@ secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) -obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) -obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -40,7 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) -obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o +obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -112,13 +112,13 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o +obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ prcm_mpu44xx.o prminst44xx.o \ vc44xx_data.o vp44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) -obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -146,7 +146,6 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) -obj-$(CONFIG_SOC_AM43XX) += powerdomains43xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) @@ -166,7 +165,6 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) -obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) @@ -212,11 +210,6 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o -obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o -obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o -obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o -obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o -obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o @@ -235,8 +228,12 @@ endif # OMAP2420 MSDI controller integration support ("MMC") obj-$(CONFIG_SOC_OMAP2420) += msdi.o +ifneq ($(CONFIG_DRM_OMAP),) +obj-y += drm.o +endif + # Specific board support -obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o +obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o @@ -245,14 +242,26 @@ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_OVERO) += board-overo.o +obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o +obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o sdram-nokia.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o +obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o board-zoom-peripherals.o +obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-display.o +obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-debugboard.o +obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o board-zoom-peripherals.o +obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-display.o +obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-debugboard.o +obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o +obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-peripherals.o +obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o +obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c new file mode 100644 index 0000000..20d6d81 --- /dev/null +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2009 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/mtd/nand.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "gpmc-smc91x.h" + +#include "board-zoom.h" + +#include "board-flash.h" +#include "mux.h" +#include "sdram-hynix-h8mbx00u0mer-0em.h" + +#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) + +static struct omap_smc91x_platform_data board_smc91x_data = { + .cs = 3, + .flags = GPMC_MUX_ADD_DATA | IORESOURCE_IRQ_LOWLEVEL, +}; + +static void __init board_smc91x_init(void) +{ + board_smc91x_data.gpio_irq = 158; + gpmc_smc91x_init(&board_smc91x_data); +} + +#else + +static inline void board_smc91x_init(void) +{ +} + +#endif /* defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) */ + +static void enable_board_wakeup_source(void) +{ + /* T2 interrupt line (keypad) */ + omap_mux_init_signal("sys_nirq", + OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); +} + +static struct usbhs_phy_data phy_data[] __initdata = { + { + .port = 1, + .reset_gpio = 126, + .vcc_gpio = -EINVAL, + }, + { + .port = 2, + .reset_gpio = 61, + .vcc_gpio = -EINVAL, + }, +}; + +static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, +}; + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#endif + +/* + * SDP3630 CS organization + * See also the Switch S8 settings in the comments. + */ +static char chip_sel_sdp[][GPMC_CS_NUM] = { + {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ + {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ + {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ +}; + +static struct mtd_partition sdp_nor_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "Bootloader-NOR", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "Params-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "Kernel-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "Filesystem-NOR", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct mtd_partition sdp_onenand_partitions[] = { + { + .name = "X-Loader-OneNAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot Environment-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 1 * (64 * 2048), + }, + { + .name = "Kernel-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 16 * (64 * 2048), + }, + { + .name = "File System-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition sdp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 6 * (64 * 2048), + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 40 * (64 * 2048), + }, + { + .name = "File System - NAND", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ + }, +}; + +static struct flash_partitions sdp_flash_partitions[] = { + { + .parts = sdp_nor_partitions, + .nr_parts = ARRAY_SIZE(sdp_nor_partitions), + }, + { + .parts = sdp_onenand_partitions, + .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), + }, + { + .parts = sdp_nand_partitions, + .nr_parts = ARRAY_SIZE(sdp_nand_partitions), + }, +}; + +static void __init omap_sdp_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); + zoom_peripherals_init(); + omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); + zoom_display_init(); + board_smc91x_init(); + board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); + enable_board_wakeup_source(); + + usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); + usbhs_init(&usbhs_bdata); +} + +MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3630_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = omap_sdp_init, + .init_late = omap3630_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 8dd0ec8..33d159e 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -25,7 +25,7 @@ #include <linux/gpio.h> #include <linux/platform_data/gpio-omap.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/i2c/twl.h> #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index ac82512..fc20a61 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, board_nand_data.nr_parts = nr_parts; board_nand_data.devsize = nand_type; - board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW; + board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; gpmc_nand_init(&board_nand_data, gpmc_t); } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 19f1652..87162e1 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -15,10 +15,13 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/irqdomain.h> +#include <linux/clk.h> #include <asm/mach/arch.h> #include "common.h" +#include "common-board-devices.h" +#include "dss-common.h" #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) #define intc_of_init NULL @@ -33,9 +36,40 @@ static struct of_device_id omap_dt_match_table[] __initdata = { { } }; +/* + * Create alias for USB host PHY clock. + * Remove this when clock phandle can be provided via DT + */ +static void __init legacy_init_ehci_clk(char *clkname) +{ + int ret; + + ret = clk_add_alias("main_clk", NULL, clkname, NULL); + if (ret) { + pr_err("%s:Failed to add main_clk alias to %s :%d\n", + __func__, clkname, ret); + } +} + static void __init omap_generic_init(void) { - pdata_quirks_init(omap_dt_match_table); + omap_sdrc_init(NULL, NULL); + + of_platform_populate(NULL, omap_dt_match_table, NULL, NULL); + + /* + * HACK: call display setup code for selected boards to enable omapdss. + * This will be removed when omapdss supports DT. + */ + if (of_machine_is_compatible("ti,omap4-panda")) { + omap4_panda_display_init_of(); + legacy_init_ehci_clk("auxclk3_ck"); + + } + else if (of_machine_is_compatible("ti,omap4-sdp")) + omap_4430sdp_display_init_of(); + else if (of_machine_is_compatible("ti,omap5-uevm")) + legacy_init_ehci_clk("auxclk1_ck"); } #ifdef CONFIG_SOC_OMAP2420 @@ -146,7 +180,6 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .init_late = am33xx_init_late, .init_time = omap3_gptimer_timer_init, .dt_compat = am33xx_boards_compat, .restart = am33xx_restart, @@ -186,7 +219,6 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .init_early = omap5_init_early, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, - .init_late = omap5_init_late, .init_time = omap5_realtime_timer_init, .dt_compat = omap5_boards_compat, .restart = omap44xx_restart, @@ -202,7 +234,6 @@ static const char *am43_boards_compat[] __initdata = { DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") .map_io = am33xx_map_io, .init_early = am43xx_init_early, - .init_late = am43xx_init_late, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, .init_time = omap3_sync32k_timer_init, @@ -221,7 +252,6 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") .smp = smp_ops(omap4_smp_ops), .map_io = omap5_map_io, .init_early = dra7xx_init_early, - .init_late = dra7xx_init_late, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, .init_time = omap5_realtime_timer_init, diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index f780834..87e41a8 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -20,7 +20,7 @@ #include <linux/delay.h> #include <linux/workqueue.h> #include <linux/i2c.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/input.h> #include <linux/err.h> #include <linux/clk.h> diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c new file mode 100644 index 0000000..06dbb2d --- /dev/null +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -0,0 +1,718 @@ +/* + * Copyright (C) 2009 Integration Software and Electronic Engineering. + * + * Modified from mach-omap2/board-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/usb/phy.h> + +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/i2c/twl.h> +#include <linux/mmc/host.h> + +#include <linux/mtd/nand.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <video/omapdss.h> +#include <video/omap-panel-data.h> +#include <linux/platform_data/mtd-onenand-omap2.h> + +#include "common.h" +#include "gpmc.h" +#include "mux.h" +#include "hsmmc.h" +#include "sdram-numonyx-m65kxxxxam.h" +#include "common-board-devices.h" +#include "board-flash.h" +#include "control.h" +#include "gpmc-onenand.h" + +#define IGEP2_SMSC911X_CS 5 +#define IGEP2_SMSC911X_GPIO 176 +#define IGEP2_GPIO_USBH_NRESET 24 +#define IGEP2_GPIO_LED0_GREEN 26 +#define IGEP2_GPIO_LED0_RED 27 +#define IGEP2_GPIO_LED1_RED 28 +#define IGEP2_GPIO_DVI_PUP 170 + +#define IGEP2_RB_GPIO_WIFI_NPD 94 +#define IGEP2_RB_GPIO_WIFI_NRESET 95 +#define IGEP2_RB_GPIO_BT_NRESET 137 +#define IGEP2_RC_GPIO_WIFI_NPD 138 +#define IGEP2_RC_GPIO_WIFI_NRESET 139 +#define IGEP2_RC_GPIO_BT_NRESET 137 + +#define IGEP3_GPIO_LED0_GREEN 54 +#define IGEP3_GPIO_LED0_RED 53 +#define IGEP3_GPIO_LED1_RED 16 +#define IGEP3_GPIO_USBH_NRESET 183 + +#define IGEP_SYSBOOT_MASK 0x1f +#define IGEP_SYSBOOT_NAND 0x0f +#define IGEP_SYSBOOT_ONENAND 0x10 + +/* + * IGEP2 Hardware Revision Table + * + * -------------------------------------------------------------------------- + * | Id. | Hw Rev. | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET | + * -------------------------------------------------------------------------- + * | 0 | B | high | gpio94 | gpio95 | - | + * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 | + * | 1 | C | low | gpio138 | gpio139 | gpio137 | + * -------------------------------------------------------------------------- + */ + +#define IGEP2_BOARD_HWREV_B 0 +#define IGEP2_BOARD_HWREV_C 1 +#define IGEP3_BOARD_HWREV 2 + +static u8 hwrev; + +static void __init igep2_get_revision(void) +{ + u8 ret; + + if (machine_is_igep0030()) { + hwrev = IGEP3_BOARD_HWREV; + return; + } + + omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT); + + if (gpio_request_one(IGEP2_GPIO_LED1_RED, GPIOF_IN, "GPIO_HW0_REV")) { + pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n"); + pr_err("IGEP2: Unknown Hardware Revision\n"); + return; + } + + ret = gpio_get_value(IGEP2_GPIO_LED1_RED); + if (ret == 0) { + pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n"); + hwrev = IGEP2_BOARD_HWREV_C; + } else if (ret == 1) { + pr_info("IGEP2: Hardware Revision B/C (B compatible)\n"); + hwrev = IGEP2_BOARD_HWREV_B; + } else { + pr_err("IGEP2: Unknown Hardware Revision\n"); + hwrev = -1; + } + + gpio_free(IGEP2_GPIO_LED1_RED); +} + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) || \ + defined(CONFIG_MTD_NAND_OMAP2) || \ + defined(CONFIG_MTD_NAND_OMAP2_MODULE) + +#define ONENAND_MAP 0x20000000 + +/* NAND04GR4E1A ( x2 Flash built-in COMBO POP MEMORY ) + * Since the device is equipped with two DataRAMs, and two-plane NAND + * Flash memory array, these two component enables simultaneous program + * of 4KiB. Plane1 has only even blocks such as block0, block2, block4 + * while Plane2 has only odd blocks such as block1, block3, block5. + * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) + */ + +static struct mtd_partition igep_flash_partitions[] = { + { + .name = "X-Loader", + .offset = 0, + .size = 2 * (64*(2*2048)) + }, + { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = 6 * (64*(2*2048)), + }, + { + .name = "Environment", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64*(2*2048)), + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = 12 * (64*(2*2048)), + }, + { + .name = "File System", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static inline u32 igep_get_sysboot_value(void) +{ + return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK; +} + +static void __init igep_flash_init(void) +{ + u32 mux; + mux = igep_get_sysboot_value(); + + if (mux == IGEP_SYSBOOT_NAND) { + pr_info("IGEP: initializing NAND memory device\n"); + board_nand_init(igep_flash_partitions, + ARRAY_SIZE(igep_flash_partitions), + 0, NAND_BUSWIDTH_16, nand_default_timings); + } else if (mux == IGEP_SYSBOOT_ONENAND) { + pr_info("IGEP: initializing OneNAND memory device\n"); + board_onenand_init(igep_flash_partitions, + ARRAY_SIZE(igep_flash_partitions), 0); + } else { + pr_err("IGEP: Flash: unsupported sysboot sequence found\n"); + } +} + +#else +static void __init igep_flash_init(void) {} +#endif + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) + +#include <linux/smsc911x.h> +#include "gpmc-smsc911x.h" + +static struct omap_smsc911x_platform_data smsc911x_cfg = { + .cs = IGEP2_SMSC911X_CS, + .gpio_irq = IGEP2_SMSC911X_GPIO, + .gpio_reset = -EINVAL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +}; + +static inline void __init igep2_init_smsc911x(void) +{ + gpmc_smsc911x_init(&smsc911x_cfg); +} + +#else +static inline void __init igep2_init_smsc911x(void) { } +#endif + +static struct regulator_consumer_supply igep_vmmc1_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data igep_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply), + .consumer_supplies = igep_vmmc1_supply, +}; + +static struct regulator_consumer_supply igep_vio_supply[] = { + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"), +}; + +static struct regulator_init_data igep_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply), + .consumer_supplies = igep_vio_supply, +}; + +static struct regulator_consumer_supply igep_vmmc2_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), +}; + +static struct regulator_init_data igep_vmmc2 = { + .constraints = { + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply), + .consumer_supplies = igep_vmmc2_supply, +}; + +static struct fixed_voltage_config igep_vwlan = { + .supply_name = "vwlan", + .microvolts = 3300000, + .gpio = -EINVAL, + .enabled_at_boot = 1, + .init_data = &igep_vmmc2, +}; + +static struct platform_device igep_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &igep_vwlan, + }, +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .deferred = true, + }, +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + { + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, +#endif + {} /* Terminator */ +}; + +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include <linux/leds.h> + +static struct gpio_led igep_gpio_leds[] = { + [0] = { + .name = "omap3:red:user0", + .default_state = 0, + }, + [1] = { + .name = "omap3:green:boot", + .default_state = 1, + }, + [2] = { + .name = "omap3:red:user1", + .default_state = 0, + }, + [3] = { + .name = "omap3:green:user1", + .default_state = 0, + .gpio = -EINVAL, /* gets replaced */ + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data igep_led_pdata = { + .leds = igep_gpio_leds, + .num_leds = ARRAY_SIZE(igep_gpio_leds), +}; + +static struct platform_device igep_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep_led_pdata, + }, +}; + +static void __init igep_leds_init(void) +{ + if (machine_is_igep0020()) { + igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED; + igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN; + igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED; + } else { + igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED; + igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN; + igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED; + } + + platform_device_register(&igep_led_device); +} + +#else +static struct gpio igep_gpio_leds[] __initdata = { + { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:red:d0" }, + { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:green:d0" }, + { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:red:d1" }, +}; + +static inline void igep_leds_init(void) +{ + int i; + + if (machine_is_igep0020()) { + igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED; + igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN; + igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED; + } else { + igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED; + igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN; + igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED; + } + + if (gpio_request_array(igep_gpio_leds, ARRAY_SIZE(igep_gpio_leds))) { + pr_warning("IGEP v2: Could not obtain leds gpios\n"); + return; + } + + for (i = 0; i < ARRAY_SIZE(igep_gpio_leds); i++) + gpio_export(igep_gpio_leds[i].gpio, 0); +} +#endif + +static struct gpio igep2_twl_gpios[] = { + { -EINVAL, GPIOF_IN, "GPIO_EHCI_NOC" }, + { -EINVAL, GPIOF_OUT_INIT_LOW, "GPIO_USBH_CPEN" }, +}; + +static int igep_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + int ret; + + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + mmc[0].gpio_cd = gpio + 0; + omap_hsmmc_late_init(mmc); + + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + ret = gpio_request_one(gpio + TWL4030_GPIO_MAX + 1, GPIOF_OUT_INIT_HIGH, + "gpio-led:green:d1"); + if (ret == 0) + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + else + pr_warning("IGEP: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + + if (machine_is_igep0030()) + return 0; + + /* + * REVISIT: need ehci-omap hooks for external VBUS + * power switch and overcurrent detect + */ + igep2_twl_gpios[0].gpio = gpio + 1; + + /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */ + igep2_twl_gpios[1].gpio = gpio + TWL4030_GPIO_MAX; + + ret = gpio_request_array(igep2_twl_gpios, ARRAY_SIZE(igep2_twl_gpios)); + if (ret < 0) + pr_err("IGEP2: Could not obtain gpio for USBH_CPEN"); + + return 0; +}; + +static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { + .use_leds = true, + .setup = igep_twl_gpio_setup, +}; + +static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, +}; + +static struct platform_device omap3stalker_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3stalker_dvi_connector_pdata, +}; + +static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = IGEP2_GPIO_DVI_PUP, +}; + +static struct platform_device omap3stalker_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3stalker_tfp410_pdata, +}; + +static struct omap_dss_board_info igep2_dss_data = { + .default_display_name = "dvi", +}; + +static struct platform_device *igep_devices[] __initdata = { + &igep_vwlan_device, + &omap3stalker_tfp410_device, + &omap3stalker_dvi_connector_device, +}; + +static int igep2_keymap[] = { + KEY(0, 0, KEY_LEFT), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_A), + KEY(0, 3, KEY_B), + KEY(1, 0, KEY_DOWN), + KEY(1, 1, KEY_UP), + KEY(1, 2, KEY_E), + KEY(1, 3, KEY_F), + KEY(2, 0, KEY_ENTER), + KEY(2, 1, KEY_I), + KEY(2, 2, KEY_J), + KEY(2, 3, KEY_K), + KEY(3, 0, KEY_M), + KEY(3, 1, KEY_N), + KEY(3, 2, KEY_O), + KEY(3, 3, KEY_P) +}; + +static struct matrix_keymap_data igep2_keymap_data = { + .keymap = igep2_keymap, + .keymap_size = ARRAY_SIZE(igep2_keymap), +}; + +static struct twl4030_keypad_data igep2_keypad_pdata = { + .keymap_data = &igep2_keymap_data, + .rows = 4, + .cols = 4, + .rep = 1, +}; + +static struct twl4030_platform_data igep_twldata = { + /* platform_data for children goes here */ + .gpio = &igep_twl4030_gpio_pdata, + .vmmc1 = &igep_vmmc1, + .vio = &igep_vio, +}; + +static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + +static void __init igep_i2c_init(void) +{ + int ret; + + omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, + TWL_COMMON_REGULATOR_VPLL2); + igep_twldata.vpll2->constraints.apply_uV = true; + igep_twldata.vpll2->constraints.name = "VDVI"; + + if (machine_is_igep0020()) { + /* + * Bus 3 is attached to the DVI port where devices like the + * pico DLP projector don't work reliably with 400kHz + */ + ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo, + ARRAY_SIZE(igep2_i2c3_boardinfo)); + if (ret) + pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret); + + igep_twldata.keypad = &igep2_keypad_pdata; + /* Get common pmic data */ + omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0); + } + + omap3_pmic_init("twl4030", &igep_twldata); +} + +static struct usbhs_phy_data igep2_phy_data[] __initdata = { + { + .port = 1, + .reset_gpio = IGEP2_GPIO_USBH_NRESET, + .vcc_gpio = -EINVAL, + }, +}; + +static struct usbhs_phy_data igep3_phy_data[] __initdata = { + { + .port = 2, + .reset_gpio = IGEP3_GPIO_USBH_NRESET, + .vcc_gpio = -EINVAL, + }, +}; + +static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, +}; + +static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = { + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, +}; + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + /* Display Sub System */ + OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), + /* TFP410 PanelBus DVI Transmitte (GPIO_170) */ + OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */ + OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#endif + +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) +static struct gpio igep_wlan_bt_gpios[] __initdata = { + { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NPD" }, + { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NRESET" }, + { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_BT_NRESET" }, +}; + +static void __init igep_wlan_bt_init(void) +{ + int err; + + /* GPIO's for WLAN-BT combo depends on hardware revision */ + if (hwrev == IGEP2_BOARD_HWREV_B) { + igep_wlan_bt_gpios[0].gpio = IGEP2_RB_GPIO_WIFI_NPD; + igep_wlan_bt_gpios[1].gpio = IGEP2_RB_GPIO_WIFI_NRESET; + igep_wlan_bt_gpios[2].gpio = IGEP2_RB_GPIO_BT_NRESET; + } else if (hwrev == IGEP2_BOARD_HWREV_C || machine_is_igep0030()) { + igep_wlan_bt_gpios[0].gpio = IGEP2_RC_GPIO_WIFI_NPD; + igep_wlan_bt_gpios[1].gpio = IGEP2_RC_GPIO_WIFI_NRESET; + igep_wlan_bt_gpios[2].gpio = IGEP2_RC_GPIO_BT_NRESET; + } else + return; + + /* Make sure that the GPIO pins are muxed correctly */ + omap_mux_init_gpio(igep_wlan_bt_gpios[0].gpio, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(igep_wlan_bt_gpios[1].gpio, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(igep_wlan_bt_gpios[2].gpio, OMAP_PIN_OUTPUT); + + err = gpio_request_array(igep_wlan_bt_gpios, + ARRAY_SIZE(igep_wlan_bt_gpios)); + if (err) { + pr_warning("IGEP2: Could not obtain WIFI/BT gpios\n"); + return; + } + + gpio_export(igep_wlan_bt_gpios[0].gpio, 0); + gpio_export(igep_wlan_bt_gpios[1].gpio, 0); + gpio_export(igep_wlan_bt_gpios[2].gpio, 0); + + gpio_set_value(igep_wlan_bt_gpios[1].gpio, 0); + udelay(10); + gpio_set_value(igep_wlan_bt_gpios[1].gpio, 1); + +} +#else +static inline void __init igep_wlan_bt_init(void) { } +#endif + +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +static void __init igep_init(void) +{ + regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + /* Get IGEP2 hardware revision */ + igep2_get_revision(); + + omap_hsmmc_init(mmc); + + /* Register I2C busses and drivers */ + igep_i2c_init(); + platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices)); + omap_serial_init(); + omap_sdrc_init(m65kxxxxam_sdrc_params, + m65kxxxxam_sdrc_params); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); + usb_musb_init(NULL); + + igep_flash_init(); + igep_leds_init(); + omap_twl4030_audio_init("igep2", NULL); + + /* + * WLAN-BT combo module from MuRata which has a Marvell WLAN + * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. + */ + igep_wlan_bt_init(); + + if (machine_is_igep0020()) { + omap_display_init(&igep2_dss_data); + igep2_init_smsc911x(); + usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data)); + usbhs_init(&igep2_usbhs_bdata); + } else { + usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data)); + usbhs_init(&igep3_usbhs_bdata); + } +} + +MACHINE_START(IGEP0020, "IGEP v2 board") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap35xx_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = igep_init, + .init_late = omap35xx_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END + +MACHINE_START(IGEP0030, "IGEP OMAP3 module") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap35xx_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = igep_init, + .init_late = omap35xx_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 4ec8d82..dd8da2c 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -36,6 +36,7 @@ #include <asm/mach/map.h> #include "common.h" +#include "board-zoom.h" #include "gpmc.h" #include "gpmc-smsc911x.h" @@ -405,7 +406,7 @@ static void __init omap_ldp_init(void) usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), - 0, 0, nand_default_timings); + ZOOM_NAND_CS, 0, nand_default_timings); omap_hsmmc_init(mmc); ldp_display_init(); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index d6ed819..f269184 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -25,7 +25,7 @@ #include <linux/gpio.h> #include <linux/input.h> #include <linux/gpio_keys.h> -#include <linux/pm_opp.h> +#include <linux/opp.h> #include <linux/cpu.h> #include <linux/mtd/mtd.h> @@ -289,12 +289,18 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = { static struct gpio_led gpio_leds[]; +/* PHY's VCC regulator might be added later, so flag that we need it */ +static struct usb_phy_gen_xceiv_platform_data hsusb2_phy_data = { + .needs_vcc = true, +}; + static struct usbhs_phy_data phy_data[] = { { .port = 2, .reset_gpio = 147, .vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */ .vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */ + .platform_data = &hsusb2_phy_data, }, }; @@ -510,17 +516,17 @@ static int __init beagle_opp_init(void) mpu_dev = get_cpu_device(0); iva_dev = omap_device_get_by_hwmod_name("iva"); - if (!mpu_dev || IS_ERR(iva_dev)) { + if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) { pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", __func__, mpu_dev, iva_dev); return -ENODEV; } /* Enable MPU 1GHz and lower opps */ - r = dev_pm_opp_enable(mpu_dev, 800000000); + r = opp_enable(mpu_dev, 800000000); /* TODO: MPU 1GHz needs SR and ABB */ /* Enable IVA 800MHz and lower opps */ - r |= dev_pm_opp_enable(iva_dev, 660000000); + r |= opp_enable(iva_dev, 660000000); /* TODO: DSP 800MHz needs SR and ABB */ if (r) { pr_err("%s: failed to enable higher opp %d\n", @@ -529,8 +535,8 @@ static int __init beagle_opp_init(void) * Cleanup - disable the higher freqs - we dont care * about the results */ - dev_pm_opp_disable(mpu_dev, 800000000); - dev_pm_opp_disable(iva_dev, 660000000); + opp_disable(mpu_dev, 800000000); + opp_disable(iva_dev, 660000000); } } return 0; diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c new file mode 100644 index 0000000..1814387 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -0,0 +1,756 @@ +/* + * linux/arch/arm/mach-omap2/board-omap3evm.c + * + * Copyright (C) 2008 Texas Instruments + * + * Modified from mach-omap2/board-3430sdp.c + * + * Initial code: Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/input/matrix_keypad.h> +#include <linux/leds.h> +#include <linux/interrupt.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> + +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> +#include <linux/i2c/twl.h> +#include <linux/usb/otg.h> +#include <linux/usb/musb.h> +#include <linux/usb/usb_phy_gen_xceiv.h> +#include <linux/smsc911x.h> + +#include <linux/wl12xx.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/mmc/host.h> +#include <linux/export.h> +#include <linux/usb/phy.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <linux/platform_data/mtd-nand-omap2.h> +#include "common.h" +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <video/omapdss.h> +#include <video/omap-panel-data.h> + +#include "soc.h" +#include "mux.h" +#include "sdram-micron-mt46h32m32lf-6.h" +#include "hsmmc.h" +#include "common-board-devices.h" +#include "board-flash.h" + +#define NAND_CS 0 + +#define OMAP3_EVM_TS_GPIO 175 +#define OMAP3_EVM_EHCI_VBUS 22 +#define OMAP3_EVM_EHCI_SELECT 61 + +#define OMAP3EVM_ETHR_START 0x2c000000 +#define OMAP3EVM_ETHR_SIZE 1024 +#define OMAP3EVM_ETHR_ID_REV 0x50 +#define OMAP3EVM_ETHR_GPIO_IRQ 176 +#define OMAP3EVM_SMSC911X_CS 5 +/* + * Eth Reset signal + * 64 = Generation 1 (<=RevD) + * 7 = Generation 2 (>=RevE) + */ +#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 +#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 + +/* + * OMAP35x EVM revision + * Run time detection of EVM revision is done by reading Ethernet + * PHY ID - + * GEN_1 = 0x01150000 + * GEN_2 = 0x92200000 + */ +enum { + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ +}; + +static u8 omap3_evm_version; + +static u8 get_omap3_evm_rev(void) +{ + return omap3_evm_version; +} + +static void __init omap3_evm_get_revision(void) +{ + void __iomem *ioaddr; + unsigned int smsc_id; + + /* Ethernet PHY ID is stored at ID_REV register */ + ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K); + if (!ioaddr) + return; + smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000; + iounmap(ioaddr); + + switch (smsc_id) { + /*SMSC9115 chipset*/ + case 0x01150000: + omap3_evm_version = OMAP3EVM_BOARD_GEN_1; + break; + /*SMSC 9220 chipset*/ + case 0x92200000: + default: + omap3_evm_version = OMAP3EVM_BOARD_GEN_2; + } +} + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +#include "gpmc-smsc911x.h" + +static struct omap_smsc911x_platform_data smsc911x_cfg = { + .cs = OMAP3EVM_SMSC911X_CS, + .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ, + .gpio_reset = -EINVAL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +}; + +static inline void __init omap3evm_init_smsc911x(void) +{ + /* Configure ethernet controller reset gpio */ + if (cpu_is_omap3430()) { + if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) + smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST; + else + smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST; + } + + gpmc_smsc911x_init(&smsc911x_cfg); +} + +#else +static inline void __init omap3evm_init_smsc911x(void) { return; } +#endif + +/* + * OMAP3EVM LCD Panel control signals + */ +#define OMAP3EVM_LCD_PANEL_LR 2 +#define OMAP3EVM_LCD_PANEL_UD 3 +#define OMAP3EVM_LCD_PANEL_INI 152 +#define OMAP3EVM_LCD_PANEL_QVGA 154 +#define OMAP3EVM_LCD_PANEL_RESB 155 + +#define OMAP3EVM_LCD_PANEL_ENVDD 153 +#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210 + +/* + * OMAP3EVM DVI control signals + */ +#define OMAP3EVM_DVI_PANEL_EN_GPIO 199 + +#ifdef CONFIG_BROKEN +static void __init omap3_evm_display_init(void) +{ + int r; + + r = gpio_request_one(OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW, + "lcd_panel_envdd"); + if (r) + pr_err("failed to get lcd_panel_envdd GPIO\n"); + + r = gpio_request_one(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, + GPIOF_OUT_INIT_LOW, "lcd_panel_bklight"); + if (r) + pr_err("failed to get lcd_panel_bklight GPIO\n"); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) + gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + else + gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); +} +#endif + +static struct panel_sharp_ls037v7dw01_platform_data omap3_evm_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .resb_gpio = OMAP3EVM_LCD_PANEL_RESB, + .ini_gpio = OMAP3EVM_LCD_PANEL_INI, + .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA, + .lr_gpio = OMAP3EVM_LCD_PANEL_LR, + .ud_gpio = OMAP3EVM_LCD_PANEL_UD, +}; + +static struct platform_device omap3_evm_lcd_device = { + .name = "panel-sharp-ls037v7dw01", + .id = 0, + .dev.platform_data = &omap3_evm_lcd_pdata, +}; + +static struct connector_dvi_platform_data omap3_evm_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, +}; + +static struct platform_device omap3_evm_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3_evm_dvi_connector_pdata, +}; + +static struct encoder_tfp410_platform_data omap3_evm_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, +}; + +static struct platform_device omap3_evm_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3_evm_tfp410_pdata, +}; + +static struct connector_atv_platform_data omap3_evm_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device omap3_evm_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &omap3_evm_tv_pdata, +}; + +static struct omap_dss_board_info omap3_evm_dss_data = { + .default_display_name = "lcd", +}; + +static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), +}; + +static struct regulator_consumer_supply omap3evm_vsim_supply[] = { + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), +}; + +/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ +static struct regulator_init_data omap3evm_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply), + .consumer_supplies = omap3evm_vmmc1_supply, +}; + +/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ +static struct regulator_init_data omap3evm_vsim = { + .constraints = { + .min_uV = 1800000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply), + .consumer_supplies = omap3evm_vsim_supply, +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = 63, + .deferred = true, + }, +#ifdef CONFIG_WILINK_PLATFORM_DATA + { + .name = "wl1271", + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .nonremovable = true, + }, +#endif + {} /* Terminator */ +}; + +static struct gpio_led gpio_leds[] = { + { + .name = "omap3evm::ledb", + /* normally not visible (board underside) */ + .default_trigger = "default-on", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + }, +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + }, +}; + + +static int omap3evm_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + int r, lcd_bl_en; + + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + mmc[0].gpio_cd = gpio + 0; + omap_hsmmc_late_init(mmc); + + /* + * Most GPIOs are for USB OTG. Some are mostly sent to + * the P2 connector; notably LEDA for the LCD backlight. + */ + + /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ + lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ? + GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; + r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL"); + if (r) + printk(KERN_ERR "failed to get/set lcd_bkl gpio\n"); + + /* gpio + 7 == DVI Enable */ + gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI"); + + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ + gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1; + + platform_device_register(&leds_gpio); + + /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output + * for starting USB tranceiver + */ +#ifdef CONFIG_TWL4030_CORE + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { + u8 val; + + twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1); + val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */ + twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1); + } +#endif + + return 0; +} + +static struct twl4030_gpio_platform_data omap3evm_gpio_data = { + .use_leds = true, + .setup = omap3evm_twl_gpio_setup, +}; + +static uint32_t board_keymap[] = { + KEY(0, 0, KEY_LEFT), + KEY(0, 1, KEY_DOWN), + KEY(0, 2, KEY_ENTER), + KEY(0, 3, KEY_M), + + KEY(1, 0, KEY_RIGHT), + KEY(1, 1, KEY_UP), + KEY(1, 2, KEY_I), + KEY(1, 3, KEY_N), + + KEY(2, 0, KEY_A), + KEY(2, 1, KEY_E), + KEY(2, 2, KEY_J), + KEY(2, 3, KEY_O), + + KEY(3, 0, KEY_B), + KEY(3, 1, KEY_F), + KEY(3, 2, KEY_K), + KEY(3, 3, KEY_P) +}; + +static struct matrix_keymap_data board_map_data = { + .keymap = board_keymap, + .keymap_size = ARRAY_SIZE(board_keymap), +}; + +static struct twl4030_keypad_data omap3evm_kp_data = { + .keymap_data = &board_map_data, + .rows = 4, + .cols = 4, + .rep = 1, +}; + +/* ads7846 on SPI */ +static struct regulator_consumer_supply omap3evm_vio_supply[] = { + REGULATOR_SUPPLY("vcc", "spi1.0"), +}; + +/* VIO for ads7846 */ +static struct regulator_init_data omap3evm_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply), + .consumer_supplies = omap3evm_vio_supply, +}; + +#ifdef CONFIG_WILINK_PLATFORM_DATA + +#define OMAP3EVM_WLAN_PMENA_GPIO (150) +#define OMAP3EVM_WLAN_IRQ_GPIO (149) + +static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), +}; + +/* VMMC2 for driving the WL12xx module */ +static struct regulator_init_data omap3evm_vmmc2 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply), + .consumer_supplies = omap3evm_vmmc2_supply, +}; + +static struct fixed_voltage_config omap3evm_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.80V */ + .gpio = OMAP3EVM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70ms */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &omap3evm_vmmc2, +}; + +static struct platform_device omap3evm_wlan_regulator = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &omap3evm_vwlan, + }, +}; + +struct wl12xx_platform_data omap3evm_wlan_data __initdata = { + .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ +}; +#endif + +/* VAUX2 for USB */ +static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = { + REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */ + REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */ + REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("vaux2", NULL), +}; + +static struct regulator_init_data omap3evm_vaux2 = { + .constraints = { + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(omap3evm_vaux2_supplies), + .consumer_supplies = omap3evm_vaux2_supplies, +}; + +static struct twl4030_platform_data omap3evm_twldata = { + /* platform_data for children goes here */ + .keypad = &omap3evm_kp_data, + .gpio = &omap3evm_gpio_data, + .vio = &omap3evm_vio, + .vmmc1 = &omap3evm_vmmc1, + .vsim = &omap3evm_vsim, +}; + +static int __init omap3_evm_i2c_init(void) +{ + omap3_pmic_get_config(&omap3evm_twldata, + TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC | + TWL_COMMON_PDATA_AUDIO, + TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); + + omap3evm_twldata.vdac->constraints.apply_uV = true; + omap3evm_twldata.vpll2->constraints.apply_uV = true; + + omap3_pmic_init("twl4030", &omap3evm_twldata); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; +} + +static struct usbhs_phy_data phy_data[] __initdata = { + { + .port = 2, + .reset_gpio = -1, /* set at runtime */ + .vcc_gpio = -EINVAL, + }, +}; + +static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, +}; + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux omap35x_board_mux[] __initdata = { + OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), + OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_NONE), + OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_NONE), +#ifdef CONFIG_WILINK_PLATFORM_DATA + /* WLAN IRQ - GPIO 149 */ + OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + + /* WLAN POWER ENABLE - GPIO 150 */ + OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + /* MMC2 SDIO pin muxes for WL12xx */ + OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), +#endif + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +static struct omap_board_mux omap36x_board_mux[] __initdata = { + OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), + /* AM/DM37x EVM: DSS data bus muxed with sys_boot */ + OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), +#ifdef CONFIG_WILINK_PLATFORM_DATA + /* WLAN IRQ - GPIO 149 */ + OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + + /* WLAN POWER ENABLE - GPIO 150 */ + OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + /* MMC2 SDIO pin muxes for WL12xx */ + OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), +#endif + + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap35x_board_mux NULL +#define omap36x_board_mux NULL +#endif + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 100, +}; + +static struct gpio omap3_evm_ehci_gpios[] __initdata = { + { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" }, + { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" }, +}; + +static void __init omap3_evm_wl12xx_init(void) +{ +#ifdef CONFIG_WILINK_PLATFORM_DATA + int ret; + + /* WL12xx WLAN Init */ + omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO); + ret = wl12xx_set_platform_data(&omap3evm_wlan_data); + if (ret) + pr_err("error setting wl12xx data: %d\n", ret); + ret = platform_device_register(&omap3evm_wlan_regulator); + if (ret) + pr_err("error registering wl12xx device: %d\n", ret); +#endif +} + +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +static struct mtd_partition omap3evm_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader", + .offset = 0, + .size = 4*(SZ_128K), + .mask_flags = MTD_WRITEABLE + }, + { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = 14*(SZ_128K), + .mask_flags = MTD_WRITEABLE + }, + { + .name = "U-Boot Env", + .offset = MTDPART_OFS_APPEND, + .size = 2*(SZ_128K) + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = 40*(SZ_128K) + }, + { + .name = "File system", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +static void __init omap3_evm_init(void) +{ + struct omap_board_mux *obm; + + omap3_evm_get_revision(); + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; + omap3_mux_init(obm, OMAP_PACKAGE_CBB); + + omap_mux_init_gpio(63, OMAP_PIN_INPUT); + omap_hsmmc_init(mmc); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) + omap3evm_twldata.vaux2 = &omap3evm_vaux2; + + omap3_evm_i2c_init(); + + omap_display_init(&omap3_evm_dss_data); + platform_device_register(&omap3_evm_lcd_device); + platform_device_register(&omap3_evm_tfp410_device); + platform_device_register(&omap3_evm_dvi_connector_device); + platform_device_register(&omap3_evm_tv_connector_device); + + omap_serial_init(); + omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); + + /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */ + usb_nop_xceiv_register(); + + if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) { + /* enable EHCI VBUS using GPIO22 */ + omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP); + /* Select EHCI port on main board */ + omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT, + OMAP_PIN_INPUT_PULLUP); + gpio_request_array(omap3_evm_ehci_gpios, + ARRAY_SIZE(omap3_evm_ehci_gpios)); + + /* setup EHCI phy reset config */ + omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); + phy_data[0].reset_gpio = 21; + + /* EVM REV >= E can supply 500mA with EXTVBUS programming */ + musb_board_data.power = 500; + musb_board_data.extvbus = 1; + } else { + /* setup EHCI phy reset on MDC */ + omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); + phy_data[0].reset_gpio = 135; + } + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); + usb_musb_init(&musb_board_data); + + usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); + usbhs_init(&usbhs_bdata); + board_nand_init(omap3evm_nand_partitions, + ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS, + NAND_BUSWIDTH_16, NULL); + + omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); + omap3evm_init_smsc911x(); +#ifdef CONFIG_BROKEN + omap3_evm_display_init(); +#endif + omap3_evm_wl12xx_init(); + omap_twl4030_audio_init("omap3evm", NULL); +} + +MACHINE_START(OMAP3EVM, "OMAP3 EVM") + /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap35xx_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = omap3_evm_init, + .init_late = omap35xx_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 119efaf..ba8342f 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -32,7 +32,7 @@ #include <linux/spi/spi.h> #include <linux/interrupt.h> #include <linux/smsc911x.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/usb/phy.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c new file mode 100644 index 0000000..345e8c4 --- /dev/null +++ b/arch/arm/mach-omap2/board-rm680.c @@ -0,0 +1,167 @@ +/* + * Board support file for Nokia N950 (RM-680) / N9 (RM-696). + * + * Copyright (C) 2010 Nokia + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/i2c/twl.h> +#include <linux/platform_device.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/consumer.h> +#include <linux/platform_data/mtd-onenand-omap2.h> +#include <linux/usb/phy.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include "common.h" +#include "mux.h" +#include "gpmc.h" +#include "mmc.h" +#include "hsmmc.h" +#include "sdram-nokia.h" +#include "common-board-devices.h" +#include "gpmc-onenand.h" + +static struct regulator_consumer_supply rm680_vemmc_consumers[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), +}; + +/* Fixed regulator for internal eMMC */ +static struct regulator_init_data rm680_vemmc = { + .constraints = { + .name = "rm680_vemmc", + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_STATUS + | REGULATOR_CHANGE_MODE, + }, + .num_consumer_supplies = ARRAY_SIZE(rm680_vemmc_consumers), + .consumer_supplies = rm680_vemmc_consumers, +}; + +static struct fixed_voltage_config rm680_vemmc_config = { + .supply_name = "VEMMC", + .microvolts = 2900000, + .gpio = 157, + .startup_delay = 150, + .enable_high = 1, + .init_data = &rm680_vemmc, +}; + +static struct platform_device rm680_vemmc_device = { + .name = "reg-fixed-voltage", + .dev = { + .platform_data = &rm680_vemmc_config, + }, +}; + +static struct platform_device *rm680_peripherals_devices[] __initdata = { + &rm680_vemmc_device, +}; + +/* TWL */ +static struct twl4030_gpio_platform_data rm680_gpio_data = { + .pullups = BIT(0), + .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), +}; + +static struct twl4030_platform_data rm680_twl_data = { + .gpio = &rm680_gpio_data, + /* add rest of the children here */ +}; + +static void __init rm680_i2c_init(void) +{ + omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0); + omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); +} + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) +static struct omap_onenand_platform_data board_onenand_data[] = { + { + .gpio_irq = 65, + .flags = ONENAND_SYNC_READWRITE, + } +}; +#endif + +/* eMMC */ +static struct omap2_hsmmc_info mmc[] __initdata = { + { + .name = "internal", + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + { /* Terminator */ } +}; + +static void __init rm680_peripherals_init(void) +{ + platform_add_devices(rm680_peripherals_devices, + ARRAY_SIZE(rm680_peripherals_devices)); + rm680_i2c_init(); + gpmc_onenand_init(board_onenand_data); + omap_hsmmc_init(mmc); +} + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#endif + +static void __init rm680_init(void) +{ + struct omap_sdrc_params *sdrc_params; + + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); + + sdrc_params = nokia_get_sdram_timings(); + omap_sdrc_init(sdrc_params, sdrc_params); + + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); + usb_musb_init(NULL); + rm680_peripherals_init(); +} + +MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3630_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = rm680_init, + .init_late = omap3630_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END + +MACHINE_START(NOKIA_RM696, "Nokia RM-696 board") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3630_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = rm680_init, + .init_late = omap3630_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index f093af1..f6fe388 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -57,8 +57,6 @@ #include "common-board-devices.h" #include "gpmc.h" #include "gpmc-onenand.h" -#include "soc.h" -#include "omap-secure.h" #define SYSTEM_REV_B_USES_VAUX3 0x1699 #define SYSTEM_REV_S_USES_VAUX3 0x8 @@ -213,11 +211,29 @@ static struct lp55xx_led_config rx51_lp5523_led_config[] = { } }; +static int rx51_lp5523_setup(void) +{ + return gpio_request_one(RX51_LP5523_CHIP_EN_GPIO, GPIOF_DIR_OUT, + "lp5523_enable"); +} + +static void rx51_lp5523_release(void) +{ + gpio_free(RX51_LP5523_CHIP_EN_GPIO); +} + +static void rx51_lp5523_enable(bool state) +{ + gpio_set_value(RX51_LP5523_CHIP_EN_GPIO, !!state); +} + static struct lp55xx_platform_data rx51_lp5523_platform_data = { .led_config = rx51_lp5523_led_config, .num_channels = ARRAY_SIZE(rx51_lp5523_led_config), .clock_mode = LP55XX_CLOCK_AUTO, - .enable_gpio = RX51_LP5523_CHIP_EN_GPIO, + .setup_resources = rx51_lp5523_setup, + .release_resources = rx51_lp5523_release, + .enable = rx51_lp5523_enable, }; #endif @@ -1282,22 +1298,6 @@ static void __init rx51_init_twl4030_hwmon(void) platform_device_register(&madc_hwmon); } -static struct platform_device omap3_rom_rng_device = { - .name = "omap3-rom-rng", - .id = -1, - .dev = { - .platform_data = rx51_secure_rng_call, - }, -}; - -static void __init rx51_init_omap3_rom_rng(void) -{ - if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { - pr_info("RX-51: Registring OMAP3 HWRNG device\n"); - platform_device_register(&omap3_rom_rng_device); - } -} - void __init rx51_peripherals_init(void) { rx51_i2c_init(); @@ -1318,6 +1318,5 @@ void __init rx51_peripherals_init(void) rx51_charger_init(); rx51_init_twl4030_hwmon(); - rx51_init_omap3_rom_rng(); } diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index db168c9..773510556 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -2,8 +2,6 @@ * Board support file for Nokia N900 (aka RX-51). * * Copyright (C) 2007, 2008 Nokia - * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> - * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -33,9 +31,7 @@ #include "mux.h" #include "gpmc.h" #include "pm.h" -#include "soc.h" #include "sdram-nokia.h" -#include "omap-secure.h" #define RX51_GPIO_SLEEP_IND 162 @@ -107,14 +103,6 @@ static void __init rx51_init(void) usb_musb_init(&musb_board_data); rx51_peripherals_init(); - if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { -#ifdef CONFIG_ARM_ERRATA_430973 - pr_info("RX-51: Enabling ARM errata 430973 workaround\n"); - /* set IBE to 1 */ - rx51_secure_update_aux_cr(BIT(6), 0); -#endif - } - /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c new file mode 100644 index 0000000..42e5f23 --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2009 Texas Instruments Inc. + * Mikkel Christensen <mlc@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/serial_8250.h> +#include <linux/smsc911x.h> +#include <linux/interrupt.h> + +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> + +#include "gpmc.h" +#include "gpmc-smsc911x.h" + +#include "board-zoom.h" + +#include "soc.h" +#include "common.h" + +#define ZOOM_SMSC911X_CS 7 +#define ZOOM_SMSC911X_GPIO 158 +#define ZOOM_QUADUART_CS 3 +#define ZOOM_QUADUART_GPIO 102 +#define ZOOM_QUADUART_RST_GPIO 152 +#define QUART_CLK 1843200 +#define DEBUG_BASE 0x08000000 +#define ZOOM_ETHR_START DEBUG_BASE + +static struct omap_smsc911x_platform_data zoom_smsc911x_cfg = { + .cs = ZOOM_SMSC911X_CS, + .gpio_irq = ZOOM_SMSC911X_GPIO, + .gpio_reset = -EINVAL, + .flags = SMSC911X_USE_32BIT, +}; + +static inline void __init zoom_init_smsc911x(void) +{ + gpmc_smsc911x_init(&zoom_smsc911x_cfg); +} + +static struct plat_serial8250_port serial_platform_data[] = { + { + .mapbase = ZOOM_UART_BASE, + .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ, + .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = QUART_CLK, + }, { + .flags = 0 + } +}; + +static struct platform_device zoom_debugboard_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; + +static inline void __init zoom_init_quaduart(void) +{ + int quart_cs; + unsigned long cs_mem_base; + int quart_gpio = 0; + + if (gpio_request_one(ZOOM_QUADUART_RST_GPIO, + GPIOF_OUT_INIT_LOW, + "TL16CP754C GPIO") < 0) { + pr_err("Failed to request GPIO%d for TL16CP754C\n", + ZOOM_QUADUART_RST_GPIO); + return; + } + + quart_cs = ZOOM_QUADUART_CS; + + if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) { + pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n"); + return; + } + + quart_gpio = ZOOM_QUADUART_GPIO; + + if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0) + printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n", + quart_gpio); + + serial_platform_data[0].irq = gpio_to_irq(102); +} + +static inline int omap_zoom_debugboard_detect(void) +{ + int debug_board_detect = 0; + int ret = 1; + + debug_board_detect = ZOOM_SMSC911X_GPIO; + + if (gpio_request_one(debug_board_detect, GPIOF_IN, + "Zoom debug board detect") < 0) { + pr_err("Failed to request GPIO%d for Zoom debug board detect\n", + debug_board_detect); + return 0; + } + + if (!gpio_get_value(debug_board_detect)) { + ret = 0; + } + gpio_free(debug_board_detect); + return ret; +} + +static struct platform_device *zoom_devices[] __initdata = { + &zoom_debugboard_serial_device, +}; + +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +int __init zoom_debugboard_init(void) +{ + if (!omap_zoom_debugboard_detect()) + return 0; + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + zoom_init_smsc911x(); + zoom_init_quaduart(); + return platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices)); +} diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c new file mode 100644 index 0000000..3d8ecc1 --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010 Texas Instruments Inc. + * + * Modified from mach-omap2/board-zoom-peripherals.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/spi/spi.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <video/omapdss.h> +#include <video/omap-panel-data.h> + +#include "board-zoom.h" +#include "soc.h" +#include "common.h" + +#define LCD_PANEL_RESET_GPIO_PROD 96 +#define LCD_PANEL_RESET_GPIO_PILOT 55 +#define LCD_PANEL_QVGA_GPIO 56 + +static struct panel_nec_nl8048hl11_platform_data zoom_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 24, + + .res_gpio = -1, /* filled in code */ + .qvga_gpio = LCD_PANEL_QVGA_GPIO, +}; + +static struct omap_dss_board_info zoom_dss_data = { + .default_display_name = "lcd", +}; + +static void __init zoom_lcd_panel_init(void) +{ + zoom_lcd_pdata.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? + LCD_PANEL_RESET_GPIO_PROD : + LCD_PANEL_RESET_GPIO_PILOT; +} + +static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { + .turbo_mode = 1, +}; + +static struct spi_board_info nec_8048_spi_board_info[] __initdata = { + [0] = { + .modalias = "panel-nec-nl8048hl11", + .bus_num = 1, + .chip_select = 2, + .max_speed_hz = 375000, + .controller_data = &dss_lcd_mcspi_config, + .platform_data = &zoom_lcd_pdata, + }, +}; + +void __init zoom_display_init(void) +{ + omap_display_init(&zoom_dss_data); + zoom_lcd_panel_init(); + spi_register_board_info(nec_8048_spi_board_info, + ARRAY_SIZE(nec_8048_spi_board_info)); +} + diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c new file mode 100644 index 0000000..a90375d --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -0,0 +1,360 @@ +/* + * Copyright (C) 2009 Texas Instruments Inc. + * + * Modified from mach-omap2/board-zoom2.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/input.h> +#include <linux/input/matrix_keypad.h> +#include <linux/gpio.h> +#include <linux/i2c/twl.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/wl12xx.h> +#include <linux/mmc/host.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/platform_data/omap-twl4030.h> +#include <linux/usb/phy.h> +#include <linux/pwm.h> +#include <linux/leds_pwm.h> +#include <linux/pwm_backlight.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" + +#include "board-zoom.h" + +#include "mux.h" +#include "hsmmc.h" +#include "common-board-devices.h" + +#define OMAP_ZOOM_WLAN_PMENA_GPIO (101) +#define OMAP_ZOOM_TSC2004_IRQ_GPIO (153) +#define OMAP_ZOOM_WLAN_IRQ_GPIO (162) + +/* Zoom2 has Qwerty keyboard*/ +static uint32_t board_keymap[] = { + KEY(0, 0, KEY_E), + KEY(0, 1, KEY_R), + KEY(0, 2, KEY_T), + KEY(0, 3, KEY_HOME), + KEY(0, 6, KEY_I), + KEY(0, 7, KEY_LEFTSHIFT), + KEY(1, 0, KEY_D), + KEY(1, 1, KEY_F), + KEY(1, 2, KEY_G), + KEY(1, 3, KEY_SEND), + KEY(1, 6, KEY_K), + KEY(1, 7, KEY_ENTER), + KEY(2, 0, KEY_X), + KEY(2, 1, KEY_C), + KEY(2, 2, KEY_V), + KEY(2, 3, KEY_END), + KEY(2, 6, KEY_DOT), + KEY(2, 7, KEY_CAPSLOCK), + KEY(3, 0, KEY_Z), + KEY(3, 1, KEY_KPPLUS), + KEY(3, 2, KEY_B), + KEY(3, 3, KEY_F1), + KEY(3, 6, KEY_O), + KEY(3, 7, KEY_SPACE), + KEY(4, 0, KEY_W), + KEY(4, 1, KEY_Y), + KEY(4, 2, KEY_U), + KEY(4, 3, KEY_F2), + KEY(4, 4, KEY_VOLUMEUP), + KEY(4, 6, KEY_L), + KEY(4, 7, KEY_LEFT), + KEY(5, 0, KEY_S), + KEY(5, 1, KEY_H), + KEY(5, 2, KEY_J), + KEY(5, 3, KEY_F3), + KEY(5, 4, KEY_UNKNOWN), + KEY(5, 5, KEY_VOLUMEDOWN), + KEY(5, 6, KEY_M), + KEY(5, 7, KEY_RIGHT), + KEY(6, 0, KEY_Q), + KEY(6, 1, KEY_A), + KEY(6, 2, KEY_N), + KEY(6, 3, KEY_BACKSPACE), + KEY(6, 6, KEY_P), + KEY(6, 7, KEY_UP), + KEY(7, 0, KEY_PROG1), /*MACRO 1 <User defined> */ + KEY(7, 1, KEY_PROG2), /*MACRO 2 <User defined> */ + KEY(7, 2, KEY_PROG3), /*MACRO 3 <User defined> */ + KEY(7, 3, KEY_PROG4), /*MACRO 4 <User defined> */ + KEY(7, 6, KEY_SELECT), + KEY(7, 7, KEY_DOWN) +}; + +static struct matrix_keymap_data board_map_data = { + .keymap = board_keymap, + .keymap_size = ARRAY_SIZE(board_keymap), +}; + +static struct twl4030_keypad_data zoom_kp_twl4030_data = { + .keymap_data = &board_map_data, + .rows = 8, + .cols = 8, + .rep = 1, +}; + +static struct regulator_consumer_supply zoom_vmmc1_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), +}; + +static struct regulator_consumer_supply zoom_vsim_supply[] = { + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), +}; + +static struct regulator_consumer_supply zoom_vmmc2_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), +}; + +static struct regulator_consumer_supply zoom_vmmc3_supply[] = { + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"), +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data zoom_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply), + .consumer_supplies = zoom_vmmc1_supply, +}; + +/* VMMC2 for MMC2 card */ +static struct regulator_init_data zoom_vmmc2 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 1850000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply), + .consumer_supplies = zoom_vmmc2_supply, +}; + +/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ +static struct regulator_init_data zoom_vsim = { + .constraints = { + .min_uV = 1800000, + .max_uV = 3000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply), + .consumer_supplies = zoom_vsim_supply, +}; + +static struct regulator_init_data zoom_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply), + .consumer_supplies = zoom_vmmc3_supply, +}; + +static struct fixed_voltage_config zoom_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &zoom_vmmc3, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zoom_vwlan, + }, +}; + +static struct pwm_lookup zoom_pwm_lookup[] = { + PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "zoom::keypad"), + PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", "backlight"), +}; + +static struct led_pwm zoom_pwm_leds[] = { + { + .name = "zoom::keypad", + .max_brightness = 127, + .pwm_period_ns = 7812500, + }, +}; + +static struct led_pwm_platform_data zoom_pwm_data = { + .num_leds = ARRAY_SIZE(zoom_pwm_leds), + .leds = zoom_pwm_leds, +}; + +static struct platform_device zoom_leds_pwm = { + .name = "leds_pwm", + .id = -1, + .dev = { + .platform_data = &zoom_pwm_data, + }, +}; + +static struct platform_pwm_backlight_data zoom_backlight_data = { + .pwm_id = 1, + .max_brightness = 127, + .dft_brightness = 127, + .pwm_period_ns = 7812500, +}; + +static struct platform_device zoom_backlight_pwm = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &zoom_backlight_data, + }, +}; + +static struct platform_device *zoom_devices[] __initdata = { + &omap_vwlan_device, + &zoom_leds_pwm, + &zoom_backlight_pwm, +}; + +static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { + .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */ +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .name = "external", + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_wp = -EINVAL, + .power_saving = true, + .deferred = true, + }, + { + .name = "internal", + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .nonremovable = true, + .power_saving = true, + }, + { + .name = "wl1271", + .mmc = 3, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .nonremovable = true, + }, + {} /* Terminator */ +}; + +static struct omap_tw4030_pdata omap_twl4030_audio_data = { + .voice_connected = true, + .custom_routing = true, + + .has_hs = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT, + .has_hf = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT, + + .has_mainmic = true, + .has_submic = true, + .has_hsmic = true, + .has_linein = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT, +}; + +static int zoom_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + mmc[0].gpio_cd = gpio + 0; + omap_hsmmc_late_init(mmc); + + /* Audio setup */ + omap_twl4030_audio_data.jack_detect = gpio + 2; + omap_twl4030_audio_init("Zoom2", &omap_twl4030_audio_data); + + return 0; +} + +static struct twl4030_gpio_platform_data zoom_gpio_data = { + .setup = zoom_twl_gpio_setup, +}; + +static struct twl4030_platform_data zoom_twldata = { + /* platform_data for children goes here */ + .gpio = &zoom_gpio_data, + .keypad = &zoom_kp_twl4030_data, + .vmmc1 = &zoom_vmmc1, + .vmmc2 = &zoom_vmmc2, + .vsim = &zoom_vsim, +}; + +static int __init omap_i2c_init(void) +{ + omap3_pmic_get_config(&zoom_twldata, + TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI | + TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, + TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); + + if (machine_is_omap_zoom2()) + zoom_twldata.audio->codec->ramp_delay_value = 3; /* 161 ms */ + + omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; +} + +static void enable_board_wakeup_source(void) +{ + /* T2 interrupt line (keypad) */ + omap_mux_init_signal("sys_nirq", + OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); +} + +void __init zoom_peripherals_init(void) +{ + int ret; + + omap_zoom_wlan_data.irq = gpio_to_irq(OMAP_ZOOM_WLAN_IRQ_GPIO); + ret = wl12xx_set_platform_data(&omap_zoom_wlan_data); + + if (ret) + pr_err("error setting wl12xx data: %d\n", ret); + + omap_hsmmc_init(mmc); + omap_i2c_init(); + pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup)); + platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices)); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); + usb_musb_init(NULL); + enable_board_wakeup_source(); + omap_serial_init(); +} diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c new file mode 100644 index 0000000..1a3dd86 --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2009-2010 Texas Instruments Inc. + * Mikkel Christensen <mlc@ti.com> + * Felipe Balbi <balbi@ti.com> + * + * Modified from mach-omap2/board-ldp.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/input.h> +#include <linux/gpio.h> +#include <linux/i2c/twl.h> +#include <linux/mtd/nand.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include "common.h" + +#include "board-zoom.h" + +#include "board-flash.h" +#include "mux.h" +#include "sdram-micron-mt46h32m32lf-6.h" +#include "sdram-hynix-h8mbx00u0mer-0em.h" + +#define ZOOM3_EHCI_RESET_GPIO 64 + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#endif + +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + +static struct usbhs_phy_data phy_data[] __initdata = { + { + .port = 2, + .reset_gpio = ZOOM3_EHCI_RESET_GPIO, + .vcc_gpio = -EINVAL, + }, +}; + +static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, +}; + +static void __init omap_zoom_init(void) +{ + if (machine_is_omap_zoom2()) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + } else if (machine_is_omap_zoom3()) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); + omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); + + usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); + usbhs_init(&usbhs_bdata); + } + + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS, + NAND_BUSWIDTH_16, nand_default_timings); + zoom_debugboard_init(); + zoom_peripherals_init(); + + if (machine_is_omap_zoom2()) + omap_sdrc_init(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + else if (machine_is_omap_zoom3()) + omap_sdrc_init(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); + + zoom_display_init(); +} + +MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3430_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = omap_zoom_init, + .init_late = omap3430_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END + +MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3630_init_early, + .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = omap_zoom_init, + .init_late = omap3630_init_late, + .init_time = omap3_sync32k_timer_init, + .restart = omap3xxx_restart, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-zoom.h b/arch/arm/mach-omap2/board-zoom.h new file mode 100644 index 0000000..2e94869 --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom.h @@ -0,0 +1,10 @@ +/* + * Defines for zoom boards + */ +#include <video/omapdss.h> + +#define ZOOM_NAND_CS 0 + +extern int __init zoom_debugboard_init(void); +extern void __init zoom_peripherals_init(void); +extern void __init zoom_display_init(void); diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 3b05aea..334b767 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -381,42 +381,6 @@ static struct clk_hw_omap dpll4_ck_hw = { DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops); -static const struct clk_div_table dpll4_mx_ck_div_table[] = { - { .div = 1, .val = 1 }, - { .div = 2, .val = 2 }, - { .div = 3, .val = 3 }, - { .div = 4, .val = 4 }, - { .div = 5, .val = 5 }, - { .div = 6, .val = 6 }, - { .div = 7, .val = 7 }, - { .div = 8, .val = 8 }, - { .div = 9, .val = 9 }, - { .div = 10, .val = 10 }, - { .div = 11, .val = 11 }, - { .div = 12, .val = 12 }, - { .div = 13, .val = 13 }, - { .div = 14, .val = 14 }, - { .div = 15, .val = 15 }, - { .div = 16, .val = 16 }, - { .div = 17, .val = 17 }, - { .div = 18, .val = 18 }, - { .div = 19, .val = 19 }, - { .div = 20, .val = 20 }, - { .div = 21, .val = 21 }, - { .div = 22, .val = 22 }, - { .div = 23, .val = 23 }, - { .div = 24, .val = 24 }, - { .div = 25, .val = 25 }, - { .div = 26, .val = 26 }, - { .div = 27, .val = 27 }, - { .div = 28, .val = 28 }, - { .div = 29, .val = 29 }, - { .div = 30, .val = 30 }, - { .div = 31, .val = 31 }, - { .div = 32, .val = 32 }, - { .div = 0 }, -}; - DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, @@ -560,10 +524,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = { { .div = 0 } }; -DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, +DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, - 0, dpll4_mx_ck_div_table, NULL); + CLK_DIVIDER_ONE_BASED, NULL); static struct clk dpll4_m3x2_ck; @@ -883,10 +847,10 @@ static struct clk dpll3_m3x2_ck_3630 = { DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1); -DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, +DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, - 0, dpll4_mx_ck_div_table, NULL); + CLK_DIVIDER_ONE_BASED, NULL); static struct clk dpll4_m4x2_ck; @@ -905,8 +869,7 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { .clkdm_name = "dpll4_clkdm", }; -DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, - dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT); +DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops); static struct clk dpll4_m4x2_ck_3630 = { .name = "dpll4_m4x2_ck", @@ -914,7 +877,6 @@ static struct clk dpll4_m4x2_ck_3630 = { .parent_names = dpll4_m4x2_ck_parent_names, .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names), .ops = &dpll4_m5x2_ck_3630_ops, - .flags = CLK_SET_RATE_PARENT, }; DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, @@ -1006,9 +968,8 @@ static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = { .clkdm_name = "dss_clkdm", }; -DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1, - dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, - CLK_SET_RATE_PARENT); +DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, + aes2_ick_ops); static struct clk dss1_alwon_fck_3430es2; @@ -1022,9 +983,8 @@ static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { .clkdm_name = "dss_clkdm", }; -DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2, - dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops, - CLK_SET_RATE_PARENT); +DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, + aes2_ick_ops); static struct clk dss2_alwon_fck; @@ -3315,7 +3275,6 @@ static struct omap_clk omap36xx_clks[] = { static struct omap_clk omap34xx_omap36xx_clks[] = { CLK(NULL, "aes1_ick", &aes1_ick), CLK("omap_rng", "ick", &rng_ick), - CLK("omap3-rom-rng", "ick", &rng_ick), CLK(NULL, "sha11_ick", &sha11_ick), CLK(NULL, "des1_ick", &des1_ick), CLK(NULL, "cam_mclk", &cam_mclk), diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index ec0dc0b..b237950 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -830,8 +830,7 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, - CLK_SET_RATE_PARENT, +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, 0x0, NULL); diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index c78e893..25b1fee 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) apll_mask = EN_APLL_LOCKED << clk->enable_bit; - r = omap2xxx_cm_get_pll_status(); + r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); return ((r & apll_mask) == apll_mask) ? true : false; } @@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void) { u32 aplls, srate = 0; - aplls = omap2xxx_cm_get_pll_config(); + aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 3ff3254..d862010 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -60,7 +60,8 @@ unsigned long omap2xxx_clk_get_core_rate(void) core_clk = omap2_get_dpll_rate(dpll_core_ck); - v = omap2xxx_cm_get_core_clk_src(); + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v &= OMAP24XX_CORE_CLK_SRC_MASK; if (v == CORE_CLK_SRC_32K) core_clk = 32768; @@ -78,7 +79,8 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) { u32 high, low, core_clk_src; - core_clk_src = omap2xxx_cm_get_core_clk_src(); + core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ high = curr_prcm_set->dpll_speed * 2; @@ -118,7 +120,8 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, const struct dpll_data *dd; cur_rate = omap2xxx_clk_get_core_rate(); - mult = omap2xxx_cm_get_core_clk_src(); + mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult &= OMAP24XX_CORE_CLK_SRC_MASK; if ((rate == (cur_rate / 2)) && (mult == 2)) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); @@ -142,7 +145,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config(); + tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; if (rate > low) { tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index b935ed2..ae2b35e 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - u32 cur_rate, done_rate, bypass = 0; + u32 cur_rate, done_rate, bypass = 0, tmp; const struct prcm_config *prcm; unsigned long found_speed = 0; unsigned long flags; @@ -141,11 +141,23 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, else done_rate = CORE_CLK_SRC_DPLL; - omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu, - prcm->cm_clksel_dsp, - prcm->cm_clksel_gfx, - prcm->cm_clksel1_core, - prcm->cm_clksel_mdm); + /* MPU divider */ + omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); + + /* dsp + iva1 div(2420), iva2.1(2430) */ + omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, + OMAP24XX_DSP_MOD, CM_CLKSEL); + + omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + + /* Major subsystem dividers */ + tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + CM_CLKSEL1); + + if (cpu_is_omap2430()) + omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, + OMAP2430_MDM_MOD, CM_CLKSEL); /* x2 to enter omap2xxx_sdrc_init_params() */ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index c7c5d31..0c38ca9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -543,44 +543,6 @@ int omap2_clk_disable_autoidle_all(void) } /** - * omap2_clk_deny_idle - disable autoidle on an OMAP clock - * @clk: struct clk * to disable autoidle for - * - * Disable autoidle on an OMAP clock. - */ -int omap2_clk_deny_idle(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return -EINVAL; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - if (c->ops && c->ops->deny_idle) - c->ops->deny_idle(c); - return 0; -} - -/** - * omap2_clk_allow_idle - enable autoidle on an OMAP clock - * @clk: struct clk * to enable autoidle for - * - * Enable autoidle on an OMAP clock. - */ -int omap2_clk_allow_idle(struct clk *clk) -{ - struct clk_hw_omap *c; - - if (__clk_get_flags(clk) & CLK_IS_BASIC) - return -EINVAL; - - c = to_clk_hw_omap(__clk_get_hw(clk)); - if (c->ops && c->ops->allow_idle) - c->ops->allow_idle(c); - return 0; -} - -/** * omap2_clk_enable_init_clocks - prepare & enable a list of clocks * @clk_names: ptr to an array of strings of clock names to enable * @num_clocks: number of clock names in @clk_names diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 82916cc..7aa32cd 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -411,8 +411,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); -int omap2_clk_allow_idle(struct clk *clk); -int omap2_clk_deny_idle(struct clk *clk); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index f17f006..4b03394 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -132,7 +132,7 @@ struct clockdomain { u8 _flags; const u8 dep_bit; const u8 prcm_partition; - const u16 cm_inst; + const s16 cm_inst; const u16 clkdm_offs; struct clkdm_dep *wkdep_srcs; struct clkdm_dep *sleepdep_srcs; @@ -218,7 +218,6 @@ extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void __init omap54xx_clockdomains_init(void); extern void __init dra7xx_clockdomains_init(void); -void am43xx_clockdomains_init(void); extern void clkdm_add_autodeps(struct clockdomain *clkdm); extern void clkdm_del_autodeps(struct clockdomain *clkdm); @@ -227,7 +226,6 @@ extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; extern struct clkdm_ops omap4_clkdm_operations; extern struct clkdm_ops am33xx_clkdm_operations; -extern struct clkdm_ops am43xx_clkdm_operations; extern struct clkdm_dep gfx_24xx_wkdeps[]; extern struct clkdm_dep dsp_24xx_wkdeps[]; diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c deleted file mode 100644 index 6d71c60..0000000 --- a/arch/arm/mach-omap2/clockdomains43xx_data.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * AM43xx Clock domains framework - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/io.h> - -#include "clockdomain.h" -#include "prcm44xx.h" -#include "prcm43xx.h" - -static struct clockdomain l4_cefuse_43xx_clkdm = { - .name = "l4_cefuse_clkdm", - .pwrdm = { .name = "cefuse_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_CEFUSE_INST, - .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain mpu_43xx_clkdm = { - .name = "mpu_clkdm", - .pwrdm = { .name = "mpu_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_MPU_INST, - .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS, - .flags = CLKDM_CAN_HWSUP_SWSUP, -}; - -static struct clockdomain l4ls_43xx_clkdm = { - .name = "l4ls_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain tamper_43xx_clkdm = { - .name = "tamper_clkdm", - .pwrdm = { .name = "tamper_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_TAMPER_INST, - .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_rtc_43xx_clkdm = { - .name = "l4_rtc_clkdm", - .pwrdm = { .name = "rtc_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_RTC_INST, - .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain pruss_ocp_43xx_clkdm = { - .name = "pruss_ocp_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain ocpwp_l3_43xx_clkdm = { - .name = "ocpwp_l3_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l3s_tsc_43xx_clkdm = { - .name = "l3s_tsc_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_WKUP_INST, - .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain dss_43xx_clkdm = { - .name = "dss_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l3_aon_43xx_clkdm = { - .name = "l3_aon_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_WKUP_INST, - .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain emif_43xx_clkdm = { - .name = "emif_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_wkup_aon_43xx_clkdm = { - .name = "l4_wkup_aon_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_WKUP_INST, - .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS, -}; - -static struct clockdomain l3_43xx_clkdm = { - .name = "l3_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_wkup_43xx_clkdm = { - .name = "l4_wkup_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_WKUP_INST, - .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain cpsw_125mhz_43xx_clkdm = { - .name = "cpsw_125mhz_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain gfx_l3_43xx_clkdm = { - .name = "gfx_l3_clkdm", - .pwrdm = { .name = "gfx_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_GFX_INST, - .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l3s_43xx_clkdm = { - .name = "l3s_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .prcm_partition = AM43XX_CM_PARTITION, - .cm_inst = AM43XX_CM_PER_INST, - .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain *clockdomains_am43xx[] __initdata = { - &l4_cefuse_43xx_clkdm, - &mpu_43xx_clkdm, - &l4ls_43xx_clkdm, - &tamper_43xx_clkdm, - &l4_rtc_43xx_clkdm, - &pruss_ocp_43xx_clkdm, - &ocpwp_l3_43xx_clkdm, - &l3s_tsc_43xx_clkdm, - &dss_43xx_clkdm, - &l3_aon_43xx_clkdm, - &emif_43xx_clkdm, - &l4_wkup_aon_43xx_clkdm, - &l3_43xx_clkdm, - &l4_wkup_43xx_clkdm, - &cpsw_125mhz_43xx_clkdm, - &gfx_l3_43xx_clkdm, - &l3s_43xx_clkdm, - NULL -}; - -void __init am43xx_clockdomains_init(void) -{ - clkdm_register_platform_funcs(&am43xx_clkdm_operations); - clkdm_register_clkdms(clockdomains_am43xx); - clkdm_complete_init(); -} diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index ce25abb..6774a53 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -327,73 +327,6 @@ struct clkdm_ops omap2_clkdm_operations = { .clkdm_clk_disable = omap2xxx_clkdm_clk_disable, }; -int omap2xxx_cm_fclks_active(void) -{ - u32 f1, f2; - - f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - - return (f1 | f2) ? 1 : 0; -} - -int omap2xxx_cm_mpu_retention_allowed(void) -{ - u32 l; - - /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | - OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | - OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) - return 0; - /* Check for UART3. */ - l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - if (l & OMAP24XX_EN_UART3_MASK) - return 0; - - return 1; -} - -u32 omap2xxx_cm_get_core_clk_src(void) -{ - u32 v; - - v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - v &= OMAP24XX_CORE_CLK_SRC_MASK; - - return v; -} - -u32 omap2xxx_cm_get_core_pll_config(void) -{ - return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); -} - -u32 omap2xxx_cm_get_pll_config(void) -{ - return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); -} - -u32 omap2xxx_cm_get_pll_status(void) -{ - return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); -} - -void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) -{ - u32 tmp; - - omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL); - omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL); - omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL); - tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & - OMAP24XX_CLKSEL_DSS2_MASK; - omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); - if (cpu_is_omap2430()) - omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL); -} - /* * */ diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h index 891d81c..4cbb39b 100644 --- a/arch/arm/mach-omap2/cm2xxx.h +++ b/arch/arm/mach-omap2/cm2xxx.h @@ -62,14 +62,6 @@ extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, u8 *idlest_reg_id); -extern int omap2xxx_cm_fclks_active(void); -extern int omap2xxx_cm_mpu_retention_allowed(void); -extern u32 omap2xxx_cm_get_core_clk_src(void); -extern u32 omap2xxx_cm_get_core_pll_config(void); -extern u32 omap2xxx_cm_get_pll_config(void); -extern u32 omap2xxx_cm_get_pll_status(void); -extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, - u32 mdm); extern int __init omap2xxx_cm_init(void); diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index 40a22e5..325a515 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -48,13 +48,13 @@ /* Private functions */ /* Read a register in a CM instance */ -static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) +static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) { return __raw_readl(cm_base + inst + idx); } /* Write into a register in a CM */ -static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) +static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) { __raw_writel(val, cm_base + inst + idx); } @@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) * @c must be the unshifted value for CLKTRCTRL - i.e., this function * will handle the shift itself. */ -static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) +static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) { u32 v; @@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) * Returns true if the clockdomain referred to by (@inst, @cdoffs) * is in hardware-supervised idle mode, or 0 otherwise. */ -bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) +bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) { u32 v; @@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs) * Put a clockdomain referred to by (@inst, @cdoffs) into * hardware-supervised idle mode. No return value. */ -void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) +void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); } @@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs) * software-supervised idle mode, i.e., controlled manually by the * Linux OMAP clockdomain code. No return value. */ -void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) +void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); } @@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs) * Put a clockdomain referred to by (@inst, @cdoffs) into idle * No return value. */ -void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) +void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); } @@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs) * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, * waking it up. No return value. */ -void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs) +void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); } diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index cfb8891..9d1f4fc 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -377,13 +377,13 @@ #ifndef __ASSEMBLER__ -bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs); -void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs); -void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs); -void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs); -void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs); +extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs); extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index f6f0288..9061c30 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -636,28 +636,6 @@ void omap3_cm_restore_context(void) OMAP3_CM_CLKOUT_CTRL_OFFSET); } -void omap3_cm_save_scratchpad_contents(u32 *ptr) -{ - *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); - *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); - *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); - - /* - * As per erratum i671, ROM code does not respect the PER DPLL - * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. - * Then, in anycase, clear these bits to avoid extra latencies. - */ - *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & - ~OMAP3430_AUTO_PERIPH_DPLL_MASK; - *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); - *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); - *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); - *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); - *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); - *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); - *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); -} - /* * */ diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h index 8224c91..e8e146f 100644 --- a/arch/arm/mach-omap2/cm3xxx.h +++ b/arch/arm/mach-omap2/cm3xxx.h @@ -83,7 +83,6 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, extern void omap3_cm_save_context(void); extern void omap3_cm_restore_context(void); -extern void omap3_cm_save_scratchpad_contents(u32 *ptr); extern int __init omap3xxx_cm_init(void); diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 731ca13..f0290f5 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs) /* Public functions */ /* Read a register in a CM instance */ -u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) +u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) { BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || @@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx) } /* Write into a register in a CM instance */ -void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) +void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) { BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || part == OMAP4430_INVALID_PRCM_PARTITION || @@ -129,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx) } /* Read-modify-write a register in CM1. Caller must lock */ -u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, +u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, s16 idx) { u32 v; @@ -142,12 +142,12 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, return v; } -u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) +u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) { return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); } -u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx) +u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) { return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); } @@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) * @c must be the unshifted value for CLKTRCTRL - i.e., this function * will handle the shift itself. */ -static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) +static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) { u32 v; @@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs) * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) * is in hardware-supervised idle mode, or 0 otherwise. */ -bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) +bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) { u32 v; @@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs) * Put a clockdomain referred to by (@part, @inst, @cdoffs) into * hardware-supervised idle mode. No return value. */ -void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) +void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); } @@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs) * software-supervised idle mode, i.e., controlled manually by the * Linux OMAP clockdomain code. No return value. */ -void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) +void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); } @@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs) * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, * waking it up. No return value. */ -void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) +void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) { _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); } @@ -483,12 +483,3 @@ struct clkdm_ops omap4_clkdm_operations = { .clkdm_clk_enable = omap4_clkdm_clk_enable, .clkdm_clk_disable = omap4_clkdm_clk_disable, }; - -struct clkdm_ops am43xx_clkdm_operations = { - .clkdm_sleep = omap4_clkdm_sleep, - .clkdm_wakeup = omap4_clkdm_wakeup, - .clkdm_allow_idle = omap4_clkdm_allow_idle, - .clkdm_deny_idle = omap4_clkdm_deny_idle, - .clkdm_clk_enable = omap4_clkdm_clk_enable, - .clkdm_clk_disable = omap4_clkdm_clk_disable, -}; diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h index 7f56ea4..bd7bab8 100644 --- a/arch/arm/mach-omap2/cminst44xx.h +++ b/arch/arm/mach-omap2/cminst44xx.h @@ -11,11 +11,11 @@ #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H -bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs); -void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs); -void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs); -void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs); -void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs); +extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); +extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); @@ -27,14 +27,14 @@ extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, * In an ideal world, we would not export these low-level functions, * but this will probably take some time to fix properly */ -u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx); -void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx); -u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, - u16 inst, s16 idx); -u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, - s16 idx); -u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, - s16 idx); +extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); +extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); +extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, + s16 inst, s16 idx); +extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, + s16 idx); +extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, + s16 idx); extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask); diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index e30ef67..4a5684b 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -98,7 +98,6 @@ void am35xx_init_early(void); void ti81xx_init_early(void); void am33xx_init_early(void); void am43xx_init_early(void); -void am43xx_init_late(void); void omap4430_init_early(void); void omap5_init_early(void); void omap3_init_late(void); /* Do not use this one */ @@ -110,11 +109,8 @@ void omap35xx_init_late(void); void omap3630_init_late(void); void am35xx_init_late(void); void ti81xx_init_late(void); -void am33xx_init_late(void); -void omap5_init_late(void); int omap2_common_pm_late_init(void); void dra7xx_init_early(void); -void dra7xx_init_late(void); #ifdef CONFIG_SOC_BUS void omap_soc_device_init(void); @@ -292,13 +288,11 @@ static inline void omap4_cpu_resume(void) #endif -void pdata_quirks_init(struct of_device_id *); -void omap_pcs_legacy_init(int irq, void (*rearm)(void)); - struct omap_sdrc_params; extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); struct omap2_hsmmc_info; +extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); extern void omap_reserve(void); struct omap_hwmod; diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 44bb4d5..31e0dfe 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -46,7 +46,17 @@ struct omap3_scratchpad { struct omap3_scratchpad_prcm_block { u32 prm_clksrc_ctrl; u32 prm_clksel; - u32 cm_contents[11]; + u32 cm_clksel_core; + u32 cm_clksel_wkup; + u32 cm_clken_pll; + u32 cm_autoidle_pll; + u32 cm_clksel1_pll; + u32 cm_clksel2_pll; + u32 cm_clksel3_pll; + u32 cm_clken_pll_mpu; + u32 cm_autoidle_pll_mpu; + u32 cm_clksel1_pll_mpu; + u32 cm_clksel2_pll_mpu; u32 prcm_block_size; }; @@ -337,9 +347,34 @@ void omap3_save_scratchpad_contents(void) prcm_block_contents.prm_clksel = omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET); - - omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); - + prcm_block_contents.cm_clksel_core = + omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); + prcm_block_contents.cm_clksel_wkup = + omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); + prcm_block_contents.cm_clken_pll = + omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. + * Then, in anycase, clear these bits to avoid extra latencies. + */ + prcm_block_contents.cm_autoidle_pll = + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & + ~OMAP3430_AUTO_PERIPH_DPLL_MASK; + prcm_block_contents.cm_clksel1_pll = + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); + prcm_block_contents.cm_clksel2_pll = + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); + prcm_block_contents.cm_clksel3_pll = + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); + prcm_block_contents.cm_clken_pll_mpu = + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); + prcm_block_contents.cm_autoidle_pll_mpu = + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); + prcm_block_contents.cm_clksel1_pll_mpu = + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); + prcm_block_contents.cm_clksel2_pll_mpu = + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.prcm_block_size = 0x0; /* Populate the SDRC block contents */ @@ -569,15 +604,4 @@ int omap3_ctrl_save_padconf(void) return 0; } -/** - * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle - * - * Sets the bootmode for IVA2 to idle. This is needed by the PM code to - * force disable IVA2 so that it does not prevent any low-power states. - */ -void omap3_ctrl_set_iva_bootmode_idle(void) -{ - omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, - OMAP343X_CONTROL_IVA2_BOOTMOD); -} #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index da05480..f7d7c2e 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -427,7 +427,6 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); -extern void omap3_ctrl_set_iva_bootmode_idle(void); extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); #else diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 0dd6398..5c5315b 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -19,6 +19,7 @@ #include <linux/of.h> #include <linux/pinctrl/machine.h> #include <linux/platform_data/omap4-keypad.h> +#include <linux/wl12xx.h> #include <linux/platform_data/mailbox-omap.h> #include <asm/mach-types.h> @@ -36,7 +37,6 @@ #include "mux.h" #include "control.h" #include "devices.h" -#include "display.h" #define L3_MODULES_MAX_LEN 12 #define L3_MODULES 3 @@ -466,13 +466,47 @@ static struct platform_device omap_vout_device = { .resource = &omap_vout_resource[0], .id = -1, }; +static void omap_init_vout(void) +{ + if (platform_device_register(&omap_vout_device) < 0) + printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); +} +#else +static inline void omap_init_vout(void) {} +#endif + +#if IS_ENABLED(CONFIG_WL12XX) -int __init omap_init_vout(void) +static struct wl12xx_platform_data wl12xx __initdata; + +void __init omap_init_wl12xx_of(void) { - return platform_device_register(&omap_vout_device); + int ret; + + if (!of_have_populated_dt()) + return; + + if (of_machine_is_compatible("ti,omap4-sdp")) { + wl12xx.board_ref_clock = WL12XX_REFCLOCK_26; + wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26; + wl12xx.irq = gpio_to_irq(53); + } else if (of_machine_is_compatible("ti,omap4-panda")) { + wl12xx.board_ref_clock = WL12XX_REFCLOCK_38; + wl12xx.irq = gpio_to_irq(53); + } else { + return; + } + + ret = wl12xx_set_platform_data(&wl12xx); + if (ret) { + pr_err("error setting wl12xx data: %d\n", ret); + return; + } } #else -int __init omap_init_vout(void) { return 0; } +static inline void omap_init_wl12xx_of(void) +{ +} #endif /*-------------------------------------------------------------------------*/ @@ -497,8 +531,12 @@ static int __init omap2_init_devices(void) omap_init_sham(); omap_init_aes(); omap_init_rng(); + } else { + /* These can be removed when bindings are done */ + omap_init_wl12xx_of(); } omap_init_sti(); + omap_init_vout(); return 0; } diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 58347bb..03a0516 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -32,6 +32,7 @@ #include "soc.h" #include "iomap.h" +#include "mux.h" #include "control.h" #include "display.h" #include "prm.h" @@ -101,13 +102,90 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { { "dss_hdmi", "omapdss_hdmi", -1 }, }; +static void __init omap4_tpd12s015_mux_pads(void) +{ + omap_mux_init_signal("hdmi_cec", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_scl", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("hdmi_ddc_sda", + OMAP_PIN_INPUT_PULLUP); +} + +static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags) +{ + u32 reg; + u16 control_i2c_1; + + /* + * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and + * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable + * internal pull up resistor. + */ + if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) { + control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1; + reg = omap4_ctrl_pad_readl(control_i2c_1); + reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK | + OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK); + omap4_ctrl_pad_writel(reg, control_i2c_1); + } +} + +static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) +{ + u32 enable_mask, enable_shift; + u32 pipd_mask, pipd_shift; + u32 reg; + + if (dsi_id == 0) { + enable_mask = OMAP4_DSI1_LANEENABLE_MASK; + enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; + pipd_mask = OMAP4_DSI1_PIPD_MASK; + pipd_shift = OMAP4_DSI1_PIPD_SHIFT; + } else if (dsi_id == 1) { + enable_mask = OMAP4_DSI2_LANEENABLE_MASK; + enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; + pipd_mask = OMAP4_DSI2_PIPD_MASK; + pipd_shift = OMAP4_DSI2_PIPD_SHIFT; + } else { + return -ENODEV; + } + + reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); + + reg &= ~enable_mask; + reg &= ~pipd_mask; + + reg |= (lanes << enable_shift) & enable_mask; + reg |= (lanes << pipd_shift) & pipd_mask; + + omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); + + return 0; +} + +int __init omap_hdmi_init(enum omap_hdmi_flags flags) +{ + if (cpu_is_omap44xx()) { + omap4_hdmi_mux_pads(flags); + omap4_tpd12s015_mux_pads(); + } + + return 0; +} + static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) { + if (cpu_is_omap44xx()) + return omap4_dsi_mux_pads(dsi_id, lane_mask); + return 0; } static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) { + if (cpu_is_omap44xx()) + omap4_dsi_mux_pads(dsi_id, 0); } static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) @@ -338,34 +416,6 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) } } - /* create DRM device */ - r = omap_init_drm(); - if (r < 0) { - pr_err("Unable to register omapdrm device\n"); - return r; - } - - /* create vrfb device */ - r = omap_init_vrfb(); - if (r < 0) { - pr_err("Unable to register omapvrfb device\n"); - return r; - } - - /* create FB device */ - r = omap_init_fb(); - if (r < 0) { - pr_err("Unable to register omapfb device\n"); - return r; - } - - /* create V4L2 display device */ - r = omap_init_vout(); - if (r < 0) { - pr_err("Unable to register omap_vout device\n"); - return r; - } - return 0; } diff --git a/arch/arm/mach-omap2/display.h b/arch/arm/mach-omap2/display.h index f3d2ce4..b871b017 100644 --- a/arch/arm/mach-omap2/display.h +++ b/arch/arm/mach-omap2/display.h @@ -26,8 +26,4 @@ struct omap_dss_dispc_dev_attr { bool has_framedonetv_irq; }; -int omap_init_drm(void); -int omap_init_vrfb(void); -int omap_init_fb(void); -int omap_init_vout(void); #endif diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c index facd740..59a4af7 100644 --- a/arch/arm/mach-omap2/drm.c +++ b/arch/arm/mach-omap2/drm.c @@ -26,9 +26,10 @@ #include <linux/platform_data/omap_drm.h> #include "soc.h" -#include "display.h" +#include "omap_device.h" +#include "omap_hwmod.h" -#if defined(CONFIG_DRM_OMAP) || defined(CONFIG_DRM_OMAP_MODULE) +#if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE) static struct omap_drm_platform_data platform_data; @@ -41,13 +42,26 @@ static struct platform_device omap_drm_device = { .id = 0, }; -int __init omap_init_drm(void) +static int __init omap_init_drm(void) { + struct omap_hwmod *oh = NULL; + struct platform_device *pdev; + + /* lookup and populate the DMM information, if present - OMAP4+ */ + oh = omap_hwmod_lookup("dmm"); + + if (oh) { + pdev = omap_device_build(oh->name, -1, oh, NULL, 0); + WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", + oh->name); + } + platform_data.omaprev = GET_OMAP_TYPE; return platform_device_register(&omap_drm_device); } -#else -int __init omap_init_drm(void) { return 0; } + +omap_arch_initcall(omap_init_drm); + #endif diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c index dadccc9..bf89eff 100644 --- a/arch/arm/mach-omap2/dss-common.c +++ b/arch/arm/mach-omap2/dss-common.c @@ -213,47 +213,3 @@ void __init omap_4430sdp_display_init_of(void) platform_device_register(&sdp4430_tpd_device); platform_device_register(&sdp4430_hdmi_connector_device); } - - -/* OMAP3 IGEPv2 data */ - -#define IGEP2_DVI_TFP410_POWER_DOWN_GPIO 170 - -/* DVI Connector */ -static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = { - .name = "dvi", - .source = "tfp410.0", - .i2c_bus_num = 2, -}; - -static struct platform_device omap3_igep2_dvi_connector_device = { - .name = "connector-dvi", - .id = 0, - .dev.platform_data = &omap3_igep2_dvi_connector_pdata, -}; - -/* TFP410 DPI-to-DVI chip */ -static struct encoder_tfp410_platform_data omap3_igep2_tfp410_pdata = { - .name = "tfp410.0", - .source = "dpi.0", - .data_lines = 24, - .power_down_gpio = IGEP2_DVI_TFP410_POWER_DOWN_GPIO, -}; - -static struct platform_device omap3_igep2_tfp410_device = { - .name = "tfp410", - .id = 0, - .dev.platform_data = &omap3_igep2_tfp410_pdata, -}; - -static struct omap_dss_board_info igep2_dss_data = { - .default_display_name = "dvi", -}; - -void __init omap3_igep2_display_init_of(void) -{ - omap_display_init(&igep2_dss_data); - - platform_device_register(&omap3_igep2_tfp410_device); - platform_device_register(&omap3_igep2_dvi_connector_device); -} diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h index a9becf0..c28fe3c 100644 --- a/arch/arm/mach-omap2/dss-common.h +++ b/arch/arm/mach-omap2/dss-common.h @@ -8,6 +8,5 @@ void __init omap4_panda_display_init_of(void); void __init omap_4430sdp_display_init_of(void); -void __init omap3_igep2_display_init_of(void); #endif diff --git a/arch/arm/mach-omap2/fb.c b/arch/arm/mach-omap2/fb.c index 26e28e9..2ca33cc 100644 --- a/arch/arm/mach-omap2/fb.c +++ b/arch/arm/mach-omap2/fb.c @@ -32,7 +32,6 @@ #include <asm/mach/map.h> #include "soc.h" -#include "display.h" #ifdef CONFIG_OMAP2_VRFB @@ -65,7 +64,7 @@ static const struct resource omap3_vrfb_resources[] = { DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"), }; -int __init omap_init_vrfb(void) +static int __init omap_init_vrfb(void) { struct platform_device *pdev; const struct resource *res; @@ -86,8 +85,8 @@ int __init omap_init_vrfb(void) return PTR_RET(pdev); } -#else -int __init omap_init_vrfb(void) { return 0; } + +omap_arch_initcall(omap_init_vrfb); #endif #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) @@ -106,10 +105,11 @@ static struct platform_device omap_fb_device = { .num_resources = 0, }; -int __init omap_init_fb(void) +static int __init omap_init_fb(void) { return platform_device_register(&omap_fb_device); } -#else -int __init omap_init_fb(void) { return 0; } + +omap_arch_initcall(omap_init_fb); + #endif diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c index 2757504..ef99011 100644 --- a/arch/arm/mach-omap2/gpmc-smsc911x.c +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c @@ -83,7 +83,7 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg) pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id, gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources), &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config)); - if (IS_ERR(pdev)) { + if (!pdev) { pr_err("Unable to register platform device\n"); gpio_free(gpmc_cfg->gpio_reset); goto free2; diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index d24926e..579697a 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1341,6 +1341,14 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, #ifdef CONFIG_MTD_NAND +static const char * const nand_ecc_opts[] = { + [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw", + [OMAP_ECC_HAMMING_CODE_HW] = "hw", + [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode", + [OMAP_ECC_BCH4_CODE_HW] = "bch4", + [OMAP_ECC_BCH8_CODE_HW] = "bch8", +}; + static const char * const nand_xfer_types[] = { [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", [NAND_OMAP_POLLED] = "polled", @@ -1370,41 +1378,13 @@ static int gpmc_probe_nand_child(struct platform_device *pdev, gpmc_nand_data->cs = val; gpmc_nand_data->of_node = child; - /* Detect availability of ELM module */ - gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); - if (gpmc_nand_data->elm_of_node == NULL) - gpmc_nand_data->elm_of_node = - of_parse_phandle(child, "elm_id", 0); - if (gpmc_nand_data->elm_of_node == NULL) - pr_warn("%s: ti,elm-id property not found\n", __func__); - - /* select ecc-scheme for NAND */ - if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { - pr_err("%s: ti,nand-ecc-opt not found\n", __func__); - return -ENODEV; - } - if (!strcmp(s, "ham1") || !strcmp(s, "sw") || - !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) - gpmc_nand_data->ecc_opt = - OMAP_ECC_HAM1_CODE_HW; - else if (!strcmp(s, "bch4")) - if (gpmc_nand_data->elm_of_node) - gpmc_nand_data->ecc_opt = - OMAP_ECC_BCH4_CODE_HW; - else - gpmc_nand_data->ecc_opt = - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; - else if (!strcmp(s, "bch8")) - if (gpmc_nand_data->elm_of_node) - gpmc_nand_data->ecc_opt = - OMAP_ECC_BCH8_CODE_HW; - else - gpmc_nand_data->ecc_opt = - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; - else - pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__); + if (!of_property_read_string(child, "ti,nand-ecc-opt", &s)) + for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++) + if (!strcasecmp(s, nand_ecc_opts[val])) { + gpmc_nand_data->ecc_opt = val; + break; + } - /* select data transfer mode for NAND controller */ if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++) if (!strcasecmp(s, nand_xfer_types[val])) { @@ -1502,22 +1482,6 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, } /* - * For some GPMC devices we still need to rely on the bootloader - * timings because the devices can be connected via FPGA. So far - * the list is smc91x on the omap2 SDP boards, and 8250 on zooms. - * REVISIT: Add timing support from slls644g.pdf and from the - * lan91c96 manual. - */ - if (of_device_is_compatible(child, "ns16550a") || - of_device_is_compatible(child, "smsc,lan91c94") || - of_device_is_compatible(child, "smsc,lan91c111")) { - dev_warn(&pdev->dev, - "%s using bootloader timings on CS%d\n", - child->name, cs); - goto no_timings; - } - - /* * FIXME: gpmc_cs_request() will map the CS to an arbitary * location in the gpmc address space. When booting with * device-tree we want the NOR flash to be mapped to the @@ -1545,7 +1509,6 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, gpmc_read_timings_dt(child, &gpmc_t); gpmc_cs_set_timings(cs, &gpmc_t); -no_timings: if (of_platform_device_create(child, NULL, &pdev->dev)) return 0; @@ -1599,8 +1562,7 @@ static int gpmc_probe_dt(struct platform_device *pdev) else if (of_node_cmp(child->name, "onenand") == 0) ret = gpmc_probe_onenand_child(pdev, child); else if (of_node_cmp(child->name, "ethernet") == 0 || - of_node_cmp(child->name, "nor") == 0 || - of_node_cmp(child->name, "uart") == 0) + of_node_cmp(child->name, "nor") == 0) ret = gpmc_probe_generic_child(pdev, child); if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 9428c5f..0289adc 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -18,7 +18,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/random.h> #include <linux/slab.h> #ifdef CONFIG_SOC_BUS @@ -131,17 +130,6 @@ void omap_get_die_id(struct omap_die_id *odi) odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); } -static int __init omap_feed_randpool(void) -{ - struct omap_die_id odi; - - /* Throw the die ID into the entropy pool at boot */ - omap_get_die_id(&odi); - add_device_randomness(&odi, sizeof(odi)); - return 0; -} -omap_device_initcall(omap_feed_randpool); - void __init omap2xxx_check_revision(void) { int i, j; @@ -588,8 +576,8 @@ void __init omap5xxx_check_revision(void) case 0xb942: switch (rev) { case 0: - /* No support for ES1.0 Test chip */ - BUG(); + omap_revision = OMAP5430_REV_ES1_0; + break; case 1: default: omap_revision = OMAP5430_REV_ES2_0; @@ -599,8 +587,8 @@ void __init omap5xxx_check_revision(void) case 0xb998: switch (rev) { case 0: - /* No support for ES1.0 Test chip */ - BUG(); + omap_revision = OMAP5432_REV_ES1_0; + break; case 1: default: omap_revision = OMAP5432_REV_ES2_0; diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cd22262..ff2113c 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -583,11 +583,6 @@ void __init am33xx_init_early(void) omap_hwmod_init_postsetup(); omap_clk_init = am33xx_clk_init; } - -void __init am33xx_init_late(void) -{ - omap_common_late_init(); -} #endif #ifdef CONFIG_SOC_AM43XX @@ -599,18 +594,7 @@ void __init am43xx_init_early(void) NULL); omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); - omap_prm_base_init(); - omap_cm_base_init(); omap3xxx_check_revision(); - am43xx_powerdomains_init(); - am43xx_clockdomains_init(); - am43xx_hwmod_init(); - omap_hwmod_init_postsetup(); -} - -void __init am43xx_init_late(void) -{ - omap_common_late_init(); } #endif @@ -667,11 +651,6 @@ void __init omap5_init_early(void) omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); } - -void __init omap5_init_late(void) -{ - omap_common_late_init(); -} #endif #ifdef CONFIG_SOC_DRA7XX @@ -692,11 +671,6 @@ void __init dra7xx_init_early(void) dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); } - -void __init dra7xx_init_late(void) -{ - omap_common_late_init(); -} #endif diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index e022a86..3926f37 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -233,7 +233,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs goto out; irqnr = readl_relaxed(base_addr + 0xd8); -#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX) +#ifdef CONFIG_SOC_TI81XX if (irqnr) goto out; irqnr = readl_relaxed(base_addr + 0xf8); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index b4ac3af..5d87680 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -25,7 +25,6 @@ #include "soc.h" #include "omap_device.h" -#include "clock.h" /* * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. @@ -34,18 +33,22 @@ #include "cm3xxx.h" #include "cm-regbits-34xx.h" -static struct clk *mcbsp_iclks[5]; - static int omap3_enable_st_clock(unsigned int id, bool enable) { + unsigned int w; + /* * Sidetone uses McBSP ICLK - which must not idle when sidetones * are enabled or sidetones start sounding ugly. */ + w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); if (enable) - return omap2_clk_deny_idle(mcbsp_iclks[id]); + w &= ~(1 << (id - 2)); else - return omap2_clk_allow_idle(mcbsp_iclks[id]); + w |= 1 << (id - 2); + omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + + return 0; } static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) @@ -55,7 +58,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) struct omap_hwmod *oh_device[2]; struct omap_mcbsp_platform_data *pdata = NULL; struct platform_device *pdev; - char clk_name[11]; sscanf(oh->name, "mcbsp%d", &id); @@ -97,8 +99,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) oh_device[1] = omap_hwmod_lookup(( (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); pdata->enable_st_clock = omap3_enable_st_clock; - sprintf(clk_name, "mcbsp%d_ick", id); - mcbsp_iclks[id] = clk_get(NULL, clk_name); count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 48094b5..f82cf87 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -811,12 +811,6 @@ int __init omap_mux_late_init(void) } } - omap_mux_dbg_init(); - - /* see pinctrl-single-omap for the wake-up interrupt handling */ - if (of_have_populated_dt()) - return 0; - ret = request_irq(omap_prcm_event_to_irq("io"), omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND, "hwmod_io", omap_mux_late_init); @@ -824,6 +818,8 @@ int __init omap_mux_late_init(void) if (ret) pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); + omap_mux_dbg_init(); + return 0; } diff --git a/arch/arm/mach-omap2/omap-pm.h b/arch/arm/mach-omap2/omap-pm.h index 1d777e6..67faa7b 100644 --- a/arch/arm/mach-omap2/omap-pm.h +++ b/arch/arm/mach-omap2/omap-pm.h @@ -17,7 +17,7 @@ #include <linux/device.h> #include <linux/cpufreq.h> #include <linux/clk.h> -#include <linux/pm_opp.h> +#include <linux/opp.h> /* * agent_id values for use with omap_pm_set_min_bus_tput(): diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 5ac122e..b970440 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -3,8 +3,6 @@ * * Copyright (C) 2011 Texas Instruments, Inc. * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> - * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> * * * This program is free software,you can redistribute it and/or modify @@ -72,77 +70,3 @@ phys_addr_t omap_secure_ram_mempool_base(void) { return omap_secure_memblock_base; } - -/** - * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls - * @idx: The PPA API index - * @process: Process ID - * @flag: The flag indicating criticality of operation - * @nargs: Number of valid arguments out of four. - * @arg1, arg2, arg3 args4: Parameters passed to secure API - * - * Return the non-zero error value on failure. - * - * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because - * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1 - */ -u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, - u32 arg1, u32 arg2, u32 arg3, u32 arg4) -{ - u32 ret; - u32 param[5]; - - param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */ - param[1] = arg1; - param[2] = arg2; - param[3] = arg3; - param[4] = arg4; - - /* - * Secure API needs physical address - * pointer for the parameters - */ - local_irq_disable(); - local_fiq_disable(); - flush_cache_all(); - outer_clean_range(__pa(param), __pa(param + 5)); - ret = omap_smc3(idx, process, flag, __pa(param)); - flush_cache_all(); - local_fiq_enable(); - local_irq_enable(); - - return ret; -} - -/** - * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register - * @set_bits: bits to set in ACR - * @clr_bits: bits to clear in ACR - * - * Return the non-zero error value on failure. -*/ -u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR, - 0, - FLAG_START_CRITICAL, - 1, acr, 0, 0, 0); -} - -/** - * rx51_secure_rng_call: Routine for HW random generator - */ -u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) -{ - return rx51_secure_dispatcher(RX51_PPA_HWRNG, - 0, - NO_FLAG, - 3, ptr, count, flag, 0); -} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 3e97c6c..0e72917 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -3,8 +3,6 @@ * * Copyright (C) 2011 Texas Instruments, Inc. * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> - * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -44,45 +42,23 @@ #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 -#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 - /* Secure PPA(Primary Protected Application) APIs */ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 -/* Secure RX-51 PPA (Primary Protected Application) APIs */ -#define RX51_PPA_HWRNG 29 -#define RX51_PPA_L2_INVAL 40 -#define RX51_PPA_WRITE_ACR 42 - #ifndef __ASSEMBLER__ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); -extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); extern int omap_secure_ram_reserve_memblock(void); -extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, - u32 arg1, u32 arg2, u32 arg3, u32 arg4); -extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); -extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); - #ifdef CONFIG_OMAP4_ERRATA_I688 extern int omap_barrier_reserve_memblock(void); #else static inline void omap_barrier_reserve_memblock(void) { } #endif - -#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER -void set_cntfreq(void); -#else -static inline void set_cntfreq(void) -{ -} -#endif - #endif /* __ASSEMBLER__ */ #endif /* OMAP_ARCH_OMAP_SECURE_H */ diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index fd90125..f6441c1 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -1,11 +1,9 @@ /* - * OMAP34xx and OMAP44xx secure APIs file. + * OMAP44xx secure APIs file. * * Copyright (C) 2010 Texas Instruments, Inc. * Written by Santosh Shilimkar <santosh.shilimkar@ti.com> * - * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> - * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> * * This program is free software,you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -56,23 +54,6 @@ ENTRY(omap_smc2) ldmfd sp!, {r4-r12, pc} ENDPROC(omap_smc2) -/** - * u32 omap_smc3(u32 service_id, u32 process_id, u32 flag, u32 pargs) - * Low level common routine for secure HAL and PPA APIs via smc #1 - * r0 - @service_id: Secure Service ID - * r1 - @process_id: Process ID - * r2 - @flag: Flag to indicate the criticality of operation - * r3 - @pargs: Physical address of parameter list - */ -ENTRY(omap_smc3) - stmfd sp!, {r4-r11, lr} - mov r12, r0 @ Copy the secure service ID - mov r6, #0xff @ Indicate new Task call - dsb @ Memory Barrier (not sure if needed, copied from omap_smc2) - smc #1 @ Call PPA service - ldmfd sp!, {r4-r11, pc} -ENDPROC(omap_smc3) - ENTRY(omap_modify_auxcoreboot0) stmfd sp!, {r1-r12, lr} ldr r12, =0x104 diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 75e95d4..8912110 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -66,13 +66,6 @@ static void omap4_secondary_init(unsigned int cpu) 4, 0, 0, 0, 0, 0); /* - * Configure the CNTFRQ register for the secondary cpu's which - * indicates the frequency of the cpu local timers. - */ - if (soc_is_omap54xx() || soc_is_dra7xx()) - set_cntfreq(); - - /* * Synchronise with the boot thread. */ spin_lock(&boot_lock); diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 3664562..813c615 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -33,12 +33,8 @@ #include "omap4-sar-layout.h" #include "common.h" -#define AM43XX_NR_REG_BANKS 7 -#define AM43XX_IRQS 224 -#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS -#define MAX_IRQS AM43XX_IRQS -#define DEFAULT_NR_REG_BANKS 5 -#define DEFAULT_IRQS 160 +#define MAX_NR_REG_BANKS 5 +#define MAX_IRQS 160 #define WKG_MASK_ALL 0x00000000 #define WKG_UNMASK_ALL 0xffffffff #define CPU_ENA_OFFSET 0x400 @@ -51,8 +47,8 @@ static void __iomem *wakeupgen_base; static void __iomem *sar_base; static DEFINE_RAW_SPINLOCK(wakeupgen_lock); static unsigned int irq_target_cpu[MAX_IRQS]; -static unsigned int irq_banks = DEFAULT_NR_REG_BANKS; -static unsigned int max_irqs = DEFAULT_IRQS; +static unsigned int irq_banks = MAX_NR_REG_BANKS; +static unsigned int max_irqs = MAX_IRQS; static unsigned int omap_secure_apis; /* @@ -422,16 +418,12 @@ int __init omap_wakeupgen_init(void) irq_banks = OMAP4_NR_BANKS; max_irqs = OMAP4_NR_IRQS; omap_secure_apis = 1; - } else if (soc_is_am43xx()) { - irq_banks = AM43XX_NR_REG_BANKS; - max_irqs = AM43XX_IRQS; } /* Clear all IRQ bitmasks at wakeupGen level */ for (i = 0; i < irq_banks; i++) { wakeupgen_writel(0, i, CPU0_ID); - if (!soc_is_am43xx()) - wakeupgen_writel(0, i, CPU1_ID); + wakeupgen_writel(0, i, CPU1_ID); } /* diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index b39efd4..5791143 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -35,6 +35,7 @@ #include "iomap.h" #include "common.h" #include "mmc.h" +#include "hsmmc.h" #include "prminst44xx.h" #include "prcm_mpu44xx.h" #include "omap4-sar-layout.h" @@ -283,3 +284,59 @@ skip_errata_init: omap_wakeupgen_init(); irqchip_init(); } + +#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int irq = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) { + irq = twl6030_mmc_card_detect_config(); + if (irq < 0) { + dev_err(dev, "%s: Error card detect config(%d)\n", + __func__, irq); + return irq; + } + pdata->slots[0].card_detect_irq = irq; + pdata->slots[0].card_detect = twl6030_mmc_card_detect; + } + return 0; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata; + + /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!dev) { + pr_err("Failed %s\n", __func__); + return; + } + pdata = dev->platform_data; + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) { + /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!c->pdev) + continue; + omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev); + } + + return 0; +} +#else +int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 53f0735..b69dd9a 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -621,7 +621,6 @@ static int _od_suspend_noirq(struct device *dev) if (!ret && !pm_runtime_status_suspended(dev)) { if (pm_generic_runtime_suspend(dev) == 0) { - pm_runtime_set_suspended(dev); omap_device_idle(pdev); od->flags |= OMAP_DEVICE_SUSPENDED; } @@ -635,18 +634,10 @@ static int _od_resume_noirq(struct device *dev) struct platform_device *pdev = to_platform_device(dev); struct omap_device *od = to_omap_device(pdev); - if (od->flags & OMAP_DEVICE_SUSPENDED) { + if ((od->flags & OMAP_DEVICE_SUSPENDED) && + !pm_runtime_status_suspended(dev)) { od->flags &= ~OMAP_DEVICE_SUSPENDED; omap_device_enable(pdev); - /* - * XXX: we run before core runtime pm has resumed itself. At - * this point in time, we just restore the runtime pm state and - * considering symmetric operations in resume, we donot expect - * to fail. If we failed, something changed in core runtime_pm - * framework OR some device driver messed things up, hence, WARN - */ - WARN(pm_runtime_set_active(dev), - "Could not set %s runtime state active\n", dev_name(dev)); pm_generic_runtime_resume(dev); } diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e3f0eca..d9ee0ff 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2357,29 +2357,25 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np, /** * _init_mpu_rt_base - populate the virtual address for a hwmod * @oh: struct omap_hwmod * to locate the virtual address - * @data: (unused, caller should pass NULL) - * @np: struct device_node * of the IP block's device node in the DT data * * Cache the virtual address used by the MPU to access this IP block's * registers. This address is needed early so the OCP registers that * are part of the device's address space can be ioremapped properly. - * - * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and - * -ENXIO on absent or invalid register target address space. + * No return value. */ -static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, - struct device_node *np) +static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) { struct omap_hwmod_addr_space *mem; void __iomem *va_start = NULL; + struct device_node *np; if (!oh) - return -EINVAL; + return; _save_mpu_port_index(oh); if (oh->_int_flags & _HWMOD_NO_MPU_PORT) - return -ENXIO; + return; mem = _find_mpu_rt_addr_space(oh); if (!mem) { @@ -2387,24 +2383,25 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, oh->name); /* Extract the IO space from device tree blob */ - if (!np) - return -ENXIO; + if (!of_have_populated_dt()) + return; - va_start = of_iomap(np, oh->mpu_rt_idx); + np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); + if (np) + va_start = of_iomap(np, oh->mpu_rt_idx); } else { va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); } if (!va_start) { pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); - return -ENXIO; + return; } pr_debug("omap_hwmod: %s: MPU register target at va %p\n", oh->name, va_start); oh->_mpu_rt_va = va_start; - return 0; } /** @@ -2417,28 +2414,18 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, * registered at this point. This is the first of two phases for * hwmod initialization. Code called here does not touch any hardware * registers, it simply prepares internal data structures. Returns 0 - * upon success or if the hwmod isn't registered or if the hwmod's - * address space is not defined, or -EINVAL upon failure. + * upon success or if the hwmod isn't registered, or -EINVAL upon + * failure. */ static int __init _init(struct omap_hwmod *oh, void *data) { int r; - struct device_node *np = NULL; if (oh->_state != _HWMOD_STATE_REGISTERED) return 0; - if (of_have_populated_dt()) - np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); - - if (oh->class->sysc) { - r = _init_mpu_rt_base(oh, NULL, np); - if (r < 0) { - WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", - oh->name); - return 0; - } - } + if (oh->class->sysc) + _init_mpu_rt_base(oh, NULL); r = _init_clocks(oh, NULL); if (r < 0) { @@ -2446,12 +2433,6 @@ static int __init _init(struct omap_hwmod *oh, void *data) return -EINVAL; } - if (np) - if (of_find_property(np, "ti,no-reset-on-init", NULL)) - oh->flags |= HWMOD_INIT_NO_RESET; - if (of_find_property(np, "ti,no-idle-on-init", NULL)) - oh->flags |= HWMOD_INIT_NO_IDLE; - oh->_state = _HWMOD_STATE_INITIALIZED; return 0; @@ -4144,14 +4125,6 @@ void __init omap_hwmod_init(void) soc_ops.init_clkdm = _init_clkdm; soc_ops.update_context_lost = _omap4_update_context_lost; soc_ops.get_context_lost = _omap4_get_context_lost; - } else if (soc_is_am43xx()) { - soc_ops.enable_module = _omap4_enable_module; - soc_ops.disable_module = _omap4_disable_module; - soc_ops.wait_target_ready = _omap4_wait_target_ready; - soc_ops.assert_hardreset = _omap4_assert_hardreset; - soc_ops.deassert_hardreset = _omap4_deassert_hardreset; - soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; - soc_ops.init_clkdm = _init_clkdm; } else if (soc_is_am33xx()) { soc_ops.enable_module = _am33xx_enable_module; soc_ops.disable_module = _am33xx_disable_module; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d63..d02acf9 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -752,7 +752,6 @@ extern int omap44xx_hwmod_init(void); extern int omap54xx_hwmod_init(void); extern int am33xx_hwmod_init(void); extern int dra7xx_hwmod_init(void); -int am43xx_hwmod_init(void); extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h deleted file mode 100644 index 130332c..0000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Data common for AM335x and AM43x - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H -#define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H - -extern struct omap_hwmod_ocp_if am33xx_mpu__l3_main; -extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s; -extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls; -extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup; -extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr; -extern struct omap_hwmod_ocp_if am33xx_mpu__prcm; -extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; -extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main; -extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; -extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; -extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc; -extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0; -extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1; -extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio1; -extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio2; -extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3; -extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2; -extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; -extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2; -extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3; -extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1; -extern struct omap_hwmod_ocp_if am33xx_l3_s__mmc2; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7; -extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc; -extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0; -extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1; -extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart2; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart3; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart4; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart5; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6; -extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; -extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0; -extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0; - -extern struct omap_hwmod am33xx_l3_main_hwmod; -extern struct omap_hwmod am33xx_l3_s_hwmod; -extern struct omap_hwmod am33xx_l3_instr_hwmod; -extern struct omap_hwmod am33xx_l4_ls_hwmod; -extern struct omap_hwmod am33xx_l4_wkup_hwmod; -extern struct omap_hwmod am33xx_mpu_hwmod; -extern struct omap_hwmod am33xx_pruss_hwmod; -extern struct omap_hwmod am33xx_gfx_hwmod; -extern struct omap_hwmod am33xx_prcm_hwmod; -extern struct omap_hwmod am33xx_aes0_hwmod; -extern struct omap_hwmod am33xx_sha0_hwmod; -extern struct omap_hwmod am33xx_ocmcram_hwmod; -extern struct omap_hwmod am33xx_smartreflex0_hwmod; -extern struct omap_hwmod am33xx_smartreflex1_hwmod; -extern struct omap_hwmod am33xx_cpgmac0_hwmod; -extern struct omap_hwmod am33xx_mdio_hwmod; -extern struct omap_hwmod am33xx_dcan0_hwmod; -extern struct omap_hwmod am33xx_dcan1_hwmod; -extern struct omap_hwmod am33xx_elm_hwmod; -extern struct omap_hwmod am33xx_epwmss0_hwmod; -extern struct omap_hwmod am33xx_ecap0_hwmod; -extern struct omap_hwmod am33xx_eqep0_hwmod; -extern struct omap_hwmod am33xx_ehrpwm0_hwmod; -extern struct omap_hwmod am33xx_epwmss1_hwmod; -extern struct omap_hwmod am33xx_ecap1_hwmod; -extern struct omap_hwmod am33xx_eqep1_hwmod; -extern struct omap_hwmod am33xx_ehrpwm1_hwmod; -extern struct omap_hwmod am33xx_epwmss2_hwmod; -extern struct omap_hwmod am33xx_ecap2_hwmod; -extern struct omap_hwmod am33xx_eqep2_hwmod; -extern struct omap_hwmod am33xx_ehrpwm2_hwmod; -extern struct omap_hwmod am33xx_gpio1_hwmod; -extern struct omap_hwmod am33xx_gpio2_hwmod; -extern struct omap_hwmod am33xx_gpio3_hwmod; -extern struct omap_hwmod am33xx_gpmc_hwmod; -extern struct omap_hwmod am33xx_i2c1_hwmod; -extern struct omap_hwmod am33xx_i2c2_hwmod; -extern struct omap_hwmod am33xx_i2c3_hwmod; -extern struct omap_hwmod am33xx_mailbox_hwmod; -extern struct omap_hwmod am33xx_mcasp0_hwmod; -extern struct omap_hwmod am33xx_mcasp1_hwmod; -extern struct omap_hwmod am33xx_mmc0_hwmod; -extern struct omap_hwmod am33xx_mmc1_hwmod; -extern struct omap_hwmod am33xx_mmc2_hwmod; -extern struct omap_hwmod am33xx_rtc_hwmod; -extern struct omap_hwmod am33xx_spi0_hwmod; -extern struct omap_hwmod am33xx_spi1_hwmod; -extern struct omap_hwmod am33xx_spinlock_hwmod; -extern struct omap_hwmod am33xx_timer1_hwmod; -extern struct omap_hwmod am33xx_timer2_hwmod; -extern struct omap_hwmod am33xx_timer3_hwmod; -extern struct omap_hwmod am33xx_timer4_hwmod; -extern struct omap_hwmod am33xx_timer5_hwmod; -extern struct omap_hwmod am33xx_timer6_hwmod; -extern struct omap_hwmod am33xx_timer7_hwmod; -extern struct omap_hwmod am33xx_tpcc_hwmod; -extern struct omap_hwmod am33xx_tptc0_hwmod; -extern struct omap_hwmod am33xx_tptc1_hwmod; -extern struct omap_hwmod am33xx_tptc2_hwmod; -extern struct omap_hwmod am33xx_uart1_hwmod; -extern struct omap_hwmod am33xx_uart2_hwmod; -extern struct omap_hwmod am33xx_uart3_hwmod; -extern struct omap_hwmod am33xx_uart4_hwmod; -extern struct omap_hwmod am33xx_uart5_hwmod; -extern struct omap_hwmod am33xx_uart6_hwmod; -extern struct omap_hwmod am33xx_wd_timer1_hwmod; - -extern struct omap_hwmod_class am33xx_l4_hwmod_class; -extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class; -extern struct omap_hwmod_class am33xx_control_hwmod_class; -extern struct omap_hwmod_class am33xx_gpio_hwmod_class; -extern struct omap_hwmod_class am33xx_timer_hwmod_class; -extern struct omap_hwmod_class am33xx_epwmss_hwmod_class; -extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; -extern struct omap_hwmod_class am33xx_spi_hwmod_class; - -extern struct omap_gpio_dev_attr gpio_dev_attr; -extern struct omap2_mcspi_dev_attr mcspi_attrib; - -void omap_hwmod_am33xx_reg(void); -void omap_hwmod_am43xx_reg(void); - -#endif diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c deleted file mode 100644 index e2db378..0000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ /dev/null @@ -1,643 +0,0 @@ -/* - * - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Interconnects common for AM335x and AM43x - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/sizes.h> -#include "omap_hwmod.h" -#include "omap_hwmod_33xx_43xx_common_data.h" - -/* mpu -> l3 main */ -struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { - .master = &am33xx_mpu_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "dpll_mpu_m2_ck", - .user = OCP_USER_MPU, -}; - -/* l3 main -> l3 s */ -struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_l3_s_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 s -> l4 per/ls */ -struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l4_ls_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 s -> l4 wkup */ -struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l4_wkup_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> l3 instr */ -struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_l3_instr_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> prcm */ -struct omap_hwmod_ocp_if am33xx_mpu__prcm = { - .master = &am33xx_mpu_hwmod, - .slave = &am33xx_prcm_hwmod, - .clk = "dpll_mpu_m2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 s -> l3 main*/ -struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* pru-icss -> l3 main */ -struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { - .master = &am33xx_pruss_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "l3_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gfx -> l3 main */ -struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { - .master = &am33xx_gfx_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> gfx */ -struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_gfx_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 wkup -> rtc */ -struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_rtc_hwmod, - .clk = "clkdiv32k_ick", - .user = OCP_USER_MPU, -}; - -/* l4 per/ls -> DCAN0 */ -struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_dcan0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 per/ls -> DCAN1 */ -struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_dcan1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 per/ls -> GPIO2 */ -struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_gpio1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 per/ls -> gpio3 */ -struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_gpio2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 per/ls -> gpio4 */ -struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_gpio3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { - .master = &am33xx_cpgmac0_hwmod, - .slave = &am33xx_mdio_hwmod, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { - { - .pa_start = 0x48080000, - .pa_end = 0x48080000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_elm_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_elm_addr_space, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { - { - .pa_start = 0x48300000, - .pa_end = 0x48300000 + SZ_16 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_epwmss0_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_epwmss0_addr_space, - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_ecap0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_eqep0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_ehrpwm0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - - -static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { - { - .pa_start = 0x48302000, - .pa_end = 0x48302000 + SZ_16 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_epwmss1_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_epwmss1_addr_space, - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_ecap1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_eqep1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_ehrpwm1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { - { - .pa_start = 0x48304000, - .pa_end = 0x48304000 + SZ_16 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_epwmss2_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_epwmss2_addr_space, - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_ecap2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_eqep2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_ehrpwm2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l3s cfg -> gpmc */ -static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { - { - .pa_start = 0x50000000, - .pa_end = 0x50000000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_gpmc_hwmod, - .clk = "l3s_gclk", - .addr = am33xx_gpmc_addr_space, - .user = OCP_USER_MPU, -}; - -/* i2c2 */ -struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_i2c2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_i2c3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { - { - .pa_start = 0x480C8000, - .pa_end = 0x480C8000 + (SZ_4K - 1), - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4 ls -> mailbox */ -struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_mailbox_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_mailbox_addrs, - .user = OCP_USER_MPU, -}; - -/* l4 ls -> spinlock */ -struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_spinlock_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mcasp0 */ -static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { - { - .pa_start = 0x48038000, - .pa_end = 0x48038000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_mcasp0_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_mcasp0_addr_space, - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mcasp1 */ -static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { - { - .pa_start = 0x4803C000, - .pa_end = 0x4803C000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_mcasp1_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_mcasp1_addr_space, - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mmc0 */ -static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { - { - .pa_start = 0x48060100, - .pa_end = 0x48060100 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_mmc0_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_mmc0_addr_space, - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mmc1 */ -static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { - { - .pa_start = 0x481d8100, - .pa_end = 0x481d8100 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_mmc1_hwmod, - .clk = "l4ls_gclk", - .addr = am33xx_mmc1_addr_space, - .user = OCP_USER_MPU, -}; - -/* l3 s -> mmc2 */ -static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { - { - .pa_start = 0x47810100, - .pa_end = 0x47810100 + SZ_64K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_mmc2_hwmod, - .clk = "l3s_gclk", - .addr = am33xx_mmc2_addr_space, - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mcspi0 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_spi0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> mcspi1 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_spi1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer2 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer3 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer4 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer5 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer6 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer6_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 per -> timer7 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer7_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l3 main -> tpcc */ -struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_tpcc_hwmod, - .clk = "l3_gclk", - .user = OCP_USER_MPU, -}; - -/* l3 main -> tpcc0 */ -static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { - { - .pa_start = 0x49800000, - .pa_end = 0x49800000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_tptc0_hwmod, - .clk = "l3_gclk", - .addr = am33xx_tptc0_addr_space, - .user = OCP_USER_MPU, -}; - -/* l3 main -> tpcc1 */ -static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { - { - .pa_start = 0x49900000, - .pa_end = 0x49900000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_tptc1_hwmod, - .clk = "l3_gclk", - .addr = am33xx_tptc1_addr_space, - .user = OCP_USER_MPU, -}; - -/* l3 main -> tpcc2 */ -static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { - { - .pa_start = 0x49a00000, - .pa_end = 0x49a00000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_tptc2_hwmod, - .clk = "l3_gclk", - .addr = am33xx_tptc2_addr_space, - .user = OCP_USER_MPU, -}; - -/* l4 ls -> uart2 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_uart2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> uart3 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_uart3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> uart4 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_uart4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> uart5 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_uart5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l4 ls -> uart6 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_uart6_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -/* l3 main -> ocmc */ -struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_ocmcram_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> sha0 HIB2 */ -static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { - { - .pa_start = 0x53100000, - .pa_end = 0x53100000 + SZ_512 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_sha0_hwmod, - .clk = "sha0_fck", - .addr = am33xx_sha0_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> AES0 HIB2 */ -static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { - { - .pa_start = 0x53500000, - .pa_end = 0x53500000 + SZ_1M - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_aes0_hwmod, - .clk = "aes0_fck", - .addr = am33xx_aes0_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c deleted file mode 100644 index 0f17862..0000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ /dev/null @@ -1,1469 +0,0 @@ -/* - * - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Hwmod common for AM335x and AM43x - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_data/gpio-omap.h> -#include <linux/platform_data/spi-omap2-mcspi.h> -#include "omap_hwmod.h" -#include "i2c.h" -#include "mmc.h" -#include "wd_timer.h" -#include "cm33xx.h" -#include "prm33xx.h" -#include "omap_hwmod_33xx_43xx_common_data.h" -#include "prcm43xx.h" - -#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) -#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) -#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst)) - -/* - * 'l3' class - * instance(s): l3_main, l3_s, l3_instr - */ -static struct omap_hwmod_class am33xx_l3_hwmod_class = { - .name = "l3", -}; - -struct omap_hwmod am33xx_l3_main_hwmod = { - .name = "l3_main", - .class = &am33xx_l3_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* l3_s */ -struct omap_hwmod am33xx_l3_s_hwmod = { - .name = "l3_s", - .class = &am33xx_l3_hwmod_class, - .clkdm_name = "l3s_clkdm", -}; - -/* l3_instr */ -struct omap_hwmod am33xx_l3_instr_hwmod = { - .name = "l3_instr", - .class = &am33xx_l3_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'l4' class - * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw - */ -struct omap_hwmod_class am33xx_l4_hwmod_class = { - .name = "l4", -}; - -/* l4_ls */ -struct omap_hwmod am33xx_l4_ls_hwmod = { - .name = "l4_ls", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* l4_wkup */ -struct omap_hwmod am33xx_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'mpu' class - */ -static struct omap_hwmod_class am33xx_mpu_hwmod_class = { - .name = "mpu", -}; - -struct omap_hwmod am33xx_mpu_hwmod = { - .name = "mpu", - .class = &am33xx_mpu_hwmod_class, - .clkdm_name = "mpu_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "dpll_mpu_m2_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'wakeup m3' class - * Wakeup controller sub-system under wakeup domain - */ -struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { - .name = "wkup_m3", -}; - -/* - * 'pru-icss' class - * Programmable Real-Time Unit and Industrial Communication Subsystem - */ -static struct omap_hwmod_class am33xx_pruss_hwmod_class = { - .name = "pruss", -}; - -static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { - { .name = "pruss", .rst_shift = 1 }, -}; - -/* pru-icss */ -/* Pseudo hwmod for reset control purpose only */ -struct omap_hwmod am33xx_pruss_hwmod = { - .name = "pruss", - .class = &am33xx_pruss_hwmod_class, - .clkdm_name = "pruss_ocp_clkdm", - .main_clk = "pruss_ocp_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .rst_lines = am33xx_pruss_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), -}; - -/* gfx */ -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod_class am33xx_gfx_hwmod_class = { - .name = "gfx", -}; - -static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { - { .name = "gfx", .rst_shift = 0, .st_shift = 0}, -}; - -struct omap_hwmod am33xx_gfx_hwmod = { - .name = "gfx", - .class = &am33xx_gfx_hwmod_class, - .clkdm_name = "gfx_l3_clkdm", - .main_clk = "gfx_fck_div_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .rst_lines = am33xx_gfx_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), -}; - -/* - * 'prcm' class - * power and reset manager (whole prcm infrastructure) - */ -static struct omap_hwmod_class am33xx_prcm_hwmod_class = { - .name = "prcm", -}; - -/* prcm */ -struct omap_hwmod am33xx_prcm_hwmod = { - .name = "prcm", - .class = &am33xx_prcm_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* - * 'aes0' class - */ -static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { - .rev_offs = 0x80, - .sysc_offs = 0x84, - .syss_offs = 0x88, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class am33xx_aes0_hwmod_class = { - .name = "aes0", - .sysc = &am33xx_aes0_sysc, -}; - -struct omap_hwmod am33xx_aes0_hwmod = { - .name = "aes", - .class = &am33xx_aes0_hwmod_class, - .clkdm_name = "l3_clkdm", - .main_clk = "aes0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* sha0 HIB2 (the 'P' (public) device) */ -static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { - .rev_offs = 0x100, - .sysc_offs = 0x110, - .syss_offs = 0x114, - .sysc_flags = SYSS_HAS_RESET_STATUS, -}; - -static struct omap_hwmod_class am33xx_sha0_hwmod_class = { - .name = "sha0", - .sysc = &am33xx_sha0_sysc, -}; - -struct omap_hwmod am33xx_sha0_hwmod = { - .name = "sham", - .class = &am33xx_sha0_hwmod_class, - .clkdm_name = "l3_clkdm", - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* ocmcram */ -static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { - .name = "ocmcram", -}; - -struct omap_hwmod am33xx_ocmcram_hwmod = { - .name = "ocmcram", - .class = &am33xx_ocmcram_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'smartreflex' class */ -static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { - .name = "smartreflex", -}; - -/* smartreflex0 */ -struct omap_hwmod am33xx_smartreflex0_hwmod = { - .name = "smartreflex0", - .class = &am33xx_smartreflex_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "smartreflex0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* smartreflex1 */ -struct omap_hwmod am33xx_smartreflex1_hwmod = { - .name = "smartreflex1", - .class = &am33xx_smartreflex_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "smartreflex1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'control' module class - */ -struct omap_hwmod_class am33xx_control_hwmod_class = { - .name = "control", -}; - -/* - * 'cpgmac' class - * cpsw/cpgmac sub system - */ -static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x8, - .syss_offs = 0x4, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | - MSTANDBY_NO), - .sysc_fields = &omap_hwmod_sysc_type3, -}; - -static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { - .name = "cpgmac0", - .sysc = &am33xx_cpgmac_sysc, -}; - -struct omap_hwmod am33xx_cpgmac0_hwmod = { - .name = "cpgmac0", - .class = &am33xx_cpgmac0_hwmod_class, - .clkdm_name = "cpsw_125mhz_clkdm", - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), - .main_clk = "cpsw_125mhz_gclk", - .mpu_rt_idx = 1, - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * mdio class - */ -static struct omap_hwmod_class am33xx_mdio_hwmod_class = { - .name = "davinci_mdio", -}; - -struct omap_hwmod am33xx_mdio_hwmod = { - .name = "davinci_mdio", - .class = &am33xx_mdio_hwmod_class, - .clkdm_name = "cpsw_125mhz_clkdm", - .main_clk = "cpsw_125mhz_gclk", -}; - -/* - * dcan class - */ -static struct omap_hwmod_class am33xx_dcan_hwmod_class = { - .name = "d_can", -}; - -/* dcan0 */ -struct omap_hwmod am33xx_dcan0_hwmod = { - .name = "d_can0", - .class = &am33xx_dcan_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dcan0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* dcan1 */ -struct omap_hwmod am33xx_dcan1_hwmod = { - .name = "d_can1", - .class = &am33xx_dcan_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dcan1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* elm */ -static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_elm_hwmod_class = { - .name = "elm", - .sysc = &am33xx_elm_sysc, -}; - -struct omap_hwmod am33xx_elm_hwmod = { - .name = "elm", - .class = &am33xx_elm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* pwmss */ -static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x4, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -struct omap_hwmod_class am33xx_epwmss_hwmod_class = { - .name = "epwmss", - .sysc = &am33xx_epwmss_sysc, -}; - -static struct omap_hwmod_class am33xx_ecap_hwmod_class = { - .name = "ecap", -}; - -static struct omap_hwmod_class am33xx_eqep_hwmod_class = { - .name = "eqep", -}; - -struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { - .name = "ehrpwm", -}; - -/* epwmss0 */ -struct omap_hwmod am33xx_epwmss0_hwmod = { - .name = "epwmss0", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* ecap0 */ -struct omap_hwmod am33xx_ecap0_hwmod = { - .name = "ecap0", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep0 */ -struct omap_hwmod am33xx_eqep0_hwmod = { - .name = "eqep0", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm0 */ -struct omap_hwmod am33xx_ehrpwm0_hwmod = { - .name = "ehrpwm0", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* epwmss1 */ -struct omap_hwmod am33xx_epwmss1_hwmod = { - .name = "epwmss1", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* ecap1 */ -struct omap_hwmod am33xx_ecap1_hwmod = { - .name = "ecap1", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep1 */ -struct omap_hwmod am33xx_eqep1_hwmod = { - .name = "eqep1", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm1 */ -struct omap_hwmod am33xx_ehrpwm1_hwmod = { - .name = "ehrpwm1", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* epwmss2 */ -struct omap_hwmod am33xx_epwmss2_hwmod = { - .name = "epwmss2", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* ecap2 */ -struct omap_hwmod am33xx_ecap2_hwmod = { - .name = "ecap2", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep2 */ -struct omap_hwmod am33xx_eqep2_hwmod = { - .name = "eqep2", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm2 */ -struct omap_hwmod am33xx_ehrpwm2_hwmod = { - .name = "ehrpwm2", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* - * 'gpio' class: for gpio 0,1,2,3 - */ -static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0114, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class am33xx_gpio_hwmod_class = { - .name = "gpio", - .sysc = &am33xx_gpio_sysc, - .rev = 2, -}; - -struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = true, -}; - -/* gpio1 */ -static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { - { .role = "dbclk", .clk = "gpio1_dbclk" }, -}; - -struct omap_hwmod am33xx_gpio1_hwmod = { - .name = "gpio2", - .class = &am33xx_gpio_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = gpio1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), - .dev_attr = &gpio_dev_attr, -}; - -/* gpio2 */ -static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { - { .role = "dbclk", .clk = "gpio2_dbclk" }, -}; - -struct omap_hwmod am33xx_gpio2_hwmod = { - .name = "gpio3", - .class = &am33xx_gpio_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = gpio2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), - .dev_attr = &gpio_dev_attr, -}; - -/* gpio3 */ -static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { - { .role = "dbclk", .clk = "gpio3_dbclk" }, -}; - -struct omap_hwmod am33xx_gpio3_hwmod = { - .name = "gpio4", - .class = &am33xx_gpio_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = gpio3_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), - .dev_attr = &gpio_dev_attr, -}; - -/* gpmc */ -static struct omap_hwmod_class_sysconfig gpmc_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { - .name = "gpmc", - .sysc = &gpmc_sysc, -}; - -struct omap_hwmod am33xx_gpmc_hwmod = { - .name = "gpmc", - .class = &am33xx_gpmc_hwmod_class, - .clkdm_name = "l3s_clkdm", - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'i2c' class */ -static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { - .sysc_offs = 0x0010, - .syss_offs = 0x0090, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &am33xx_i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_2, - .reset = &omap_i2c_reset, -}; - -static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, -}; - -/* i2c1 */ -struct omap_hwmod am33xx_i2c1_hwmod = { - .name = "i2c1", - .class = &i2c_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "dpll_per_m2_div4_wkupdm_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &i2c_dev_attr, -}; - -/* i2c1 */ -struct omap_hwmod am33xx_i2c2_hwmod = { - .name = "i2c2", - .class = &i2c_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &i2c_dev_attr, -}; - -/* i2c3 */ -struct omap_hwmod am33xx_i2c3_hwmod = { - .name = "i2c3", - .class = &i2c_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &i2c_dev_attr, -}; - -/* - * 'mailbox' class - * mailbox module allowing communication between the on-chip processors using a - * queued mailbox-interrupt mechanism. - */ -static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { - .name = "mailbox", - .sysc = &am33xx_mailbox_sysc, -}; - -struct omap_hwmod am33xx_mailbox_hwmod = { - .name = "mailbox", - .class = &am33xx_mailbox_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'mcasp' class - */ -static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x4, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type3, -}; - -static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { - .name = "mcasp", - .sysc = &am33xx_mcasp_sysc, -}; - -/* mcasp0 */ -struct omap_hwmod am33xx_mcasp0_hwmod = { - .name = "mcasp0", - .class = &am33xx_mcasp_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "mcasp0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* mcasp1 */ -struct omap_hwmod am33xx_mcasp1_hwmod = { - .name = "mcasp1", - .class = &am33xx_mcasp_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "mcasp1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'mmc' class */ -static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { - .rev_offs = 0x1fc, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_mmc_hwmod_class = { - .name = "mmc", - .sysc = &am33xx_mmc_sysc, -}; - -/* mmc0 */ -static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, -}; - -struct omap_hwmod am33xx_mmc0_hwmod = { - .name = "mmc1", - .class = &am33xx_mmc_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "mmc_clk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &am33xx_mmc0_dev_attr, -}; - -/* mmc1 */ -static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, -}; - -struct omap_hwmod am33xx_mmc1_hwmod = { - .name = "mmc2", - .class = &am33xx_mmc_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "mmc_clk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &am33xx_mmc1_dev_attr, -}; - -/* mmc2 */ -static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, -}; -struct omap_hwmod am33xx_mmc2_hwmod = { - .name = "mmc3", - .class = &am33xx_mmc_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "mmc_clk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &am33xx_mmc2_dev_attr, -}; - -/* - * 'rtc' class - * rtc subsystem - */ -static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { - .rev_offs = 0x0074, - .sysc_offs = 0x0078, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | - SIDLE_SMART | SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type3, -}; - -static struct omap_hwmod_class am33xx_rtc_hwmod_class = { - .name = "rtc", - .sysc = &am33xx_rtc_sysc, -}; - -struct omap_hwmod am33xx_rtc_hwmod = { - .name = "rtc", - .class = &am33xx_rtc_hwmod_class, - .clkdm_name = "l4_rtc_clkdm", - .main_clk = "clk_32768_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'spi' class */ -static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0110, - .syss_offs = 0x0114, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -struct omap_hwmod_class am33xx_spi_hwmod_class = { - .name = "mcspi", - .sysc = &am33xx_mcspi_sysc, - .rev = OMAP4_MCSPI_REV, -}; - -/* spi0 */ -struct omap2_mcspi_dev_attr mcspi_attrib = { - .num_chipselect = 2, -}; -struct omap_hwmod am33xx_spi0_hwmod = { - .name = "spi0", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &mcspi_attrib, -}; - -/* spi1 */ -struct omap_hwmod am33xx_spi1_hwmod = { - .name = "spi1", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &mcspi_attrib, -}; - -/* - * 'spinlock' class - * spinlock provides hardware assistance for synchronizing the - * processes running on multiple processors - */ - -static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { - .name = "spinlock", - .sysc = &am33xx_spinlock_sysc, -}; - -struct omap_hwmod am33xx_spinlock_hwmod = { - .name = "spinlock", - .class = &am33xx_spinlock_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'timer 2-7' class */ -static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -struct omap_hwmod_class am33xx_timer_hwmod_class = { - .name = "timer", - .sysc = &am33xx_timer_sysc, -}; - -/* timer1 1ms */ -static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { - .name = "timer", - .sysc = &am33xx_timer1ms_sysc, -}; - -struct omap_hwmod am33xx_timer1_hwmod = { - .name = "timer1", - .class = &am33xx_timer1ms_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "timer1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer2_hwmod = { - .name = "timer2", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer2_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer3_hwmod = { - .name = "timer3", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer3_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer4_hwmod = { - .name = "timer4", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer4_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer5_hwmod = { - .name = "timer5", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer5_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer6_hwmod = { - .name = "timer6", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer6_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer7_hwmod = { - .name = "timer7", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer7_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* tpcc */ -static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { - .name = "tpcc", -}; - -struct omap_hwmod am33xx_tpcc_hwmod = { - .name = "tpcc", - .class = &am33xx_tpcc_hwmod_class, - .clkdm_name = "l3_clkdm", - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x10, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_MIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -/* 'tptc' class */ -static struct omap_hwmod_class am33xx_tptc_hwmod_class = { - .name = "tptc", - .sysc = &am33xx_tptc_sysc, -}; - -/* tptc0 */ -struct omap_hwmod am33xx_tptc0_hwmod = { - .name = "tptc0", - .class = &am33xx_tptc_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* tptc1 */ -struct omap_hwmod am33xx_tptc1_hwmod = { - .name = "tptc1", - .class = &am33xx_tptc_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* tptc2 */ -struct omap_hwmod am33xx_tptc2_hwmod = { - .name = "tptc2", - .class = &am33xx_tptc_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'uart' class */ -static struct omap_hwmod_class_sysconfig uart_sysc = { - .rev_offs = 0x50, - .sysc_offs = 0x54, - .syss_offs = 0x58, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class uart_class = { - .name = "uart", - .sysc = &uart_sysc, -}; - -struct omap_hwmod am33xx_uart1_hwmod = { - .name = "uart1", - .class = &uart_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "dpll_per_m2_div4_wkupdm_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_uart2_hwmod = { - .name = "uart2", - .class = &uart_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* uart3 */ -struct omap_hwmod am33xx_uart3_hwmod = { - .name = "uart3", - .class = &uart_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_uart4_hwmod = { - .name = "uart4", - .class = &uart_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_uart5_hwmod = { - .name = "uart5", - .class = &uart_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_uart6_hwmod = { - .name = "uart6", - .class = &uart_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* 'wd_timer' class */ -static struct omap_hwmod_class_sysconfig wdt_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { - .name = "wd_timer", - .sysc = &wdt_sysc, - .pre_shutdown = &omap2_wd_timer_disable, -}; - -/* - * XXX: device.c file uses hardcoded name for watchdog timer - * driver "wd_timer2, so we are also using same name as of now... - */ -struct omap_hwmod am33xx_wd_timer1_hwmod = { - .name = "wd_timer2", - .class = &am33xx_wd_timer_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wdt1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static void omap_hwmod_am33xx_clkctrl(void) -{ - CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET); - CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET); - CLKCTRL(am33xx_smartreflex0_hwmod, - AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_smartreflex1_hwmod, - AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET); - CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); - CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); -} - -static void omap_hwmod_am33xx_rst(void) -{ - RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET); - RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET); - RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET); -} - -void omap_hwmod_am33xx_reg(void) -{ - omap_hwmod_am33xx_clkctrl(); - omap_hwmod_am33xx_rst(); -} - -static void omap_hwmod_am43xx_clkctrl(void) -{ - CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET); - CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET); - CLKCTRL(am33xx_smartreflex0_hwmod, - AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_smartreflex1_hwmod, - AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET); - CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); - CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); - CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); -} - -static void omap_hwmod_am43xx_rst(void) -{ - RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET); - RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); - RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); -} - -void omap_hwmod_am43xx_reg(void) -{ - omap_hwmod_am43xx_clkctrl(); - omap_hwmod_am43xx_rst(); -} diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 6b406ca..215894f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -29,7 +29,6 @@ #include "i2c.h" #include "mmc.h" #include "wd_timer.h" -#include "omap_hwmod_33xx_43xx_common_data.h" /* * IP blocks @@ -53,7 +52,7 @@ static struct omap_hwmod am33xx_emif_hwmod = { .name = "emif", .class = &am33xx_emif_hwmod_class, .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .main_clk = "dpll_ddr_m2_div2_ck", .prcm = { .omap4 = { @@ -63,12 +62,79 @@ static struct omap_hwmod am33xx_emif_hwmod = { }, }; +/* + * 'l3' class + * instance(s): l3_main, l3_s, l3_instr + */ +static struct omap_hwmod_class am33xx_l3_hwmod_class = { + .name = "l3", +}; + +static struct omap_hwmod am33xx_l3_main_hwmod = { + .name = "l3_main", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* l3_s */ +static struct omap_hwmod am33xx_l3_s_hwmod = { + .name = "l3_s", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3s_clkdm", +}; + +/* l3_instr */ +static struct omap_hwmod am33xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &am33xx_l3_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'l4' class + * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw + */ +static struct omap_hwmod_class am33xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_ls */ +static struct omap_hwmod am33xx_l4_ls_hwmod = { + .name = "l4_ls", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* l4_hs */ static struct omap_hwmod am33xx_l4_hs_hwmod = { .name = "l4_hs", .class = &am33xx_l4_hwmod_class, .clkdm_name = "l4hs_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .main_clk = "l4hs_gclk", .prcm = { .omap4 = { @@ -78,6 +144,50 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = { }, }; + +/* l4_wkup */ +static struct omap_hwmod am33xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &am33xx_l4_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mpu' class + */ +static struct omap_hwmod_class am33xx_mpu_hwmod_class = { + .name = "mpu", +}; + +static struct omap_hwmod am33xx_mpu_hwmod = { + .name = "mpu", + .class = &am33xx_mpu_hwmod_class, + .clkdm_name = "mpu_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'wakeup m3' class + * Wakeup controller sub-system under wakeup domain + */ +static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { + .name = "wkup_m3", +}; + static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, }; @@ -103,6 +213,78 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { }; /* + * 'pru-icss' class + * Programmable Real-Time Unit and Industrial Communication Subsystem + */ +static struct omap_hwmod_class am33xx_pruss_hwmod_class = { + .name = "pruss", +}; + +static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { + { .name = "pruss", .rst_shift = 1 }, +}; + +/* pru-icss */ +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod am33xx_pruss_hwmod = { + .name = "pruss", + .class = &am33xx_pruss_hwmod_class, + .clkdm_name = "pruss_ocp_clkdm", + .main_clk = "pruss_ocp_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_pruss_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), +}; + +/* gfx */ +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod_class am33xx_gfx_hwmod_class = { + .name = "gfx", +}; + +static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { + { .name = "gfx", .rst_shift = 0, .st_shift = 0}, +}; + +static struct omap_hwmod am33xx_gfx_hwmod = { + .name = "gfx", + .class = &am33xx_gfx_hwmod_class, + .clkdm_name = "gfx_l3_clkdm", + .main_clk = "gfx_fck_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, + .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, + .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .rst_lines = am33xx_gfx_resets, + .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), +}; + +/* + * 'prcm' class + * power and reset manager (whole prcm infrastructure) + */ +static struct omap_hwmod_class am33xx_prcm_hwmod_class = { + .name = "prcm", +}; + +/* prcm */ +static struct omap_hwmod am33xx_prcm_hwmod = { + .name = "prcm", + .class = &am33xx_prcm_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* * 'adc/tsc' class * TouchScreen Controller (Anolog-To-Digital Converter) */ @@ -206,6 +388,79 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { #endif /* + * 'aes0' class + */ +static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { + .rev_offs = 0x80, + .sysc_offs = 0x84, + .syss_offs = 0x88, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class am33xx_aes0_hwmod_class = { + .name = "aes0", + .sysc = &am33xx_aes0_sysc, +}; + +static struct omap_hwmod am33xx_aes0_hwmod = { + .name = "aes", + .class = &am33xx_aes0_hwmod_class, + .clkdm_name = "l3_clkdm", + .main_clk = "aes0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* sha0 HIB2 (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { + .rev_offs = 0x100, + .sysc_offs = 0x110, + .syss_offs = 0x114, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class am33xx_sha0_hwmod_class = { + .name = "sha0", + .sysc = &am33xx_sha0_sysc, +}; + +static struct omap_hwmod am33xx_sha0_hwmod = { + .name = "sham", + .class = &am33xx_sha0_hwmod_class, + .clkdm_name = "l3_clkdm", + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ocmcram */ +static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { + .name = "ocmcram", +}; + +static struct omap_hwmod am33xx_ocmcram_hwmod = { + .name = "ocmcram", + .class = &am33xx_ocmcram_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'debugss' class * debug sub system */ @@ -233,11 +488,51 @@ static struct omap_hwmod am33xx_debugss_hwmod = { .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), }; +/* 'smartreflex' class */ +static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { + .name = "smartreflex", +}; + +/* smartreflex0 */ +static struct omap_hwmod am33xx_smartreflex0_hwmod = { + .name = "smartreflex0", + .class = &am33xx_smartreflex_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .main_clk = "smartreflex0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* smartreflex1 */ +static struct omap_hwmod am33xx_smartreflex1_hwmod = { + .name = "smartreflex1", + .class = &am33xx_smartreflex_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .main_clk = "smartreflex1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'control' module class + */ +static struct omap_hwmod_class am33xx_control_hwmod_class = { + .name = "control", +}; + static struct omap_hwmod am33xx_control_hwmod = { .name = "control", .class = &am33xx_control_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), .main_clk = "dpll_core_m4_div2_ck", .prcm = { .omap4 = { @@ -247,6 +542,288 @@ static struct omap_hwmod am33xx_control_hwmod = { }, }; +/* + * 'cpgmac' class + * cpsw/cpgmac sub system + */ +static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x8, + .syss_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | + MSTANDBY_NO), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { + .name = "cpgmac0", + .sysc = &am33xx_cpgmac_sysc, +}; + +static struct omap_hwmod am33xx_cpgmac0_hwmod = { + .name = "cpgmac0", + .class = &am33xx_cpgmac0_hwmod_class, + .clkdm_name = "cpsw_125mhz_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "cpsw_125mhz_gclk", + .mpu_rt_idx = 1, + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * mdio class + */ +static struct omap_hwmod_class am33xx_mdio_hwmod_class = { + .name = "davinci_mdio", +}; + +static struct omap_hwmod am33xx_mdio_hwmod = { + .name = "davinci_mdio", + .class = &am33xx_mdio_hwmod_class, + .clkdm_name = "cpsw_125mhz_clkdm", + .main_clk = "cpsw_125mhz_gclk", +}; + +/* + * dcan class + */ +static struct omap_hwmod_class am33xx_dcan_hwmod_class = { + .name = "d_can", +}; + +/* dcan0 */ +static struct omap_hwmod am33xx_dcan0_hwmod = { + .name = "d_can0", + .class = &am33xx_dcan_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "dcan0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* dcan1 */ +static struct omap_hwmod am33xx_dcan1_hwmod = { + .name = "d_can1", + .class = &am33xx_dcan_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "dcan1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* elm */ +static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_elm_hwmod_class = { + .name = "elm", + .sysc = &am33xx_elm_sysc, +}; + +static struct omap_hwmod am33xx_elm_hwmod = { + .name = "elm", + .class = &am33xx_elm_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* pwmss */ +static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &am33xx_epwmss_sysc, +}; + +static struct omap_hwmod_class am33xx_ecap_hwmod_class = { + .name = "ecap", +}; + +static struct omap_hwmod_class am33xx_eqep_hwmod_class = { + .name = "eqep", +}; + +static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { + .name = "ehrpwm", +}; + +/* epwmss0 */ +static struct omap_hwmod am33xx_epwmss0_hwmod = { + .name = "epwmss0", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap0 */ +static struct omap_hwmod am33xx_ecap0_hwmod = { + .name = "ecap0", + .class = &am33xx_ecap_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* eqep0 */ +static struct omap_hwmod am33xx_eqep0_hwmod = { + .name = "eqep0", + .class = &am33xx_eqep_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* ehrpwm0 */ +static struct omap_hwmod am33xx_ehrpwm0_hwmod = { + .name = "ehrpwm0", + .class = &am33xx_ehrpwm_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* epwmss1 */ +static struct omap_hwmod am33xx_epwmss1_hwmod = { + .name = "epwmss1", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap1 */ +static struct omap_hwmod am33xx_ecap1_hwmod = { + .name = "ecap1", + .class = &am33xx_ecap_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* eqep1 */ +static struct omap_hwmod am33xx_eqep1_hwmod = { + .name = "eqep1", + .class = &am33xx_eqep_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* ehrpwm1 */ +static struct omap_hwmod am33xx_ehrpwm1_hwmod = { + .name = "ehrpwm1", + .class = &am33xx_ehrpwm_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* epwmss2 */ +static struct omap_hwmod am33xx_epwmss2_hwmod = { + .name = "epwmss2", + .class = &am33xx_epwmss_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* ecap2 */ +static struct omap_hwmod am33xx_ecap2_hwmod = { + .name = "ecap2", + .class = &am33xx_ecap_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* eqep2 */ +static struct omap_hwmod am33xx_eqep2_hwmod = { + .name = "eqep2", + .class = &am33xx_eqep_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* ehrpwm2 */ +static struct omap_hwmod am33xx_ehrpwm2_hwmod = { + .name = "ehrpwm2", + .class = &am33xx_ehrpwm_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", +}; + +/* + * 'gpio' class: for gpio 0,1,2,3 + */ +static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &am33xx_gpio_sysc, + .rev = 2, +}; + +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + /* gpio0 */ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { { .role = "dbclk", .clk = "gpio0_dbclk" }, @@ -269,6 +846,174 @@ static struct omap_hwmod am33xx_gpio0_hwmod = { .dev_attr = &gpio_dev_attr, }; +/* gpio1 */ +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio1_hwmod = { + .name = "gpio2", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio2_hwmod = { + .name = "gpio3", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod am33xx_gpio3_hwmod = { + .name = "gpio4", + .class = &am33xx_gpio_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpmc */ +static struct omap_hwmod_class_sysconfig gpmc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &gpmc_sysc, +}; + +static struct omap_hwmod am33xx_gpmc_hwmod = { + .name = "gpmc", + .class = &am33xx_gpmc_hwmod_class, + .clkdm_name = "l3s_clkdm", + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .main_clk = "l3s_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'i2c' class */ +static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &am33xx_i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_2, + .reset = &omap_i2c_reset, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, +}; + +/* i2c1 */ +static struct omap_hwmod am33xx_i2c1_hwmod = { + .name = "i2c1", + .class = &i2c_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_wkupdm_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c1 */ +static struct omap_hwmod am33xx_i2c2_hwmod = { + .name = "i2c2", + .class = &i2c_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c3 */ +static struct omap_hwmod am33xx_i2c3_hwmod = { + .name = "i2c3", + .class = &i2c_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + + /* lcdc */ static struct omap_hwmod_class_sysconfig lcdc_sysc = { .rev_offs = 0x0, @@ -298,6 +1043,600 @@ static struct omap_hwmod am33xx_lcdc_hwmod = { }; /* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors using a + * queued mailbox-interrupt mechanism. + */ +static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &am33xx_mailbox_sysc, +}; + +static struct omap_hwmod am33xx_mailbox_hwmod = { + .name = "mailbox", + .class = &am33xx_mailbox_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcasp' class + */ +static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { + .name = "mcasp", + .sysc = &am33xx_mcasp_sysc, +}; + +/* mcasp0 */ +static struct omap_hwmod am33xx_mcasp0_hwmod = { + .name = "mcasp0", + .class = &am33xx_mcasp_hwmod_class, + .clkdm_name = "l3s_clkdm", + .main_clk = "mcasp0_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mcasp1 */ +static struct omap_hwmod am33xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &am33xx_mcasp_hwmod_class, + .clkdm_name = "l3s_clkdm", + .main_clk = "mcasp1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'mmc' class */ +static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &am33xx_mmc_sysc, +}; + +/* mmc0 */ +static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod am33xx_mmc0_hwmod = { + .name = "mmc1", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc0_dev_attr, +}; + +/* mmc1 */ +static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod am33xx_mmc1_hwmod = { + .name = "mmc2", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc1_dev_attr, +}; + +/* mmc2 */ +static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; +static struct omap_hwmod am33xx_mmc2_hwmod = { + .name = "mmc3", + .class = &am33xx_mmc_hwmod_class, + .clkdm_name = "l3s_clkdm", + .main_clk = "mmc_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &am33xx_mmc2_dev_attr, +}; + +/* + * 'rtc' class + * rtc subsystem + */ +static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { + .rev_offs = 0x0074, + .sysc_offs = 0x0078, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | + SIDLE_SMART | SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class am33xx_rtc_hwmod_class = { + .name = "rtc", + .sysc = &am33xx_rtc_sysc, +}; + +static struct omap_hwmod am33xx_rtc_hwmod = { + .name = "rtc", + .class = &am33xx_rtc_hwmod_class, + .clkdm_name = "l4_rtc_clkdm", + .main_clk = "clk_32768_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'spi' class */ +static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0110, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_spi_hwmod_class = { + .name = "mcspi", + .sysc = &am33xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, +}; + +/* spi0 */ +static struct omap2_mcspi_dev_attr mcspi_attrib = { + .num_chipselect = 2, +}; +static struct omap_hwmod am33xx_spi0_hwmod = { + .name = "spi0", + .class = &am33xx_spi_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi_attrib, +}; + +/* spi1 */ +static struct omap_hwmod am33xx_spi1_hwmod = { + .name = "spi1", + .class = &am33xx_spi_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi_attrib, +}; + +/* + * 'spinlock' class + * spinlock provides hardware assistance for synchronizing the + * processes running on multiple processors + */ +static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { + .name = "spinlock", +}; + +static struct omap_hwmod am33xx_spinlock_hwmod = { + .name = "spinlock", + .class = &am33xx_spinlock_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "l4ls_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'timer 2-7' class */ +static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class am33xx_timer_hwmod_class = { + .name = "timer", + .sysc = &am33xx_timer_sysc, +}; + +/* timer1 1ms */ +static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { + .name = "timer", + .sysc = &am33xx_timer1ms_sysc, +}; + +static struct omap_hwmod am33xx_timer1_hwmod = { + .name = "timer1", + .class = &am33xx_timer1ms_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .main_clk = "timer1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_timer2_hwmod = { + .name = "timer2", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_timer3_hwmod = { + .name = "timer3", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_timer4_hwmod = { + .name = "timer4", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "timer4_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_timer5_hwmod = { + .name = "timer5", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "timer5_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_timer6_hwmod = { + .name = "timer6", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "timer6_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_timer7_hwmod = { + .name = "timer7", + .class = &am33xx_timer_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .main_clk = "timer7_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tpcc */ +static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { + .name = "tpcc", +}; + +static struct omap_hwmod am33xx_tpcc_hwmod = { + .name = "tpcc", + .class = &am33xx_tpcc_hwmod_class, + .clkdm_name = "l3_clkdm", + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +/* 'tptc' class */ +static struct omap_hwmod_class am33xx_tptc_hwmod_class = { + .name = "tptc", + .sysc = &am33xx_tptc_sysc, +}; + +/* tptc0 */ +static struct omap_hwmod am33xx_tptc0_hwmod = { + .name = "tptc0", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tptc1 */ +static struct omap_hwmod am33xx_tptc1_hwmod = { + .name = "tptc1", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* tptc2 */ +static struct omap_hwmod am33xx_tptc2_hwmod = { + .name = "tptc2", + .class = &am33xx_tptc_hwmod_class, + .clkdm_name = "l3_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'uart' class */ +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod am33xx_uart1_hwmod = { + .name = "uart1", + .class = &uart_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, + .main_clk = "dpll_per_m2_div4_wkupdm_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_uart2_hwmod = { + .name = "uart2", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart3 */ +static struct omap_hwmod am33xx_uart3_hwmod = { + .name = "uart3", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_uart4_hwmod = { + .name = "uart4", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_uart5_hwmod = { + .name = "uart5", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +static struct omap_hwmod am33xx_uart6_hwmod = { + .name = "uart6", + .class = &uart_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .main_clk = "dpll_per_m2_div4_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* 'wd_timer' class */ +static struct omap_hwmod_class_sysconfig wdt_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &wdt_sysc, + .pre_shutdown = &omap2_wd_timer_disable, +}; + +/* + * XXX: device.c file uses hardcoded name for watchdog timer + * driver "wd_timer2, so we are also using same name as of now... + */ +static struct omap_hwmod am33xx_wd_timer1_hwmod = { + .name = "wd_timer2", + .class = &am33xx_wd_timer_hwmod_class, + .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "wdt1_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'usb_otg' class * high-speed on-the-go universal serial bus (usb_otg) controller */ @@ -351,6 +1690,14 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mpu -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { + .master = &am33xx_mpu_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "dpll_mpu_m2_ck", + .user = OCP_USER_MPU, +}; + /* l3 main -> l4 hs */ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { .master = &am33xx_l3_main_hwmod, @@ -359,6 +1706,62 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3 main -> l3 s */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l3_s_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 per/ls */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_ls_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l4 wkup */ +static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l4_wkup_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> l3 instr */ +static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_l3_instr_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> prcm */ +static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { + .master = &am33xx_mpu_hwmod, + .slave = &am33xx_prcm_hwmod, + .clk = "dpll_mpu_m2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 s -> l3 main*/ +static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3s_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* pru-icss -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { + .master = &am33xx_pruss_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* wkup m3 -> l4 wkup */ static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { .master = &am33xx_wkup_m3_hwmod, @@ -367,6 +1770,14 @@ static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* gfx -> l3 main */ +static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { + .master = &am33xx_gfx_hwmod, + .slave = &am33xx_l3_main_hwmod, + .clk = "dpll_core_m4_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4 wkup -> wkup m3 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { .master = &am33xx_l4_wkup_hwmod, @@ -383,6 +1794,14 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3 main -> gfx */ +static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_gfx_hwmod, + .clk = "dpll_core_m4_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main -> debugss */ static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { { @@ -425,6 +1844,54 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { .user = OCP_USER_MPU, }; +/* l4 wkup -> rtc */ +static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { + .master = &am33xx_l4_wkup_hwmod, + .slave = &am33xx_rtc_hwmod, + .clk = "clkdiv32k_ick", + .user = OCP_USER_MPU, +}; + +/* l4 per/ls -> DCAN0 */ +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_dcan0_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> DCAN1 */ +static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_dcan1_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> GPIO2 */ +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio1_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> gpio3 */ +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 per/ls -> gpio4 */ +static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_gpio3_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L4 WKUP -> I2C1 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { .master = &am33xx_l4_wkup_hwmod, @@ -466,6 +1933,177 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { + .master = &am33xx_cpgmac0_hwmod, + .slave = &am33xx_mdio_hwmod, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { + { + .pa_start = 0x48080000, + .pa_end = 0x48080000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_elm_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_elm_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { + { + .pa_start = 0x48300000, + .pa_end = 0x48300000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_epwmss0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_epwmss0_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { + .master = &am33xx_epwmss0_hwmod, + .slave = &am33xx_ecap0_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { + .master = &am33xx_epwmss0_hwmod, + .slave = &am33xx_eqep0_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { + .master = &am33xx_epwmss0_hwmod, + .slave = &am33xx_ehrpwm0_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + + +static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { + { + .pa_start = 0x48302000, + .pa_end = 0x48302000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_epwmss1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_epwmss1_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { + .master = &am33xx_epwmss1_hwmod, + .slave = &am33xx_ecap1_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { + .master = &am33xx_epwmss1_hwmod, + .slave = &am33xx_eqep1_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { + .master = &am33xx_epwmss1_hwmod, + .slave = &am33xx_ehrpwm1_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_16 - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_epwmss2_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_epwmss2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { + .master = &am33xx_epwmss2_hwmod, + .slave = &am33xx_ecap2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { + .master = &am33xx_epwmss2_hwmod, + .slave = &am33xx_eqep2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { + .master = &am33xx_epwmss2_hwmod, + .slave = &am33xx_ehrpwm2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l3s cfg -> gpmc */ +static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { + { + .pa_start = 0x50000000, + .pa_end = 0x50000000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_gpmc_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_gpmc_addr_space, + .user = OCP_USER_MPU, +}; + +/* i2c2 */ +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_i2c2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_i2c3_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { { .pa_start = 0x4830E000, @@ -483,6 +2121,138 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { + { + .pa_start = 0x480C8000, + .pa_end = 0x480C8000 + (SZ_4K - 1), + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4 ls -> mailbox */ +static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mailbox_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mailbox_addrs, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> spinlock */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spinlock_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcasp0 */ +static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { + { + .pa_start = 0x48038000, + .pa_end = 0x48038000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mcasp0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcasp0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcasp1 */ +static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { + { + .pa_start = 0x4803C000, + .pa_end = 0x4803C000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mcasp1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mcasp1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mmc0 */ +static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { + { + .pa_start = 0x48060100, + .pa_end = 0x48060100 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mmc0_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mmc0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mmc1 */ +static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { + { + .pa_start = 0x481d8100, + .pa_end = 0x481d8100 + SZ_4K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_mmc1_hwmod, + .clk = "l4ls_gclk", + .addr = am33xx_mmc1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 s -> mmc2 */ +static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { + { + .pa_start = 0x47810100, + .pa_end = 0x47810100 + SZ_64K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { + .master = &am33xx_l3_s_hwmod, + .slave = &am33xx_mmc2_hwmod, + .clk = "l3s_gclk", + .addr = am33xx_mmc2_addr_space, + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcspi0 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spi0_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 ls -> mcspi1 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_spi1_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + /* l4 wkup -> timer1 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { .master = &am33xx_l4_wkup_hwmod, @@ -491,6 +2261,116 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { .user = OCP_USER_MPU, }; +/* l4 per -> timer2 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer3 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer3_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer4 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer4_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer5 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer5_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer6 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer6_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 per -> timer7 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_timer7_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc */ +static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tpcc_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc0 */ +static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { + { + .pa_start = 0x49800000, + .pa_end = 0x49800000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc0_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc0_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc1 */ +static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { + { + .pa_start = 0x49900000, + .pa_end = 0x49900000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc1_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc1_addr_space, + .user = OCP_USER_MPU, +}; + +/* l3 main -> tpcc2 */ +static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { + { + .pa_start = 0x49a00000, + .pa_end = 0x49a00000 + SZ_8K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_tptc2_hwmod, + .clk = "l3_gclk", + .addr = am33xx_tptc2_addr_space, + .user = OCP_USER_MPU, +}; + /* l4 wkup -> uart1 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { .master = &am33xx_l4_wkup_hwmod, @@ -499,6 +2379,46 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { .user = OCP_USER_MPU, }; +/* l4 ls -> uart2 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart2_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart3 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart3_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart4 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart4_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart5 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart5_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + +/* l4 ls -> uart6 */ +static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_uart6_hwmod, + .clk = "l4ls_gclk", + .user = OCP_USER_MPU, +}; + /* l4 wkup -> wd_timer1 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { .master = &am33xx_l4_wkup_hwmod, @@ -517,39 +2437,47 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { .flags = OCPIF_SWSUP_IDLE, }; -/* rng */ -static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { - .rev_offs = 0x1fe0, - .sysc_offs = 0x1fe4, - .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, - .idlemodes = SIDLE_FORCE | SIDLE_NO, - .sysc_fields = &omap_hwmod_sysc_type1, +/* l3 main -> ocmc */ +static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_ocmcram_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class am33xx_rng_hwmod_class = { - .name = "rng", - .sysc = &am33xx_rng_sysc, +/* l3 main -> sha0 HIB2 */ +static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { + { + .pa_start = 0x53100000, + .pa_end = 0x53100000 + SZ_512 - 1, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod am33xx_rng_hwmod = { - .name = "rng", - .class = &am33xx_rng_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "rng_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_sha0_hwmod, + .clk = "sha0_fck", + .addr = am33xx_sha0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3 main -> AES0 HIB2 */ +static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { + { + .pa_start = 0x53500000, + .pa_end = 0x53500000 + SZ_1M - 1, + .flags = ADDR_TYPE_RT }, + { } }; -static struct omap_hwmod_ocp_if am33xx_l4_per__rng = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_rng_hwmod, - .clk = "rng_fck", - .user = OCP_USER_MPU, +static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_aes0_hwmod, + .clk = "aes0_fck", + .addr = am33xx_aes0_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { @@ -631,13 +2559,11 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_cpgmac0__mdio, &am33xx_l3_main__sha0, &am33xx_l3_main__aes0, - &am33xx_l4_per__rng, NULL, }; int __init am33xx_hwmod_init(void) { - omap_hwmod_am33xx_reg(); omap_hwmod_init(); return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 9e56fab..0c3a427 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -3693,53 +3693,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* - * 'ssi' class - * synchronous serial interface (multichannel and full-duplex serial if) - */ - -static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | - SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap34xx_ssi_hwmod_class = { - .name = "ssi", - .sysc = &omap34xx_ssi_sysc, -}; - -static struct omap_hwmod omap34xx_ssi_hwmod = { - .name = "ssi", - .class = &omap34xx_ssi_hwmod_class, - .clkdm_name = "core_l4_clkdm", - .main_clk = "ssi_ssr_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP3430_EN_SSI_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, - }, - }, -}; - -/* L4 CORE -> SSI */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_ssi_hwmod, - .clk = "ssi_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3865,7 +3818,6 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { #ifdef CONFIG_OMAP_IOMMU_IVA2 &omap3xxx_l3_main__mmu_iva, #endif - &omap34xx_l4_core__ssi, NULL }; diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c deleted file mode 100644 index 9002fca..0000000 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ /dev/null @@ -1,758 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Hwmod present only in AM43x and those that differ other than register - * offsets as compared to AM335x. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_data/gpio-omap.h> -#include <linux/platform_data/spi-omap2-mcspi.h> -#include "omap_hwmod.h" -#include "omap_hwmod_33xx_43xx_common_data.h" -#include "prcm43xx.h" - -/* IP blocks */ -static struct omap_hwmod am43xx_l4_hs_hwmod = { - .name = "l4_hs", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l4hs_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { - { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, -}; - -static struct omap_hwmod am43xx_wkup_m3_hwmod = { - .name = "wkup_m3", - .class = &am33xx_wkup_m3_hwmod_class, - .clkdm_name = "l4_wkup_aon_clkdm", - /* Keep hardreset asserted */ - .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, - .main_clk = "sys_clkin_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, - .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET, - .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .rst_lines = am33xx_wkup_m3_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), -}; - -static struct omap_hwmod am43xx_control_hwmod = { - .name = "control", - .class = &am33xx_control_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "sys_clkin_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { - { .role = "dbclk", .clk = "gpio0_dbclk" }, -}; - -static struct omap_hwmod am43xx_gpio0_hwmod = { - .name = "gpio1", - .class = &am33xx_gpio_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "sys_clkin_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = gpio0_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), - .dev_attr = &gpio_dev_attr, -}; - -static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x4, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am43xx_synctimer_hwmod_class = { - .name = "synctimer", - .sysc = &am43xx_synctimer_sysc, -}; - -static struct omap_hwmod am43xx_synctimer_hwmod = { - .name = "counter_32k", - .class = &am43xx_synctimer_hwmod_class, - .clkdm_name = "l4_wkup_aon_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "synctimer_32kclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer8_hwmod = { - .name = "timer8", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer8_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer9_hwmod = { - .name = "timer9", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer9_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer10_hwmod = { - .name = "timer10", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer10_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_timer11_hwmod = { - .name = "timer11", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer11_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_epwmss3_hwmod = { - .name = "epwmss3", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_ehrpwm3_hwmod = { - .name = "ehrpwm3", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -static struct omap_hwmod am43xx_epwmss4_hwmod = { - .name = "epwmss4", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_ehrpwm4_hwmod = { - .name = "ehrpwm4", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -static struct omap_hwmod am43xx_epwmss5_hwmod = { - .name = "epwmss5", - .class = &am33xx_epwmss_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_ehrpwm5_hwmod = { - .name = "ehrpwm5", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -static struct omap_hwmod am43xx_spi2_hwmod = { - .name = "spi2", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &mcspi_attrib, -}; - -static struct omap_hwmod am43xx_spi3_hwmod = { - .name = "spi3", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &mcspi_attrib, -}; - -static struct omap_hwmod am43xx_spi4_hwmod = { - .name = "spi4", - .class = &am33xx_spi_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "dpll_per_m2_div4_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .dev_attr = &mcspi_attrib, -}; - -static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { - { .role = "dbclk", .clk = "gpio4_dbclk" }, -}; - -static struct omap_hwmod am43xx_gpio4_hwmod = { - .name = "gpio5", - .class = &am33xx_gpio_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = gpio4_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), - .dev_attr = &gpio_dev_attr, -}; - -static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { - { .role = "dbclk", .clk = "gpio5_dbclk" }, -}; - -static struct omap_hwmod am43xx_gpio5_hwmod = { - .name = "gpio6", - .class = &am33xx_gpio_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = gpio5_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), - .dev_attr = &gpio_dev_attr, -}; - -static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", -}; - -static struct omap_hwmod am43xx_ocp2scp0_hwmod = { - .name = "ocp2scp0", - .class = &am43xx_ocp2scp_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_ocp2scp1_hwmod = { - .name = "ocp2scp1", - .class = &am43xx_ocp2scp_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | - MSTANDBY_NO | MSTANDBY_SMART | - MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = { - .name = "usb_otg_ss", - .sysc = &am43xx_usb_otg_ss_sysc, -}; - -static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = { - .name = "usb_otg_ss0", - .class = &am43xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { - .name = "usb_otg_ss1", - .class = &am43xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = { - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am43xx_qspi_hwmod_class = { - .name = "qspi", - .sysc = &am43xx_qspi_sysc, -}; - -static struct omap_hwmod am43xx_qspi_hwmod = { - .name = "qspi", - .class = &am43xx_qspi_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* Interfaces */ -static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { - .master = &am33xx_l3_main_hwmod, - .slave = &am43xx_l4_hs_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = { - .master = &am43xx_wkup_m3_hwmod, - .slave = &am33xx_l4_wkup_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_wkup_m3_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_pruss_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_smartreflex0_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_smartreflex1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_control_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_i2c1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_gpio0_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = { - .master = &am43xx_l4_hs_hwmod, - .slave = &am33xx_cpgmac0_hwmod, - .clk = "cpsw_125mhz_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_timer1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_uart1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_wd_timer1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_synctimer_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer8_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer9_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer10_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_timer11_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_epwmss3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = { - .master = &am43xx_epwmss3_hwmod, - .slave = &am43xx_ehrpwm3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_epwmss4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = { - .master = &am43xx_epwmss4_hwmod, - .slave = &am43xx_ehrpwm4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_epwmss5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = { - .master = &am43xx_epwmss5_hwmod, - .slave = &am43xx_ehrpwm5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_spi2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_spi3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_spi4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_gpio4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_gpio5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_ocp2scp0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am43xx_ocp2scp1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { - .master = &am33xx_l3_s_hwmod, - .slave = &am43xx_usb_otg_ss0_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { - .master = &am33xx_l3_s_hwmod, - .slave = &am43xx_usb_otg_ss1_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { - .master = &am33xx_l3_s_hwmod, - .slave = &am43xx_qspi_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_l4_wkup__synctimer, - &am43xx_l4_ls__timer8, - &am43xx_l4_ls__timer9, - &am43xx_l4_ls__timer10, - &am43xx_l4_ls__timer11, - &am43xx_l4_ls__epwmss3, - &am43xx_epwmss3__ehrpwm3, - &am43xx_l4_ls__epwmss4, - &am43xx_epwmss4__ehrpwm4, - &am43xx_l4_ls__epwmss5, - &am43xx_epwmss5__ehrpwm5, - &am43xx_l4_ls__mcspi2, - &am43xx_l4_ls__mcspi3, - &am43xx_l4_ls__mcspi4, - &am43xx_l4_ls__gpio4, - &am43xx_l4_ls__gpio5, - &am43xx_l3_main__pruss, - &am33xx_mpu__l3_main, - &am33xx_mpu__prcm, - &am33xx_l3_s__l4_ls, - &am33xx_l3_s__l4_wkup, - &am43xx_l3_main__l4_hs, - &am33xx_l3_main__l3_s, - &am33xx_l3_main__l3_instr, - &am33xx_l3_main__gfx, - &am33xx_l3_s__l3_main, - &am33xx_pruss__l3_main, - &am43xx_wkup_m3__l4_wkup, - &am33xx_gfx__l3_main, - &am43xx_l4_wkup__wkup_m3, - &am43xx_l4_wkup__control, - &am43xx_l4_wkup__smartreflex0, - &am43xx_l4_wkup__smartreflex1, - &am43xx_l4_wkup__uart1, - &am43xx_l4_wkup__timer1, - &am43xx_l4_wkup__i2c1, - &am43xx_l4_wkup__gpio0, - &am43xx_l4_wkup__wd_timer1, - &am43xx_l3_s__qspi, - &am33xx_l4_per__dcan0, - &am33xx_l4_per__dcan1, - &am33xx_l4_per__gpio1, - &am33xx_l4_per__gpio2, - &am33xx_l4_per__gpio3, - &am33xx_l4_per__i2c2, - &am33xx_l4_per__i2c3, - &am33xx_l4_per__mailbox, - &am33xx_l4_ls__mcasp0, - &am33xx_l4_ls__mcasp1, - &am33xx_l4_ls__mmc0, - &am33xx_l4_ls__mmc1, - &am33xx_l3_s__mmc2, - &am33xx_l4_ls__timer2, - &am33xx_l4_ls__timer3, - &am33xx_l4_ls__timer4, - &am33xx_l4_ls__timer5, - &am33xx_l4_ls__timer6, - &am33xx_l4_ls__timer7, - &am33xx_l3_main__tpcc, - &am33xx_l4_ls__uart2, - &am33xx_l4_ls__uart3, - &am33xx_l4_ls__uart4, - &am33xx_l4_ls__uart5, - &am33xx_l4_ls__uart6, - &am33xx_l4_ls__elm, - &am33xx_l4_ls__epwmss0, - &am33xx_epwmss0__ecap0, - &am33xx_epwmss0__eqep0, - &am33xx_epwmss0__ehrpwm0, - &am33xx_l4_ls__epwmss1, - &am33xx_epwmss1__ecap1, - &am33xx_epwmss1__eqep1, - &am33xx_epwmss1__ehrpwm1, - &am33xx_l4_ls__epwmss2, - &am33xx_epwmss2__ecap2, - &am33xx_epwmss2__eqep2, - &am33xx_epwmss2__ehrpwm2, - &am33xx_l3_s__gpmc, - &am33xx_l4_ls__mcspi0, - &am33xx_l4_ls__mcspi1, - &am33xx_l3_main__tptc0, - &am33xx_l3_main__tptc1, - &am33xx_l3_main__tptc2, - &am33xx_l3_main__ocmc, - &am43xx_l4_hs__cpgmac0, - &am33xx_cpgmac0__mdio, - &am33xx_l3_main__sha0, - &am33xx_l3_main__aes0, - &am43xx_l4_ls__ocp2scp0, - &am43xx_l4_ls__ocp2scp1, - &am43xx_l3_s__usbotgss0, - &am43xx_l3_s__usbotgss1, - NULL, -}; - -int __init am43xx_hwmod_init(void) -{ - omap_hwmod_am43xx_reg(); - omap_hwmod_init(); - return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); -} diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 1e5b12c..9c3b504 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -914,7 +914,7 @@ static struct omap_hwmod omap44xx_emif1_hwmod = { .name = "emif1", .class = &omap44xx_emif_hwmod_class, .clkdm_name = "l3_emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .main_clk = "ddrphy_ck", .prcm = { .omap4 = { @@ -930,7 +930,7 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { .name = "emif2", .class = &omap44xx_emif_hwmod_class, .clkdm_name = "l3_emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .main_clk = "ddrphy_ck", .prcm = { .omap4 = { @@ -2193,7 +2193,7 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .name = "mpu", .class = &omap44xx_mpu_hwmod_class, .clkdm_name = "mpuss_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .main_clk = "dpll_mpu_m2_ck", .prcm = { .omap4 = { diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 9e08d69..cde4155 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -352,7 +352,7 @@ static struct omap_hwmod omap54xx_emif1_hwmod = { .name = "emif1", .class = &omap54xx_emif_hwmod_class, .clkdm_name = "emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .main_clk = "dpll_core_h11x2_ck", .prcm = { .omap4 = { @@ -368,7 +368,7 @@ static struct omap_hwmod omap54xx_emif2_hwmod = { .name = "emif2", .class = &omap54xx_emif_hwmod_class, .clkdm_name = "emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .main_clk = "dpll_core_h11x2_ck", .prcm = { .omap4 = { @@ -1135,7 +1135,7 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { .name = "mpu", .class = &omap54xx_mpu_hwmod_class, .clkdm_name = "mpu_clkdm", - .flags = HWMOD_INIT_NO_IDLE, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .main_clk = "dpll_mpu_m2_ck", .prcm = { .omap4 = { @@ -1146,77 +1146,6 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { }; /* - * 'spinlock' class - * spinlock provides hardware assistance for synchronizing the processes - * running on multiple processors - */ - -static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = { - .name = "spinlock", - .sysc = &omap54xx_spinlock_sysc, -}; - -/* spinlock */ -static struct omap_hwmod omap54xx_spinlock_hwmod = { - .name = "spinlock", - .class = &omap54xx_spinlock_hwmod_class, - .clkdm_name = "l4cfg_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, - }, - }, -}; - -/* - * 'ocp2scp' class - * bridge to transform ocp interface protocol to scp (serial control port) - * protocol - */ - -static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = { - .name = "ocp2scp", - .sysc = &omap54xx_ocp2scp_sysc, -}; - -/* ocp2scp1 */ -static struct omap_hwmod omap54xx_ocp2scp1_hwmod = { - .name = "ocp2scp1", - .class = &omap54xx_ocp2scp_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* * 'timer' class * general purpose timer module with accurate 1ms tick * This class contains several variants: ['timer_1ms', 'timer'] @@ -1536,123 +1465,6 @@ static struct omap_hwmod omap54xx_uart6_hwmod = { }; /* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ - -static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap54xx_usb_host_hs_sysc, -}; - -static struct omap_hwmod omap54xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap54xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3init_clkdm", - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, - .main_clk = "l3init_60m_fclk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ - -static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap54xx_usb_tll_hs_sysc, -}; - -static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap54xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* * 'usb_otg_ss' class * 2.0 super speed (usb_otg_ss) controller */ @@ -2148,22 +1960,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_spinlock_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> ocp2scp1 */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_ocp2scp1_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { .master = &omap54xx_l4_wkup_hwmod, @@ -2300,22 +2096,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> usb_host_hs */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_usb_host_hs_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> usb_tll_hs */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_usb_tll_hs_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> usb_otg_ss */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { .master = &omap54xx_l4_cfg_hwmod, @@ -2383,8 +2163,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_per__mmc4, &omap54xx_l4_per__mmc5, &omap54xx_l4_cfg__mpu, - &omap54xx_l4_cfg__spinlock, - &omap54xx_l4_cfg__ocp2scp1, &omap54xx_l4_wkup__timer1, &omap54xx_l4_per__timer2, &omap54xx_l4_per__timer3, @@ -2402,8 +2180,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_per__uart4, &omap54xx_l4_per__uart5, &omap54xx_l4_per__uart6, - &omap54xx_l4_cfg__usb_host_hs, - &omap54xx_l4_cfg__usb_tll_hs, &omap54xx_l4_cfg__usb_otg_ss, &omap54xx_l4_wkup__wd_timer2, NULL, diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index a358a07..bd41d59 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -17,8 +17,7 @@ * GNU General Public License for more details. */ #include <linux/module.h> -#include <linux/of.h> -#include <linux/pm_opp.h> +#include <linux/opp.h> #include <linux/cpu.h> #include "omap_device.h" @@ -41,9 +40,6 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, { int i, r; - if (of_have_populated_dt()) - return -EINVAL; - if (!opp_def || !opp_def_size) { pr_err("%s: invalid params!\n", __func__); return -EINVAL; @@ -85,14 +81,14 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, dev = &oh->od->pdev->dev; } - r = dev_pm_opp_add(dev, opp_def->freq, opp_def->u_volt); + r = opp_add(dev, opp_def->freq, opp_def->u_volt); if (r) { dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n", __func__, opp_def->freq, opp_def->hwmod_name, i, r); } else { if (!opp_def->default_available) - r = dev_pm_opp_disable(dev, opp_def->freq); + r = opp_disable(dev, opp_def->freq); if (r) dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n", __func__, opp_def->freq, diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c deleted file mode 100644 index 39f020c..0000000 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Legacy platform_data quirks - * - * Copyright (C) 2013 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/clk.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/of_platform.h> -#include <linux/wl12xx.h> - -#include <linux/platform_data/pinctrl-single.h> - -#include "common.h" -#include "common-board-devices.h" -#include "dss-common.h" -#include "control.h" - -struct pdata_init { - const char *compatible; - void (*fn)(void); -}; - -/* - * Create alias for USB host PHY clock. - * Remove this when clock phandle can be provided via DT - */ -static void __init __used legacy_init_ehci_clk(char *clkname) -{ - int ret; - - ret = clk_add_alias("main_clk", NULL, clkname, NULL); - if (ret) - pr_err("%s:Failed to add main_clk alias to %s :%d\n", - __func__, clkname, ret); -} - -#if IS_ENABLED(CONFIG_WL12XX) - -static struct wl12xx_platform_data wl12xx __initdata; - -static void __init __used legacy_init_wl12xx(unsigned ref_clock, - unsigned tcxo_clock, - int gpio) -{ - int res; - - wl12xx.board_ref_clock = ref_clock; - wl12xx.board_tcxo_clock = tcxo_clock; - wl12xx.irq = gpio_to_irq(gpio); - - res = wl12xx_set_platform_data(&wl12xx); - if (res) { - pr_err("error setting wl12xx data: %d\n", res); - return; - } -} -#else -static inline void legacy_init_wl12xx(unsigned ref_clock, - unsigned tcxo_clock, - int gpio) -{ -} -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static void __init hsmmc2_internal_input_clk(void) -{ - u32 reg; - - reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); - reg |= OMAP2_MMCSDIO2ADPCLKISEL; - omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); -} - -static void __init omap3_igep0020_legacy_init(void) -{ - omap3_igep2_display_init_of(); -} - -static void __init omap3_evm_legacy_init(void) -{ - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149); -} - -static void __init omap3_zoom_legacy_init(void) -{ - legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162); -} -#endif /* CONFIG_ARCH_OMAP3 */ - -#ifdef CONFIG_ARCH_OMAP4 -static void __init omap4_sdp_legacy_init(void) -{ - omap_4430sdp_display_init_of(); - legacy_init_wl12xx(WL12XX_REFCLOCK_26, - WL12XX_TCXOCLOCK_26, 53); -} - -static void __init omap4_panda_legacy_init(void) -{ - omap4_panda_display_init_of(); - legacy_init_ehci_clk("auxclk3_ck"); - legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53); -} -#endif - -#ifdef CONFIG_SOC_OMAP5 -static void __init omap5_uevm_legacy_init(void) -{ - legacy_init_ehci_clk("auxclk1_ck"); -} -#endif - -static struct pcs_pdata pcs_pdata; - -void omap_pcs_legacy_init(int irq, void (*rearm)(void)) -{ - pcs_pdata.irq = irq; - pcs_pdata.rearm = rearm; -} - -struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { -#ifdef CONFIG_ARCH_OMAP3 - OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), - OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), -#endif -#ifdef CONFIG_ARCH_OMAP4 - OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), - OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), -#endif - { /* sentinel */ }, -}; - -static struct pdata_init pdata_quirks[] __initdata = { -#ifdef CONFIG_ARCH_OMAP3 - { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, - { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, - { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, - { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, - { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, - { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, -#endif -#ifdef CONFIG_ARCH_OMAP4 - { "ti,omap4-sdp", omap4_sdp_legacy_init, }, - { "ti,omap4-panda", omap4_panda_legacy_init, }, -#endif -#ifdef CONFIG_SOC_OMAP5 - { "ti,omap5-uevm", omap5_uevm_legacy_init, }, -#endif - { /* sentinel */ }, -}; - -void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) -{ - struct pdata_init *quirks = pdata_quirks; - - omap_sdrc_init(NULL, NULL); - of_platform_populate(NULL, omap_dt_match_table, - omap_auxdata_lookup, NULL); - - while (quirks->compatible) { - if (of_machine_is_compatible(quirks->compatible)) { - if (quirks->fn) - quirks->fn(); - break; - } - quirks++; - } -} diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index e1b4141..e742118 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -13,7 +13,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/err.h> -#include <linux/pm_opp.h> +#include <linux/opp.h> #include <linux/export.h> #include <linux/suspend.h> #include <linux/cpu.h> @@ -131,7 +131,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, { struct voltagedomain *voltdm; struct clk *clk; - struct dev_pm_opp *opp; + struct opp *opp; unsigned long freq, bootup_volt; struct device *dev; @@ -172,7 +172,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, clk_put(clk); rcu_read_lock(); - opp = dev_pm_opp_find_freq_ceil(dev, &freq); + opp = opp_find_freq_ceil(dev, &freq); if (IS_ERR(opp)) { rcu_read_unlock(); pr_err("%s: unable to find boot up OPP for vdd_%s\n", @@ -180,7 +180,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, goto exit; } - bootup_volt = dev_pm_opp_get_voltage(opp); + bootup_volt = opp_get_voltage(opp); rcu_read_unlock(); if (!bootup_volt) { pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", @@ -266,12 +266,7 @@ static void __init omap4_init_voltages(void) static inline void omap_init_cpufreq(void) { - struct platform_device_info devinfo = { }; - - if (!of_have_populated_dt()) - devinfo.name = "omap-cpufreq"; - else - devinfo.name = "cpufreq-cpu0"; + struct platform_device_info devinfo = { .name = "omap-cpufreq", }; platform_device_register_full(&devinfo); } @@ -305,11 +300,10 @@ int __init omap2_common_pm_late_init(void) /* Smartreflex device init */ omap_devinit_smartreflex(); + /* cpufreq dummy device instantiation */ + omap_init_cpufreq(); } - /* cpufreq dummy device instantiation */ - omap_init_cpufreq(); - #ifdef CONFIG_SUSPEND suspend_set_ops(&omap_pm_ops); #endif diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 8c07594..ce956b0 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -62,6 +62,16 @@ static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; static struct clk *osc_ck, *emul_ck; +static int omap2_fclks_active(void) +{ + u32 f1, f2; + + f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + + return (f1 | f2) ? 1 : 0; +} + static int omap2_enter_full_retention(void) { u32 l; @@ -132,7 +142,17 @@ static int sti_console_enabled; static int omap2_allow_mpu_retention(void) { - if (!omap2xxx_cm_mpu_retention_allowed()) + u32 l; + + /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | + OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | + OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) + return 0; + /* Check for UART3. */ + l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + if (l & OMAP24XX_EN_UART3_MASK) return 0; if (sti_console_enabled) return 0; @@ -168,7 +188,7 @@ static void omap2_enter_mpu_retention(void) static int omap2_can_sleep(void) { - if (omap2xxx_cm_fclks_active()) + if (omap2_fclks_active()) return 0; if (__clk_is_enabled(osc_ck)) return 0; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 1f3770a..5a2d803 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -120,7 +120,7 @@ static void omap3_save_secure_ram_context(void) * will hang the system. */ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); - ret = _omap_save_secure_sram((u32 *)(unsigned long) + ret = _omap_save_secure_sram((u32 *) __pa(omap3_secure_ram_storage)); pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); /* Following is for error tracking, it should not happen */ @@ -430,7 +430,8 @@ static void __init omap3_iva_idle(void) OMAP3430_IVA2_MOD, CM_FCLKEN); /* Set IVA2 boot mode to 'idle' */ - omap3_ctrl_set_iva_bootmode_idle(); + omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, + OMAP343X_CONTROL_IVA2_BOOTMOD); /* Un-reset IVA2 */ omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 93a2a6e..e233dfc 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -128,8 +128,7 @@ skip_voltdm: for (i = 0; i < pwrdm->banks; i++) pwrdm->ret_mem_off_counter[i] = 0; - if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition) - arch_pwrdm->pwrdm_wait_transition(pwrdm); + arch_pwrdm->pwrdm_wait_transition(pwrdm); pwrdm->state = pwrdm_read_pwrst(pwrdm); pwrdm->state_counter[pwrdm->state] = 1; diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index da5a59a..baf3d8b 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -257,7 +257,6 @@ extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); extern void omap54xx_powerdomains_init(void); extern void dra7xx_powerdomains_init(void); -void am43xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; diff --git a/arch/arm/mach-omap2/powerdomains43xx_data.c b/arch/arm/mach-omap2/powerdomains43xx_data.c deleted file mode 100644 index 95fee54..0000000 --- a/arch/arm/mach-omap2/powerdomains43xx_data.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * AM43xx Power domains framework - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include "powerdomain.h" - -#include "prcm-common.h" -#include "prcm44xx.h" -#include "prcm43xx.h" - -static struct powerdomain gfx_43xx_pwrdm = { - .name = "gfx_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM43XX_PRM_GFX_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_ON, - .banks = 1, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* gfx_mem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -static struct powerdomain mpu_43xx_pwrdm = { - .name = "mpu_pwrdm", - .voltdm = { .name = "mpu" }, - .prcm_offs = AM43XX_PRM_MPU_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 3, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* mpu_l1 */ - [1] = PWRSTS_OFF_RET, /* mpu_l2 */ - [2] = PWRSTS_OFF_RET, /* mpu_ram */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* mpu_l1 */ - [1] = PWRSTS_ON, /* mpu_l2 */ - [2] = PWRSTS_ON, /* mpu_ram */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -static struct powerdomain rtc_43xx_pwrdm = { - .name = "rtc_pwrdm", - .voltdm = { .name = "rtc" }, - .prcm_offs = AM43XX_PRM_RTC_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_ON, -}; - -static struct powerdomain wkup_43xx_pwrdm = { - .name = "wkup_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM43XX_PRM_WKUP_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_ON, - .banks = 1, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* debugss_mem */ - }, -}; - -static struct powerdomain tamper_43xx_pwrdm = { - .name = "tamper_pwrdm", - .voltdm = { .name = "tamper" }, - .prcm_offs = AM43XX_PRM_TAMPER_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_ON, -}; - -static struct powerdomain cefuse_43xx_pwrdm = { - .name = "cefuse_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM43XX_PRM_CEFUSE_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_ON, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -static struct powerdomain per_43xx_pwrdm = { - .name = "per_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM43XX_PRM_PER_INST, - .prcm_partition = AM43XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .banks = 4, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* icss_mem */ - [1] = PWRSTS_OFF_RET, /* per_mem */ - [2] = PWRSTS_OFF_RET, /* ram1_mem */ - [3] = PWRSTS_OFF_RET, /* ram2_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* icss_mem */ - [1] = PWRSTS_ON, /* per_mem */ - [2] = PWRSTS_ON, /* ram1_mem */ - [3] = PWRSTS_ON, /* ram2_mem */ - }, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, -}; - -static struct powerdomain *powerdomains_am43xx[] __initdata = { - &gfx_43xx_pwrdm, - &mpu_43xx_pwrdm, - &rtc_43xx_pwrdm, - &wkup_43xx_pwrdm, - &tamper_43xx_pwrdm, - &cefuse_43xx_pwrdm, - &per_43xx_pwrdm, - NULL -}; - -static int am43xx_check_vcvp(void) -{ - return 0; -} - -void __init am43xx_powerdomains_init(void) -{ - omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp; - pwrdm_register_platform_funcs(&omap4_pwrdm_operations); - pwrdm_register_pwrdms(powerdomains_am43xx); - pwrdm_complete_init(); -} diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h deleted file mode 100644 index 7785be9..0000000 --- a/arch/arm/mach-omap2/prcm43xx.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * AM43x PRCM defines - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H -#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H - -#define AM43XX_PRM_PARTITION 1 -#define AM43XX_CM_PARTITION 1 - -/* PRM instances */ -#define AM43XX_PRM_OCP_SOCKET_INST 0x0000 -#define AM43XX_PRM_MPU_INST 0x0300 -#define AM43XX_PRM_GFX_INST 0x0400 -#define AM43XX_PRM_RTC_INST 0x0500 -#define AM43XX_PRM_TAMPER_INST 0x0600 -#define AM43XX_PRM_CEFUSE_INST 0x0700 -#define AM43XX_PRM_PER_INST 0x0800 -#define AM43XX_PRM_WKUP_INST 0x2000 -#define AM43XX_PRM_DEVICE_INST 0x4000 - -/* RM RSTCTRL offsets */ -#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 -#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 -#define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 - -/* RM RSTST offsets */ -#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 -#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 - -/* CM instances */ -#define AM43XX_CM_WKUP_INST 0x2800 -#define AM43XX_CM_DEVICE_INST 0x4100 -#define AM43XX_CM_DPLL_INST 0x4200 -#define AM43XX_CM_MPU_INST 0x8300 -#define AM43XX_CM_GFX_INST 0x8400 -#define AM43XX_CM_RTC_INST 0x8500 -#define AM43XX_CM_TAMPER_INST 0x8600 -#define AM43XX_CM_CEFUSE_INST 0x8700 -#define AM43XX_CM_PER_INST 0x8800 - -/* CD offsets */ -#define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000 -#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100 -#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200 -#define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300 -#define AM43XX_CM_MPU_MPU_CDOFFS 0x0000 -#define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000 -#define AM43XX_CM_RTC_RTC_CDOFFS 0x0000 -#define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000 -#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000 -#define AM43XX_CM_PER_L3_CDOFFS 0x0000 -#define AM43XX_CM_PER_L3S_CDOFFS 0x0200 -#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 -#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 -#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 -#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 -#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 -#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 - -/* CLK CTRL offsets */ -#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 -#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 -#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 -#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 -#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 -#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 -#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 -#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 -#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 -#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 -#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 -#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 -#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 -#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 -#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 -#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 -#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 -#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 -#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 -#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 -#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 -#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 -#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 -#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 -#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 -#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 -#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 -#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 -#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 -#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 -#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 -#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 -#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 -#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 -#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 -#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 -#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 -#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 -#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 -#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 -#define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 -#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 -#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 -#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 -#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 -#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 -#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 -#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 -#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 -#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 -#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 -#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 -#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 -#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 -#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 -#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 -#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 -#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 -#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 -#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 -#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 -#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 -#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 -#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 -#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 -#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 -#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 -#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 -#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 -#define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 -#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 -#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 -#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 - -#endif diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h index f8eb833..277f717 100644 --- a/arch/arm/mach-omap2/prm3xxx.h +++ b/arch/arm/mach-omap2/prm3xxx.h @@ -144,13 +144,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset); extern void omap3_prm_vcvp_write(u32 val, u8 offset); extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); -#ifdef CONFIG_ARCH_OMAP3 -void omap3xxx_prm_reconfigure_io_chain(void); -#else -static inline void omap3xxx_prm_reconfigure_io_chain(void) -{ -} -#endif +extern void omap3xxx_prm_reconfigure_io_chain(void); /* PRM interrupt-related functions */ extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h index 8d95aa5..7cd22ab 100644 --- a/arch/arm/mach-omap2/prm44xx_54xx.h +++ b/arch/arm/mach-omap2/prm44xx_54xx.h @@ -42,14 +42,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset); extern void omap4_prm_vcvp_write(u32 val, u8 offset); extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ - defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX) -void omap44xx_prm_reconfigure_io_chain(void); -#else -static inline void omap44xx_prm_reconfigure_io_chain(void) -{ -} -#endif +extern void omap44xx_prm_reconfigure_io_chain(void); /* PRM interrupt-related functions */ extern void omap44xx_prm_read_pending_irqs(unsigned long *events); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index a2e1174..228b850 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -24,7 +24,6 @@ #include <linux/interrupt.h> #include <linux/slab.h> -#include "soc.h" #include "prm2xxx_3xxx.h" #include "prm2xxx.h" #include "prm3xxx.h" @@ -323,16 +322,6 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) prcm_irq_chips[i] = gc; } - if (of_have_populated_dt()) { - int irq = omap_prcm_event_to_irq("io"); - if (cpu_is_omap34xx()) - omap_pcs_legacy_init(irq, - omap3xxx_prm_reconfigure_io_chain); - else - omap_pcs_legacy_init(irq, - omap44xx_prm_reconfigure_io_chain); - } - return 0; err: diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 076bd90..4588df1 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -455,7 +455,9 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) #define OMAP54XX_CLASS 0x54000054 +#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) #define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) +#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) #define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 3ca81e0..ead48fa 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -55,7 +55,6 @@ #include "soc.h" #include "common.h" #include "powerdomain.h" -#include "omap-secure.h" #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 @@ -67,15 +66,6 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; -#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER -static unsigned long arch_timer_freq; - -void set_cntfreq(void) -{ - omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); -} -#endif - static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_gpt; @@ -88,7 +78,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) static struct irqaction omap2_gp_timer_irq = { .name = "gp_timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = omap2_gp_timer_interrupt, }; @@ -525,10 +515,6 @@ static void __init realtime_counter_init(void) num = 8; den = 25; break; - case 20000000: - num = 192; - den = 625; - break; case 2600000: num = 384; den = 1625; @@ -556,9 +542,6 @@ static void __init realtime_counter_init(void) reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); - arch_timer_freq = (rate / den) * num; - set_cntfreq(); - iounmap(base); } #else diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index b0d54da..c05898f 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -24,7 +24,6 @@ #include <linux/i2c/twl.h> #include <linux/gpio.h> #include <linux/string.h> -#include <linux/phy/phy.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -91,18 +90,8 @@ void __init omap_pmic_late_init(void) } #if defined(CONFIG_ARCH_OMAP3) -struct phy_consumer consumers[] = { - PHY_CONSUMER("musb-hdrc.0", "usb"), -}; - -struct phy_init_data init_data = { - .consumers = consumers, - .num_consumers = ARRAY_SIZE(consumers), -}; - static struct twl4030_usb_data omap3_usb_pdata = { .usb_mode = T2_USB_MODE_ULPI, - .init_data = &init_data, }; static int omap3_batt_table[] = { diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 10855eb..e83a6a4 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -435,7 +435,6 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) struct platform_device *pdev; char *phy_id; struct platform_device_info pdevinfo; - struct usb_phy_gen_xceiv_platform_data nop_pdata; for (i = 0; i < num_phys; i++) { @@ -456,18 +455,11 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) return -ENOMEM; } - /* set platform data */ - memset(&nop_pdata, 0, sizeof(nop_pdata)); - if (gpio_is_valid(phy->vcc_gpio)) - nop_pdata.needs_vcc = true; - nop_pdata.gpio_reset = phy->reset_gpio; - nop_pdata.type = USB_PHY_TYPE_USB2; - /* create a NOP PHY device */ memset(&pdevinfo, 0, sizeof(pdevinfo)); pdevinfo.name = nop_name; pdevinfo.id = phy->port; - pdevinfo.data = &nop_pdata; + pdevinfo.data = phy->platform_data; pdevinfo.size_data = sizeof(struct usb_phy_gen_xceiv_platform_data); scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d", @@ -482,6 +474,14 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id); + /* Do we need RESET regulator ? */ + if (gpio_is_valid(phy->reset_gpio)) { + scnprintf(rail_name, MAX_STR, + "hsusb%d_reset", phy->port); + usbhs_add_regulator(rail_name, phy_id, "reset", + phy->reset_gpio, 1); + } + /* Do we need VCC regulator ? */ if (gpio_is_valid(phy->vcc_gpio)) { scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port); diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h index 4ba2ae7..e7261eb 100644 --- a/arch/arm/mach-omap2/usb.h +++ b/arch/arm/mach-omap2/usb.h @@ -58,6 +58,7 @@ struct usbhs_phy_data { int reset_gpio; int vcc_gpio; bool vcc_polarity; /* 1 active high, 0 active low */ + void *platform_data; }; extern void usb_musb_init(struct omap_musb_board_data *board_data); diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index d49aff7..e110b6d 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -6,6 +6,7 @@ * Licensed under GPLv2 or later. */ +#include <linux/clocksource.h> #include <linux/init.h> #include <linux/kernel.h> #include <asm/sizes.h> @@ -20,6 +21,13 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } +static __init void sirfsoc_init_time(void) +{ + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); + clocksource_of_init(); +} + static __init void sirfsoc_map_io(void) { sirfsoc_map_lluart(); @@ -35,6 +43,7 @@ static const char *atlas6_dt_match[] __initdata = { DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .map_io = sirfsoc_map_io, + .init_time = sirfsoc_init_time, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, .restart = sirfsoc_restart, @@ -50,6 +59,7 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .map_io = sirfsoc_map_io, + .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, .init_late = sirfsoc_init_late, .dt_compat = prima2_dt_match, @@ -67,6 +77,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .smp = smp_ops(sirfsoc_smp_ops), .map_io = sirfsoc_map_io, + .init_time = sirfsoc_init_time, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, .restart = sirfsoc_restart, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 4b76806..a630485 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -23,6 +23,7 @@ extern void sirfsoc_secondary_startup(void); extern void sirfsoc_cpu_die(unsigned int cpu); extern void __init sirfsoc_of_irq_init(void); +extern void __init sirfsoc_of_clk_init(void); extern void sirfsoc_restart(enum reboot_mode, const char *); extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs); diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 96100db..a842711 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -615,12 +615,14 @@ endmenu config PXA25x bool select CPU_XSCALE + select CPU_FREQ_TABLE if CPU_FREQ help Select code specific to PXA21x/25x/26x variants config PXA27x bool select CPU_XSCALE + select CPU_FREQ_TABLE if CPU_FREQ help Select code specific to PXA27x variants @@ -633,6 +635,7 @@ config CPU_PXA26x config PXA3xx bool select CPU_XSC3 + select CPU_FREQ_TABLE if CPU_FREQ help Select code specific to PXA3xx variants diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 584439b..f942349 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -310,7 +310,6 @@ static struct platform_pwm_backlight_data cm_x300_backlight_data = { .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 10000, - .enable_gpio = -1, }; static struct platform_device cm_x300_backlight_device = { diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 3aa2646..2d4a7b4 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -189,7 +189,6 @@ static struct platform_pwm_backlight_data income_backlight_data = { .max_brightness = 0x3ff, .dft_brightness = 0x1ff, .pwm_period_ns = 1000000, - .enable_gpio = -1, }; static struct platform_device income_backlight = { diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index ab93441..fe2eb83 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -54,7 +54,6 @@ static struct platform_pwm_backlight_data ezx_backlight_data = { .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, - .enable_gpio = -1, }; static struct platform_device ezx_backlight_device = { diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index a7c30eb..133109e 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -561,7 +561,6 @@ static struct platform_pwm_backlight_data backlight_data = { .max_brightness = 200, .dft_brightness = 100, .pwm_period_ns = 30923, - .enable_gpio = -1, }; static struct platform_device backlight = { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/mach-pxa/include/mach/gpio.h index 50b99a2..0248e43 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/mach-pxa/include/mach/gpio.h @@ -1,5 +1,9 @@ /* - * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * arch/arm/mach-pxa/include/mach/gpio.h + * + * PXA GPIO wrappers for arch-neutral GPIO calls + * + * Written by Philipp Zabel <philipp.zabel@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -8,30 +12,21 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * */ -/include/ "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; +#ifndef __ASM_ARCH_PXA_GPIO_H +#define __ASM_ARCH_PXA_GPIO_H - chosen { - bootargs = "console=ttyS0,115200"; - }; +#include <asm-generic/gpio.h> - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; -}; +#include <mach/irqs.h> +#include <mach/hardware.h> -&gmac1 { - status = "okay"; -}; +#endif diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 9f6ec16..1255ee0 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -269,7 +269,6 @@ static struct platform_pwm_backlight_data lpd270_backlight_data = { .max_brightness = 1, .dft_brightness = 1, .pwm_period_ns = 78770, - .enable_gpio = -1, }; static struct platform_device lpd270_backlight_device = { diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index fab30d6..f44532f 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -378,7 +378,6 @@ static struct platform_pwm_backlight_data backlight_data = { .max_brightness = 272, .dft_brightness = 100, .pwm_period_ns = 30923, - .enable_gpio = -1, .init = magician_backlight_init, .notify = magician_backlight_notify, .exit = magician_backlight_exit, diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 08ccc07..dd70343 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -338,7 +338,6 @@ static struct platform_pwm_backlight_data mainstone_backlight_data = { .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, - .enable_gpio = -1, }; static struct platform_device mainstone_backlight_device = { diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index f70583f..acc9d3c 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -186,7 +186,6 @@ static struct platform_pwm_backlight_data mioa701_backlight_data = { .max_brightness = 100, .dft_brightness = 50, .pwm_period_ns = 4000 * 1024, /* Fl = 250kHz */ - .enable_gpio = -1, }; /* diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index e54a296..17d4c53 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -322,7 +322,6 @@ static struct platform_pwm_backlight_data palm27x_backlight_data = { .max_brightness = 0xfe, .dft_brightness = 0x7e, .pwm_period_ns = 3500 * 1024, - .enable_gpio = -1, .init = palm27x_backlight_init, .notify = palm27x_backlight_notify, .exit = palm27x_backlight_exit, diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 7691c97..100b176f 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -166,12 +166,45 @@ static inline void palmtc_keys_init(void) {} * Backlight ******************************************************************************/ #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +static int palmtc_backlight_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_PALMTC_BL_POWER, "BL POWER"); + if (ret) + goto err; + ret = gpio_direction_output(GPIO_NR_PALMTC_BL_POWER, 1); + if (ret) + goto err2; + + return 0; + +err2: + gpio_free(GPIO_NR_PALMTC_BL_POWER); +err: + return ret; +} + +static int palmtc_backlight_notify(struct device *dev, int brightness) +{ + /* backlight is on when GPIO16 AF0 is high */ + gpio_set_value(GPIO_NR_PALMTC_BL_POWER, brightness); + return brightness; +} + +static void palmtc_backlight_exit(struct device *dev) +{ + gpio_free(GPIO_NR_PALMTC_BL_POWER); +} + static struct platform_pwm_backlight_data palmtc_backlight_data = { .pwm_id = 1, .max_brightness = PALMTC_MAX_INTENSITY, .dft_brightness = PALMTC_MAX_INTENSITY, .pwm_period_ns = PALMTC_PERIOD_NS, - .enable_gpio = GPIO_NR_PALMTC_BL_POWER, + .init = palmtc_backlight_init, + .notify = palmtc_backlight_notify, + .exit = palmtc_backlight_exit, }; static struct platform_device palmtc_backlight = { diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 956fd24..0742721 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -165,7 +165,6 @@ static struct platform_pwm_backlight_data palmte2_backlight_data = { .max_brightness = PALMTE2_MAX_INTENSITY, .dft_brightness = PALMTE2_MAX_INTENSITY, .pwm_period_ns = PALMTE2_PERIOD_NS, - .enable_gpio = -1, .init = palmte2_backlight_init, .notify = palmte2_backlight_notify, .exit = palmte2_backlight_exit, diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9a4e470..3133ba8 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -153,7 +153,6 @@ static struct platform_pwm_backlight_data pcm990_backlight_data = { .max_brightness = 1023, .dft_brightness = 1023, .pwm_period_ns = 78770, - .enable_gpio = -1, }; static struct platform_device pcm990_backlight_device = { diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 8386dc3..969b0ba 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -539,7 +539,6 @@ static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = { .dft_brightness = 100, /* 10000 ns = 10 ms ^= 100 kHz */ .pwm_period_ns = 10000, - .enable_gpio = -1, }; static struct platform_device raumfeld_pwm_backlight_device = { diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 01de542..62aea3e 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -27,7 +27,7 @@ #include <linux/i2c/pxa-i2c.h> #include <linux/i2c/pcf857x.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/smc91x.h> #include <linux/gpio.h> #include <linux/leds.h> diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index a71da84..4680efe 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -175,7 +175,6 @@ static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 100000, - .enable_gpio = -1, }, [1] = { /* secondary backlight */ @@ -183,7 +182,6 @@ static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 100000, - .enable_gpio = -1, }, }; diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 29905b1..9c363c0 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -401,7 +401,6 @@ static struct platform_pwm_backlight_data viper_backlight_data = { .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 1000000, - .enable_gpio = -1, .init = viper_backlight_init, .notify = viper_backlight_notify, .exit = viper_backlight_exit, diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index e1a121b..2513d8f 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -206,7 +206,6 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { .max_brightness = 1023, .dft_brightness = 0, .pwm_period_ns = 1260320, - .enable_gpio = -1, }, [1] = { /* LCD Backlight */ @@ -214,7 +213,6 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { .max_brightness = 1023, .dft_brightness = 512, .pwm_period_ns = 1260320, - .enable_gpio = -1, }, }; diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 77daea4..36cf7cf 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -125,7 +125,6 @@ static struct platform_pwm_backlight_data zylonite_backlight_data = { .max_brightness = 100, .dft_brightness = 100, .pwm_period_ns = 10000, - .enable_gpio = -1, }; static struct platform_device zylonite_backlight_device = { diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index cf073de..25ee12b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -5,13 +5,12 @@ config ARCH_ROCKCHIP select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CACHE_L2X0 - select HAVE_ARM_TWD if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS select HAVE_SMP + select LOCAL_TIMERS if SMP select COMMON_CLK select GENERIC_CLOCKEVENTS select DW_APB_TIMER_OF - select ARM_GLOBAL_TIMER - select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK help Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs containing the RK2928, RK30xx and RK31xx series. diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 82c0b07..724d2d8 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -19,10 +19,18 @@ #include <linux/init.h> #include <linux/of_platform.h> #include <linux/irqchip.h> +#include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/hardware/cache-l2x0.h> +static void __init rockchip_timer_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + static void __init rockchip_dt_init(void) { l2x0_of_init(0, ~0UL); @@ -39,5 +47,6 @@ static const char * const rockchip_board_dt_compat[] = { DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") .init_machine = rockchip_dt_init, + .init_time = rockchip_timer_init, .dt_compat = rockchip_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 8f1d327..dba2173 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -28,7 +28,6 @@ config CPU_S3C2410 select CPU_ARM920T select CPU_LLSERIAL_S3C2410 select S3C2410_CLOCK - select S3C2410_DMA if S3C24XX_DMA select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ select S3C2410_PM if PM select SAMSUNG_WDT_RESET @@ -71,7 +70,6 @@ config CPU_S3C2442 select CPU_ARM920T select CPU_LLSERIAL_S3C2440 select S3C2410_CLOCK - select S3C2410_DMA if S3C24XX_DMA select S3C2410_PM if PM help Support for S3C2442 Samsung Mobile CPU based systems. @@ -150,6 +148,7 @@ config S3C2410_DMA_DEBUG config S3C2410_DMA bool depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) + default y if CPU_S3C2410 || CPU_S3C2442 help DMA device selection for S3C2410 and compatible CPUs diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c index 11b3b28..d8f253f 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c @@ -484,22 +484,22 @@ static struct clk init_clocks_disable[] = { static struct clk init_clocks[] = { { - .name = "dma.0", + .name = "dma", .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA0, }, { - .name = "dma.1", + .name = "dma", .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA1, }, { - .name = "dma.2", + .name = "dma", .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA2, }, { - .name = "dma.3", + .name = "dma", .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit = S3C2412_CLKCON_DMA3, diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c index 65d3eef..f6b9f2e 100644 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/arch/arm/mach-s3c24xx/common-s3c2443.c @@ -438,32 +438,32 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { - .name = "dma.0", + .name = "dma", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA0, }, { - .name = "dma.1", + .name = "dma", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA1, }, { - .name = "dma.2", + .name = "dma", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA2, }, { - .name = "dma.3", + .name = "dma", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA3, }, { - .name = "dma.4", + .name = "dma", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA4, }, { - .name = "dma.5", + .name = "dma", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_DMA5, diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 4adaa4b..457261c 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -31,7 +31,6 @@ #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/platform_data/dma-s3c24xx.h> #include <mach/hardware.h> #include <mach/regs-clock.h> @@ -45,7 +44,6 @@ #include <mach/regs-gpio.h> #include <plat/regs-serial.h> -#include <mach/dma.h> #include <plat/cpu.h> #include <plat/devs.h> @@ -331,207 +329,3 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, clk_p.rate = pclk; clk_f.rate = fclk; } - -#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ - defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -static struct resource s3c2410_dma_resource[] = { - [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), - [1] = DEFINE_RES_IRQ(IRQ_DMA0), - [2] = DEFINE_RES_IRQ(IRQ_DMA1), - [3] = DEFINE_RES_IRQ(IRQ_DMA2), - [4] = DEFINE_RES_IRQ(IRQ_DMA3), -}; -#endif - -#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442) -static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | - S3C24XX_DMA_CHANREQ(2, 2) | - S3C24XX_DMA_CHANREQ(1, 3), - }, - [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, - [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | - S3C24XX_DMA_CHANREQ(3, 2) | - S3C24XX_DMA_CHANREQ(3, 3), - }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | - S3C24XX_DMA_CHANREQ(1, 2), - }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), }, - [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, - [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, - [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, - [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, -}; - -static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { - .num_phy_channels = 4, - .channels = s3c2410_dma_channels, - .num_channels = DMACH_MAX, -}; - -struct platform_device s3c2410_device_dma = { - .name = "s3c2410-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dma_resource), - .resource = s3c2410_dma_resource, - .dev = { - .platform_data = &s3c2410_dma_platdata, - }, -}; -#endif - -#ifdef CONFIG_CPU_S3C2412 -static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, - [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, - [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, - [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, - [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, - [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, - [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, - [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, - [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 }, - [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 }, - [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 }, - [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, -}; - -static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { - .num_phy_channels = 4, - .channels = s3c2412_dma_channels, - .num_channels = DMACH_MAX, -}; - -struct platform_device s3c2412_device_dma = { - .name = "s3c2412-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dma_resource), - .resource = s3c2410_dma_resource, - .dev = { - .platform_data = &s3c2412_dma_platdata, - }, -}; -#endif - -#if defined(CONFIG_CPU_S3C2440) -static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | - S3C24XX_DMA_CHANREQ(6, 1) | - S3C24XX_DMA_CHANREQ(2, 2) | - S3C24XX_DMA_CHANREQ(1, 3), - }, - [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, - [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | - S3C24XX_DMA_CHANREQ(3, 2) | - S3C24XX_DMA_CHANREQ(3, 3), - }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | - S3C24XX_DMA_CHANREQ(1, 2), - }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) | - S3C24XX_DMA_CHANREQ(0, 2), - }, - [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) | - S3C24XX_DMA_CHANREQ(5, 2), - }, - [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) | - S3C24XX_DMA_CHANREQ(6, 3), - }, - [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) | - S3C24XX_DMA_CHANREQ(5, 3), - }, - [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, - [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, - [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, - [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, -}; - -static struct s3c24xx_dma_platdata s3c2440_dma_platdata = { - .num_phy_channels = 4, - .channels = s3c2440_dma_channels, - .num_channels = DMACH_MAX, -}; - -struct platform_device s3c2440_device_dma = { - .name = "s3c2410-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2410_dma_resource), - .resource = s3c2410_dma_resource, - .dev = { - .platform_data = &s3c2440_dma_platdata, - }, -}; -#endif - -#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416) -static struct resource s3c2443_dma_resource[] = { - [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), - [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0), - [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1), - [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2), - [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3), - [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4), - [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5), -}; - -static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { - [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, - [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, - [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, - [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, - [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, - [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, - [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, - [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, - [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, - [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, - [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 }, - [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, - [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, - [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, - [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 }, - [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, - [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, - [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, - [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 }, - [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 }, - [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, -}; - -static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { - .num_phy_channels = 6, - .channels = s3c2443_dma_channels, - .num_channels = DMACH_MAX, -}; - -struct platform_device s3c2443_device_dma = { - .name = "s3c2443-dma", - .id = 0, - .num_resources = ARRAY_SIZE(s3c2443_dma_resource), - .resource = s3c2443_dma_resource, - .dev = { - .platform_data = &s3c2443_dma_platdata, - }, -}; -#endif diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index e46c104..84b2806 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h @@ -109,9 +109,4 @@ extern void s3c2443_init_irq(void); extern struct syscore_ops s3c24xx_irq_syscore_ops; -extern struct platform_device s3c2410_device_dma; -extern struct platform_device s3c2412_device_dma; -extern struct platform_device s3c2440_device_dma; -extern struct platform_device s3c2443_device_dma; - #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index 952b6a0..74dd479 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -504,7 +504,6 @@ static struct platform_pwm_backlight_data backlight_data = { .dft_brightness = 50, /* tcnt = 0x31 */ .pwm_period_ns = 36296, - .enable_gpio = -1, .init = h1940_backlight_init, .notify = h1940_backlight_notify, .exit = h1940_backlight_exit, diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index 43c23e2..a45fcd8 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c @@ -466,7 +466,6 @@ static struct platform_device *jive_devices[] __initdata = { &jive_device_wm8750, &s3c_device_nand, &s3c_device_usbgadget, - &s3c2412_device_dma, }; static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index 4a18d49..a83db46 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -24,7 +24,7 @@ #include <linux/io.h> #include <linux/serial_core.h> #include <linux/dm9000.h> -#include <linux/platform_data/at24.h> +#include <linux/i2c/at24.h> #include <linux/platform_device.h> #include <linux/gpio_keys.h> #include <linux/i2c.h> diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index 034b7fe..206b1f7 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -522,7 +522,6 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = { .max_brightness = 24, .dft_brightness = 4, .pwm_period_ns = 48000, - .enable_gpio = -1, .init = rx1950_backlight_init, .notify = rx1950_backlight_notify, .exit = rx1950_backlight_exit, diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c index c9d31ef..8146e92 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c @@ -89,7 +89,6 @@ static struct platform_device *smdk2413_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_iis, &s3c_device_usbgadget, - &s3c2412_device_dma, }; static void __init smdk2413_fixup(struct tag *tags, char **cmdline, diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c index f88e672..cb46847 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -215,7 +215,6 @@ static struct platform_device *smdk2416_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_usb_hsudc, - &s3c2443_device_dma, }; static void __init smdk2416_map_io(void) diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c index d9933fc..9435c3b 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c @@ -115,7 +115,6 @@ static struct platform_device *smdk2443_devices[] __initdata = { #ifdef CONFIG_SND_SOC_SMDK2443_WM9710 &s3c_device_ac97, #endif - &s3c2443_device_dma, }; static void __init smdk2443_map_io(void) diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c index f7ec9c5..b665884 100644 --- a/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/arch/arm/mach-s3c24xx/mach-vstms.c @@ -126,7 +126,6 @@ static struct platform_device *vstms_devices[] __initdata = { &s3c_device_iis, &s3c_device_rtc, &s3c_device_nand, - &s3c2412_device_dma, }; static void __init vstms_fixup(struct tag *tags, char **cmdline, diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 2cb8dc5..041da51 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -3,7 +3,16 @@ # # Licensed under GPLv2 -if ARCH_S3C64XX +# temporary until we can eliminate all drivers using it. +config PLAT_S3C64XX + bool + depends on ARCH_S3C64XX + default y + select PM_GENERIC_DOMAINS + select SAMSUNG_WAKEMASK + help + Base platform code for any Samsung S3C64XX device + # Configuration options for the S3C6410 CPU @@ -297,21 +306,3 @@ config MACH_WLF_CRAGG_6410 select SAMSUNG_GPIO_EXTRA128 help Machine support for the Wolfson Cragganmore S3C6410 variant. - -config MACH_S3C64XX_DT - bool "Samsung S3C6400/S3C6410 machine using Device Tree" - select CLKSRC_OF - select CPU_S3C6400 - select CPU_S3C6410 - select PINCTRL - select PINCTRL_S3C64XX - select USE_OF - help - Machine support for Samsung S3C6400/S3C6410 machines with Device Tree - enabled. - Select this if a fdt blob is available for your S3C64XX SoC based - board. - Note: This is under development and not all peripherals can be - supported with this machine file. - -endif diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 6faedcf..31d0c91 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -12,7 +12,7 @@ obj- := # Core -obj-y += common.o +obj-y += common.o clock.o # Core support @@ -57,4 +57,3 @@ obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o -obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c new file mode 100644 index 0000000..c1bcc4a --- /dev/null +++ b/arch/arm/mach-s3c64xx/clock.c @@ -0,0 +1,1007 @@ +/* linux/arch/arm/plat-s3c64xx/clock.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX Base clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <mach/regs-clock.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/cpu-freq.h> +#include <plat/clock.h> +#include <plat/clock-clksrc.h> +#include <plat/pll.h> + +#include "regs-sys.h" + +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call + * ext_xtal_mux for want of an actual name from the manual. +*/ + +static struct clk clk_ext_xtal_mux = { + .name = "ext_xtal", +}; + +#define clk_fin_apll clk_ext_xtal_mux +#define clk_fin_mpll clk_ext_xtal_mux +#define clk_fin_epll clk_ext_xtal_mux + +#define clk_fout_mpll clk_mpll +#define clk_fout_epll clk_epll + +struct clk clk_h2 = { + .name = "hclk2", + .rate = 0, +}; + +struct clk clk_27m = { + .name = "clk_27m", + .rate = 27000000, +}; + +static int clk_48m_ctrl(struct clk *clk, int enable) +{ + unsigned long flags; + u32 val; + + /* can't rely on clock lock, this register has other usages */ + local_irq_save(flags); + + val = __raw_readl(S3C64XX_OTHERS); + if (enable) + val |= S3C64XX_OTHERS_USBMASK; + else + val &= ~S3C64XX_OTHERS_USBMASK; + + __raw_writel(val, S3C64XX_OTHERS); + local_irq_restore(flags); + + return 0; +} + +struct clk clk_48m = { + .name = "clk_48m", + .rate = 48000000, + .enable = clk_48m_ctrl, +}; + +struct clk clk_xusbxti = { + .name = "xusbxti", + .rate = 48000000, +}; + +static int inline s3c64xx_gate(void __iomem *reg, + struct clk *clk, + int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + u32 con; + + con = __raw_readl(reg); + + if (enable) + con |= ctrlbit; + else + con &= ~ctrlbit; + + __raw_writel(con, reg); + return 0; +} + +static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) +{ + return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); +} + +static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) +{ + return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); +} + +int s3c64xx_sclk_ctrl(struct clk *clk, int enable) +{ + return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); +} + +static struct clk init_clocks_off[] = { + { + .name = "nand", + .parent = &clk_h, + }, { + .name = "rtc", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_RTC, + }, { + .name = "adc", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_TSADC, + }, { + .name = "i2c", + .devname = "s3c2440-i2c.0", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_IIC, + }, { + .name = "i2c", + .devname = "s3c2440-i2c.1", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, + }, { + .name = "keypad", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, + }, { + .name = "spi", + .devname = "s3c6410-spi.0", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_SPI0, + }, { + .name = "spi", + .devname = "s3c6410-spi.1", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_SPI1, + }, { + .name = "48m", + .devname = "s3c-sdhci.0", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, + }, { + .name = "48m", + .devname = "s3c-sdhci.1", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, + }, { + .name = "48m", + .devname = "s3c-sdhci.2", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, + }, { + .name = "ac97", + .parent = &clk_p, + .ctrlbit = S3C_CLKCON_PCLK_AC97, + }, { + .name = "cfcon", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_IHOST, + }, { + .name = "dma0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_DMA0, + }, { + .name = "dma1", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_DMA1, + }, { + .name = "3dse", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_3DSE, + }, { + .name = "hclk_secur", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_SECUR, + }, { + .name = "sdma1", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_SDMA1, + }, { + .name = "sdma0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_SDMA0, + }, { + .name = "hclk_jpeg", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_JPEG, + }, { + .name = "camif", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_CAMIF, + }, { + .name = "hclk_scaler", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_SCALER, + }, { + .name = "2d", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_2D, + }, { + .name = "tv", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_TV, + }, { + .name = "post0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_POST0, + }, { + .name = "rot", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_ROT, + }, { + .name = "hclk_mfc", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_MFC, + }, { + .name = "pclk_mfc", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_MFC, + }, { + .name = "dac27", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_DAC27, + }, { + .name = "tv27", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_TV27, + }, { + .name = "scaler27", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SCALER27, + }, { + .name = "sclk_scaler", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SCALER, + }, { + .name = "post0_27", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_POST0_27, + }, { + .name = "secur", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SECUR, + }, { + .name = "sclk_mfc", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MFC, + }, { + .name = "sclk_jpeg", + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_JPEG, + }, +}; + +static struct clk clk_48m_spi0 = { + .name = "spi_48m", + .devname = "s3c6410-spi.0", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, +}; + +static struct clk clk_48m_spi1 = { + .name = "spi_48m", + .devname = "s3c6410-spi.1", + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, +}; + +static struct clk clk_i2s0 = { + .name = "iis", + .devname = "samsung-i2s.0", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_IIS0, +}; + +static struct clk clk_i2s1 = { + .name = "iis", + .devname = "samsung-i2s.1", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_IIS1, +}; + +#ifdef CONFIG_CPU_S3C6410 +static struct clk clk_i2s2 = { + .name = "iis", + .devname = "samsung-i2s.2", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, +}; +#endif + +static struct clk init_clocks[] = { + { + .name = "lcd", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_LCD, + }, { + .name = "gpio", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_GPIO, + }, { + .name = "usb-host", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_UHOST, + }, { + .name = "otg", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_USB, + }, { + .name = "timers", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_PWM, + }, { + .name = "uart", + .devname = "s3c6400-uart.0", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART0, + }, { + .name = "uart", + .devname = "s3c6400-uart.1", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART1, + }, { + .name = "uart", + .devname = "s3c6400-uart.2", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART2, + }, { + .name = "uart", + .devname = "s3c6400-uart.3", + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART3, + }, { + .name = "watchdog", + .parent = &clk_p, + .ctrlbit = S3C_CLKCON_PCLK_WDT, + }, +}; + +static struct clk clk_hsmmc0 = { + .name = "hsmmc", + .devname = "s3c-sdhci.0", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, +}; + +static struct clk clk_hsmmc1 = { + .name = "hsmmc", + .devname = "s3c-sdhci.1", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, +}; + +static struct clk clk_hsmmc2 = { + .name = "hsmmc", + .devname = "s3c-sdhci.2", + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, +}; + +static struct clk clk_fout_apll = { + .name = "fout_apll", +}; + +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; + +static struct clksrc_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; + +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, + .sources = &clk_src_apll, +}; + +static struct clk *clk_src_epll_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_fout_epll, +}; + +static struct clksrc_sources clk_src_epll = { + .sources = clk_src_epll_list, + .nr_sources = ARRAY_SIZE(clk_src_epll_list), +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, + .sources = &clk_src_epll, +}; + +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; + +static struct clksrc_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, + .sources = &clk_src_mpll, +}; + +static unsigned int armclk_mask; + +static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv; + + /* divisor mask starts at bit0, so no need to shift */ + clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; + + return rate / (clkdiv + 1); +} + +static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + + if (parent < rate) + return parent; + + div = (parent / rate) - 1; + if (div > armclk_mask) + div = armclk_mask; + + return parent / (div + 1); +} + +static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + u32 val; + + if (rate < parent / (armclk_mask + 1)) + return -EINVAL; + + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; + + val = __raw_readl(S3C_CLK_DIV0); + val &= ~armclk_mask; + val |= (div - 1); + __raw_writel(val, S3C_CLK_DIV0); + + return 0; + +} + +static struct clk clk_arm = { + .name = "armclk", + .parent = &clk_mout_apll.clk, + .ops = &(struct clk_ops) { + .get_rate = s3c64xx_clk_arm_get_rate, + .set_rate = s3c64xx_clk_arm_set_rate, + .round_rate = s3c64xx_clk_arm_round_rate, + }, +}; + +static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); + + if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) + rate /= 2; + + return rate; +} + +static struct clk_ops clk_dout_ops = { + .get_rate = s3c64xx_clk_doutmpll_get_rate, +}; + +static struct clk clk_dout_mpll = { + .name = "dout_mpll", + .parent = &clk_mout_mpll.clk, + .ops = &clk_dout_ops, +}; + +static struct clk *clkset_spi_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_27m, +}; + +static struct clksrc_sources clkset_spi_mmc = { + .sources = clkset_spi_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +}; + +static struct clk *clkset_irda_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + NULL, + &clk_27m, +}; + +static struct clksrc_sources clkset_irda = { + .sources = clkset_irda_list, + .nr_sources = ARRAY_SIZE(clkset_irda_list), +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + NULL, + NULL +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clk *clkset_uhost_list[] = { + &clk_48m, + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, +}; + +static struct clksrc_sources clkset_uhost = { + .sources = clkset_uhost_list, + .nr_sources = ARRAY_SIZE(clkset_uhost_list), +}; + +/* The peripheral clocks are all controlled via clocksource followed + * by an optional divider and gate stage. We currently roll this into + * one clock which hides the intermediate clock from the mux. + * + * Note, the JPEG clock can only be an even divider... + * + * The scaler and LCD clocks depend on the S3C64XX version, and also + * have a common parent divisor so are not included here. + */ + +/* clocks that feed other parts of the clock source tree */ + +static struct clk clk_iis_cd0 = { + .name = "iis_cdclk0", +}; + +static struct clk clk_iis_cd1 = { + .name = "iis_cdclk1", +}; + +static struct clk clk_iisv4_cd = { + .name = "iis_cdclk_v4", +}; + +static struct clk clk_pcm_cd = { + .name = "pcm_cdclk", +}; + +static struct clk *clkset_audio0_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iis_cd0, + [4] = &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio0 = { + .sources = clkset_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_audio0_list), +}; + +static struct clk *clkset_audio1_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iis_cd1, + [4] = &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio1 = { + .sources = clkset_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_audio1_list), +}; + +#ifdef CONFIG_CPU_S3C6410 +static struct clk *clkset_audio2_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iisv4_cd, + [4] = &clk_pcm_cd, +}; + +static struct clksrc_sources clkset_audio2 = { + .sources = clkset_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_audio2_list), +}; +#endif + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "usb-bus-host", + .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, + .sources = &clkset_uhost, + }, { + .clk = { + .name = "irda-bus", + .ctrlbit = S3C_CLKCON_SCLK_IRDA, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, + .sources = &clkset_irda, + }, { + .clk = { + .name = "camera", + .ctrlbit = S3C_CLKCON_SCLK_CAM, + .enable = s3c64xx_sclk_ctrl, + .parent = &clk_h2, + }, + .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, + }, +}; + +/* Where does UCLK0 come from? */ +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name = "uclk1", + .ctrlbit = S3C_CLKCON_SCLK_UART, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, + .sources = &clkset_uart, +}; + +static struct clksrc_clk clk_sclk_mmc0 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.0", + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc1 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.1", + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_mmc2 = { + .clk = { + .name = "mmc_bus", + .devname = "s3c-sdhci.2", + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_spi0 = { + .clk = { + .name = "spi-bus", + .devname = "s3c6410-spi.0", + .ctrlbit = S3C_CLKCON_SCLK_SPI0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_sclk_spi1 = { + .clk = { + .name = "spi-bus", + .devname = "s3c6410-spi.1", + .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, +}; + +static struct clksrc_clk clk_audio_bus0 = { + .clk = { + .name = "audio-bus", + .devname = "samsung-i2s.0", + .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, + .sources = &clkset_audio0, +}; + +static struct clksrc_clk clk_audio_bus1 = { + .clk = { + .name = "audio-bus", + .devname = "samsung-i2s.1", + .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, + .sources = &clkset_audio1, +}; + +#ifdef CONFIG_CPU_S3C6410 +static struct clksrc_clk clk_audio_bus2 = { + .clk = { + .name = "audio-bus", + .devname = "samsung-i2s.2", + .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 }, + .sources = &clkset_audio2, +}; +#endif +/* Clock initialisation code */ + +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_epll, + &clk_mout_mpll, +}; + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, + &clk_sclk_mmc0, + &clk_sclk_mmc1, + &clk_sclk_mmc2, + &clk_sclk_spi0, + &clk_sclk_spi1, + &clk_audio_bus0, + &clk_audio_bus1, +}; + +static struct clk *clk_cdev[] = { + &clk_hsmmc0, + &clk_hsmmc1, + &clk_hsmmc2, + &clk_48m_spi0, + &clk_48m_spi1, + &clk_i2s0, + &clk_i2s1, +}; + +static struct clk_lookup s3c64xx_clk_lookup[] = { + CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), + CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), + CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), + CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), + CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0), + CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1), + CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), + CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk), + CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1), + CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk), +#ifdef CONFIG_CPU_S3C6410 + CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2), + CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk), +#endif +}; + +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) + +void __init_or_cpufreq s3c64xx_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long hclk2; + unsigned long pclk; + unsigned long epll; + unsigned long apll; + unsigned long mpll; + unsigned int ptr; + u32 clkdiv0; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + clkdiv0 = __raw_readl(S3C_CLK_DIV0); + printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + /* For now assume the mux always selects the crystal */ + clk_ext_xtal_mux.parent = xtal_clk; + + epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0), + __raw_readl(S3C_EPLL_CON1)); + mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); + apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); + + fclk = mpll; + + printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", + apll, mpll, epll); + + if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL) + /* Synchronous mode */ + hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + else + /* Asynchronous mode */ + hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + + hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); + pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); + + printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", + hclk2, hclk, pclk); + + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + + clk_h2.rate = hclk2; + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_f.rate = fclk; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); +} + +static struct clk *clks1[] __initdata = { + &clk_ext_xtal_mux, + &clk_iis_cd0, + &clk_iis_cd1, + &clk_iisv4_cd, + &clk_pcm_cd, + &clk_mout_epll.clk, + &clk_mout_mpll.clk, + &clk_dout_mpll, + &clk_arm, +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_27m, + &clk_48m, + &clk_h2, + &clk_xusbxti, +}; + +/** + * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410 + * @xtal: The rate for the clock crystal feeding the PLLs. + * @armclk_divlimit: Divisor mask for ARMCLK. + * + * Register the clocks for the S3C6400 and S3C6410 SoC range, such + * as ARMCLK as well as the necessary parent clocks. + * + * This call does not setup the clocks, which is left to the + * s3c64xx_setup_clocks() call which may be needed by the cpufreq + * or resume code to re-set the clocks if the bootloader has changed + * them. + */ +void __init s3c64xx_register_clocks(unsigned long xtal, + unsigned armclk_divlimit) +{ + unsigned int cnt; + + armclk_mask = armclk_divlimit; + + s3c24xx_register_baseclocks(xtal); + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) + s3c_disable_clocks(clk_cdev[cnt], 1); + + s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) + s3c_register_clksrc(clksrc_cdev[cnt], 1); + clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup)); +} diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 7a3ce4c..73d79cf 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -14,14 +14,9 @@ * published by the Free Software Foundation. */ -/* - * NOTE: Code in this file is not used when booting with Device Tree support. - */ - #include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> -#include <linux/clk-provider.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h> @@ -43,6 +38,7 @@ #include <mach/regs-gpio.h> #include <plat/cpu.h> +#include <plat/clock.h> #include <plat/devs.h> #include <plat/pm.h> #include <plat/gpio-cfg.h> @@ -54,19 +50,6 @@ #include "common.h" -/* External clock frequency */ -static unsigned long xtal_f = 12000000, xusbxti_f = 48000000; - -void __init s3c64xx_set_xtal_freq(unsigned long freq) -{ - xtal_f = freq; -} - -void __init s3c64xx_set_xusbxti_freq(unsigned long freq) -{ - xusbxti_f = freq; -} - /* uart registration process */ static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) @@ -84,6 +67,7 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = S3C6400_CPU_ID, .idmask = S3C64XX_CPU_MASK, .map_io = s3c6400_map_io, + .init_clocks = s3c6400_init_clocks, .init_uarts = s3c64xx_init_uarts, .init = s3c6400_init, .name = name_s3c6400, @@ -91,6 +75,7 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = S3C6410_CPU_ID, .idmask = S3C64XX_CPU_MASK, .map_io = s3c6410_map_io, + .init_clocks = s3c6410_init_clocks, .init_uarts = s3c64xx_init_uarts, .init = s3c6410_init, .name = name_s3c6410, @@ -207,10 +192,6 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) static __init int s3c64xx_dev_init(void) { - /* Not applicable when using DT. */ - if (of_have_populated_dt()) - return 0; - subsys_system_register(&s3c64xx_subsys, NULL); return device_register(&s3c64xx_dev); } @@ -232,10 +213,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { /* * FIXME: there is no better place to put this at the moment - * (s3c64xx_clk_init needs ioremap and must happen before init_time - * samsung_wdt_reset_init needs clocks) + * (samsung_wdt_reset_init needs clocks) */ - s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS); samsung_wdt_reset_init(S3C_VA_WATCHDOG); printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); @@ -412,10 +391,6 @@ static int __init s3c64xx_init_irq_eint(void) { int irq; - /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */ - if (of_have_populated_dt()) - return -ENODEV; - for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h index bd3bd56..e8f990b 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c64xx/common.h @@ -22,21 +22,21 @@ void s3c64xx_init_irq(u32 vic0, u32 vic1); void s3c64xx_init_io(struct map_desc *mach_desc, int size); +void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit); +void s3c64xx_setup_clocks(void); + void s3c64xx_restart(enum reboot_mode mode, const char *cmd); void s3c64xx_init_late(void); -void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, - unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base); -void s3c64xx_set_xtal_freq(unsigned long freq); -void s3c64xx_set_xusbxti_freq(unsigned long freq); - #ifdef CONFIG_CPU_S3C6400 extern int s3c6400_init(void); extern void s3c6400_init_irq(void); extern void s3c6400_map_io(void); +extern void s3c6400_init_clocks(int xtal); #else +#define s3c6400_init_clocks NULL #define s3c6400_map_io NULL #define s3c6400_init NULL #endif @@ -46,8 +46,10 @@ extern void s3c6400_map_io(void); extern int s3c6410_init(void); extern void s3c6410_init_irq(void); extern void s3c6410_map_io(void); +extern void s3c6410_init_clocks(int xtal); #else +#define s3c6410_init_clocks NULL #define s3c6410_map_io NULL #define s3c6410_init NULL #endif diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 7e22c21..759846c 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -12,10 +12,6 @@ * published by the Free Software Foundation. */ -/* - * NOTE: Code in this file is not used when booting with Device Tree support. - */ - #include <linux/kernel.h> #include <linux/module.h> #include <linux/interrupt.h> @@ -28,7 +24,6 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/amba/pl080.h> -#include <linux/of.h> #include <mach/dma.h> #include <mach/map.h> @@ -682,7 +677,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, goto err_map; } - clk_prepare_enable(dmac->clk); + clk_enable(dmac->clk); dmac->regs = regs; dmac->chanbase = chbase; @@ -716,7 +711,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, return 0; err_clk: - clk_disable_unprepare(dmac->clk); + clk_disable(dmac->clk); clk_put(dmac->clk); err_map: iounmap(regs); @@ -731,10 +726,6 @@ static int __init s3c64xx_dma_init(void) { int ret; - /* This driver is not supported when booting with device tree. */ - if (of_have_populated_dt()) - return -ENODEV; - printk(KERN_INFO "%s: Registering DMA channels\n", __func__); dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0); diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 4f44aac..05332b9 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -15,21 +15,145 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -/* - * FIXME: Remove remaining definitions - */ - #define S3C_CLKREG(x) (S3C_VA_SYS + (x)) +#define S3C_APLL_LOCK S3C_CLKREG(0x00) +#define S3C_MPLL_LOCK S3C_CLKREG(0x04) +#define S3C_EPLL_LOCK S3C_CLKREG(0x08) +#define S3C_APLL_CON S3C_CLKREG(0x0C) +#define S3C_MPLL_CON S3C_CLKREG(0x10) +#define S3C_EPLL_CON0 S3C_CLKREG(0x14) +#define S3C_EPLL_CON1 S3C_CLKREG(0x18) +#define S3C_CLK_SRC S3C_CLKREG(0x1C) +#define S3C_CLK_DIV0 S3C_CLKREG(0x20) +#define S3C_CLK_DIV1 S3C_CLKREG(0x24) +#define S3C_CLK_DIV2 S3C_CLKREG(0x28) +#define S3C_CLK_OUT S3C_CLKREG(0x2C) +#define S3C_HCLK_GATE S3C_CLKREG(0x30) #define S3C_PCLK_GATE S3C_CLKREG(0x34) +#define S3C_SCLK_GATE S3C_CLKREG(0x38) +#define S3C_MEM0_GATE S3C_CLKREG(0x3C) #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) +/* CLKDIV0 */ +#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) +#define S3C6400_CLKDIV0_PCLK_SHIFT (12) +#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) +#define S3C6400_CLKDIV0_HCLK2_SHIFT (9) +#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) +#define S3C6400_CLKDIV0_HCLK_SHIFT (8) +#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) +#define S3C6400_CLKDIV0_MPLL_SHIFT (4) + +#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) +#define S3C6400_CLKDIV0_ARM_SHIFT (0) + +/* HCLK GATE Registers */ +#define S3C_CLKCON_HCLK_3DSE (1<<31) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) +#define S3C_CLKCON_HCLK_IROM (1<<25) +#define S3C_CLKCON_HCLK_DDR1 (1<<24) +#define S3C_CLKCON_HCLK_DDR0 (1<<23) +#define S3C_CLKCON_HCLK_MEM1 (1<<22) +#define S3C_CLKCON_HCLK_MEM0 (1<<21) +#define S3C_CLKCON_HCLK_USB (1<<20) +#define S3C_CLKCON_HCLK_HSMMC2 (1<<19) +#define S3C_CLKCON_HCLK_HSMMC1 (1<<18) +#define S3C_CLKCON_HCLK_HSMMC0 (1<<17) +#define S3C_CLKCON_HCLK_MDP (1<<16) +#define S3C_CLKCON_HCLK_DHOST (1<<15) +#define S3C_CLKCON_HCLK_IHOST (1<<14) +#define S3C_CLKCON_HCLK_DMA1 (1<<13) +#define S3C_CLKCON_HCLK_DMA0 (1<<12) +#define S3C_CLKCON_HCLK_JPEG (1<<11) +#define S3C_CLKCON_HCLK_CAMIF (1<<10) +#define S3C_CLKCON_HCLK_SCALER (1<<9) +#define S3C_CLKCON_HCLK_2D (1<<8) +#define S3C_CLKCON_HCLK_TV (1<<7) +#define S3C_CLKCON_HCLK_POST0 (1<<5) +#define S3C_CLKCON_HCLK_ROT (1<<4) +#define S3C_CLKCON_HCLK_LCD (1<<3) +#define S3C_CLKCON_HCLK_TZIC (1<<2) +#define S3C_CLKCON_HCLK_INTC (1<<1) +#define S3C_CLKCON_HCLK_MFC (1<<0) + /* PCLK GATE Registers */ +#define S3C6410_CLKCON_PCLK_I2C1 (1<<27) +#define S3C6410_CLKCON_PCLK_IIS2 (1<<26) +#define S3C_CLKCON_PCLK_SKEY (1<<24) +#define S3C_CLKCON_PCLK_CHIPID (1<<23) +#define S3C_CLKCON_PCLK_SPI1 (1<<22) +#define S3C_CLKCON_PCLK_SPI0 (1<<21) +#define S3C_CLKCON_PCLK_HSIRX (1<<20) +#define S3C_CLKCON_PCLK_HSITX (1<<19) +#define S3C_CLKCON_PCLK_GPIO (1<<18) +#define S3C_CLKCON_PCLK_IIC (1<<17) +#define S3C_CLKCON_PCLK_IIS1 (1<<16) +#define S3C_CLKCON_PCLK_IIS0 (1<<15) +#define S3C_CLKCON_PCLK_AC97 (1<<14) +#define S3C_CLKCON_PCLK_TZPC (1<<13) +#define S3C_CLKCON_PCLK_TSADC (1<<12) +#define S3C_CLKCON_PCLK_KEYPAD (1<<11) +#define S3C_CLKCON_PCLK_IRDA (1<<10) +#define S3C_CLKCON_PCLK_PCM1 (1<<9) +#define S3C_CLKCON_PCLK_PCM0 (1<<8) +#define S3C_CLKCON_PCLK_PWM (1<<7) +#define S3C_CLKCON_PCLK_RTC (1<<6) +#define S3C_CLKCON_PCLK_WDT (1<<5) #define S3C_CLKCON_PCLK_UART3 (1<<4) #define S3C_CLKCON_PCLK_UART2 (1<<3) #define S3C_CLKCON_PCLK_UART1 (1<<2) #define S3C_CLKCON_PCLK_UART0 (1<<1) +#define S3C_CLKCON_PCLK_MFC (1<<0) + +/* SCLK GATE Registers */ +#define S3C_CLKCON_SCLK_UHOST (1<<30) +#define S3C_CLKCON_SCLK_MMC2_48 (1<<29) +#define S3C_CLKCON_SCLK_MMC1_48 (1<<28) +#define S3C_CLKCON_SCLK_MMC0_48 (1<<27) +#define S3C_CLKCON_SCLK_MMC2 (1<<26) +#define S3C_CLKCON_SCLK_MMC1 (1<<25) +#define S3C_CLKCON_SCLK_MMC0 (1<<24) +#define S3C_CLKCON_SCLK_SPI1_48 (1<<23) +#define S3C_CLKCON_SCLK_SPI0_48 (1<<22) +#define S3C_CLKCON_SCLK_SPI1 (1<<21) +#define S3C_CLKCON_SCLK_SPI0 (1<<20) +#define S3C_CLKCON_SCLK_DAC27 (1<<19) +#define S3C_CLKCON_SCLK_TV27 (1<<18) +#define S3C_CLKCON_SCLK_SCALER27 (1<<17) +#define S3C_CLKCON_SCLK_SCALER (1<<16) +#define S3C_CLKCON_SCLK_LCD27 (1<<15) +#define S3C_CLKCON_SCLK_LCD (1<<14) +#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) +#define S3C6410_CLKCON_FIMC (1<<13) +#define S3C_CLKCON_SCLK_POST0_27 (1<<12) +#define S3C6400_CLKCON_SCLK_POST1 (1<<11) +#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) +#define S3C_CLKCON_SCLK_POST0 (1<<10) +#define S3C_CLKCON_SCLK_AUDIO1 (1<<9) +#define S3C_CLKCON_SCLK_AUDIO0 (1<<8) +#define S3C_CLKCON_SCLK_SECUR (1<<7) +#define S3C_CLKCON_SCLK_IRDA (1<<6) +#define S3C_CLKCON_SCLK_UART (1<<5) +#define S3C_CLKCON_SCLK_ONENAND (1<<4) +#define S3C_CLKCON_SCLK_MFC (1<<3) +#define S3C_CLKCON_SCLK_CAM (1<<2) +#define S3C_CLKCON_SCLK_JPEG (1<<1) + +/* CLKSRC */ + +#define S3C6400_CLKSRC_APLL_MOUT (1 << 0) +#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) +#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) +#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) +#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) +#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) +#define S3C6400_CLKSRC_MFC (1 << 4) /* MEM_SYS_CFG */ #define MEM_SYS_CFG_INDEP_CF 0x4000 diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c index 1649c0d..c3da1b6 100644 --- a/arch/arm/mach-s3c64xx/irq-pm.c +++ b/arch/arm/mach-s3c64xx/irq-pm.c @@ -12,17 +12,12 @@ * published by the Free Software Foundation. */ -/* - * NOTE: Code in this file is not used when booting with Device Tree support. - */ - #include <linux/kernel.h> #include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/serial_core.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/of.h> #include <mach/map.h> @@ -106,10 +101,6 @@ static struct syscore_ops s3c64xx_irq_syscore_ops = { static __init int s3c64xx_syscore_init(void) { - /* Appropriate drivers (pinctrl, uart) handle this when using DT. */ - if (of_have_populated_dt()) - return 0; - register_syscore_ops(&s3c64xx_irq_syscore_ops); return 0; diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index d266dd5..35e3f54 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = { static void __init anw6410_map_io(void) { s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index 758e31b..eb8e5a1 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -114,7 +114,6 @@ static struct platform_pwm_backlight_data crag6410_backlight_data = { .max_brightness = 1000, .dft_brightness = 600, .pwm_period_ns = 100000, /* about 1kHz */ - .enable_gpio = -1, }; static struct platform_device crag6410_backlight_device = { @@ -311,6 +310,10 @@ static struct regulator_consumer_supply wallvdd_consumers[] = { REGULATOR_SUPPLY("SPKVDDL", "spi0.1"), REGULATOR_SUPPLY("SPKVDDR", "spi0.1"), + REGULATOR_SUPPLY("SPKVDDL", "wm5102-codec"), + REGULATOR_SUPPLY("SPKVDDR", "wm5102-codec"), + REGULATOR_SUPPLY("SPKVDDL", "wm5110-codec"), + REGULATOR_SUPPLY("SPKVDDR", "wm5110-codec"), REGULATOR_SUPPLY("DC1VDD", "0-0034"), REGULATOR_SUPPLY("DC2VDD", "0-0034"), @@ -650,6 +653,14 @@ static struct regulator_consumer_supply pvdd_1v8_consumers[] = { REGULATOR_SUPPLY("DBVDD3", "spi0.1"), REGULATOR_SUPPLY("LDOVDD", "spi0.1"), REGULATOR_SUPPLY("CPVDD", "spi0.1"), + + REGULATOR_SUPPLY("DBVDD2", "wm5102-codec"), + REGULATOR_SUPPLY("DBVDD3", "wm5102-codec"), + REGULATOR_SUPPLY("CPVDD", "wm5102-codec"), + + REGULATOR_SUPPLY("DBVDD2", "wm5110-codec"), + REGULATOR_SUPPLY("DBVDD3", "wm5110-codec"), + REGULATOR_SUPPLY("CPVDD", "wm5110-codec"), }; static struct regulator_init_data pvdd_1v8 = { @@ -732,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = { static void __init crag6410_map_io(void) { s3c64xx_init_io(NULL, 0); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 614a03a..f39569e 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -114,7 +114,6 @@ static struct platform_pwm_backlight_data hmt_backlight_data = { .max_brightness = 100 * 256, .dft_brightness = 40 * 256, .pwm_period_ns = 1000000000 / (100 * 256 * 20), - .enable_gpio = -1, .init = hmt_bl_init, .notify = hmt_bl_notify, .exit = hmt_bl_exit, @@ -248,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = { static void __init hmt_map_io(void) { s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index 58d46a3..fc043e3 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -231,7 +231,7 @@ static void __init mini6410_map_io(void) u32 tmp; s3c64xx_init_io(NULL, 0); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index 2067b0b..7e2c390 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c @@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {}; static void __init ncp_map_io(void) { s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc)); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c deleted file mode 100644 index 7eb9a10..0000000 --- a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Samsung's S3C64XX flattened device tree enabled machine - * - * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/clk-provider.h> -#include <linux/irqchip.h> -#include <linux/of_platform.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/system_misc.h> - -#include <plat/cpu.h> -#include <plat/watchdog-reset.h> - -#include <mach/map.h> - -#include "common.h" - -/* - * IO mapping for shared system controller IP. - * - * FIXME: Make remaining drivers use dynamic mapping. - */ -static struct map_desc s3c64xx_dt_iodesc[] __initdata = { - { - .virtual = (unsigned long)S3C_VA_SYS, - .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void __init s3c64xx_dt_map_io(void) -{ - debug_ll_io_init(); - iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc)); - - s3c64xx_init_cpu(); - - if (!soc_is_s3c64xx()) - panic("SoC is not S3C64xx!"); -} - -static void __init s3c64xx_dt_init_irq(void) -{ - of_clk_init(NULL); - samsung_wdt_reset_of_init(); - irqchip_init(); -}; - -static void __init s3c64xx_dt_init_machine(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd) -{ - if (mode != REBOOT_SOFT) - samsung_wdt_reset(); - - /* if all else fails, or mode was for soft, jump to 0 */ - soft_restart(0); -} - -static char const *s3c64xx_dt_compat[] __initdata = { - "samsung,s3c6400", - "samsung,s3c6410", - NULL -}; - -DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)") - /* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */ - .dt_compat = s3c64xx_dt_compat, - .map_io = s3c64xx_dt_map_io, - .init_irq = s3c64xx_dt_init_irq, - .init_machine = s3c64xx_dt_init_machine, - .restart = s3c64xx_dt_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index a6b338f..86d980b 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -151,7 +151,6 @@ static struct platform_pwm_backlight_data smartq_backlight_data = { .max_brightness = 1000, .dft_brightness = 600, .pwm_period_ns = 1000000000 / (1000 * 20), - .enable_gpio = -1, .init = smartq_bl_init, }; @@ -338,6 +337,13 @@ err: return ret; } +static int __init smartq_usb_otg_init(void) +{ + clk_xusbxti.rate = 12000000; + + return 0; +} + static int __init smartq_wifi_init(void) { int ret; @@ -371,8 +377,7 @@ static struct map_desc smartq_iodesc[] __initdata = {}; void __init smartq_map_io(void) { s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); - s3c64xx_set_xtal_freq(12000000); - s3c64xx_set_xusbxti_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); @@ -394,6 +399,7 @@ void __init smartq_machine_init(void) WARN_ON(smartq_lcd_setup_gpio()); WARN_ON(smartq_power_off_init()); WARN_ON(smartq_usb_host_init()); + WARN_ON(smartq_usb_otg_init()); WARN_ON(smartq_wifi_init()); platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index 27381cf..d70c084 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c @@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {}; static void __init smdk6400_map_io(void) { s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d5ea938..d90b450 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -625,7 +625,6 @@ static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = { static struct platform_pwm_backlight_data smdk6410_bl_data = { .pwm_id = 1, - .enable_gpio = -1, }; static struct s3c_hsotg_plat smdk6410_hsotg_pdata; @@ -635,7 +634,7 @@ static void __init smdk6410_map_io(void) u32 tmp; s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); - s3c64xx_set_xtal_freq(12000000); + s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index 8cdb824..6a1f91f 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -194,8 +194,29 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear) #endif static struct sleep_save core_save[] = { + SAVE_ITEM(S3C_APLL_LOCK), + SAVE_ITEM(S3C_MPLL_LOCK), + SAVE_ITEM(S3C_EPLL_LOCK), + SAVE_ITEM(S3C_CLK_SRC), + SAVE_ITEM(S3C_CLK_DIV0), + SAVE_ITEM(S3C_CLK_DIV1), + SAVE_ITEM(S3C_CLK_DIV2), + SAVE_ITEM(S3C_CLK_OUT), + SAVE_ITEM(S3C_HCLK_GATE), + SAVE_ITEM(S3C_PCLK_GATE), + SAVE_ITEM(S3C_SCLK_GATE), + SAVE_ITEM(S3C_MEM0_GATE), + + SAVE_ITEM(S3C_EPLL_CON1), + SAVE_ITEM(S3C_EPLL_CON0), + SAVE_ITEM(S3C64XX_MEM0DRVCON), SAVE_ITEM(S3C64XX_MEM1DRVCON), + +#ifndef CONFIG_CPU_FREQ + SAVE_ITEM(S3C_APLL_CON), + SAVE_ITEM(S3C_MPLL_CON), +#endif }; static struct sleep_save misc_save[] = { diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 3db0c98..4869714 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -9,10 +9,6 @@ * published by the Free Software Foundation. */ -/* - * NOTE: Code in this file is not used when booting with Device Tree support. - */ - #include <linux/kernel.h> #include <linux/types.h> #include <linux/interrupt.h> @@ -24,7 +20,6 @@ #include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> -#include <linux/of.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -63,6 +58,12 @@ void __init s3c6400_map_io(void) s3c64xx_onenand1_setname("s3c6400-onenand"); } +void __init s3c6400_init_clocks(int xtal) +{ + s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK); + s3c64xx_setup_clocks(); +} + void __init s3c6400_init_irq(void) { /* VIC0 does not have IRQS 5..7, @@ -81,10 +82,6 @@ static struct device s3c6400_dev = { static int __init s3c6400_core_init(void) { - /* Not applicable when using DT. */ - if (of_have_populated_dt()) - return 0; - return subsys_system_register(&s3c6400_subsys, NULL); } diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 72b2278..31c29fd 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -10,10 +10,6 @@ * published by the Free Software Foundation. */ -/* - * NOTE: Code in this file is not used when booting with Device Tree support. - */ - #include <linux/kernel.h> #include <linux/types.h> #include <linux/interrupt.h> @@ -25,7 +21,6 @@ #include <linux/device.h> #include <linux/serial_core.h> #include <linux/platform_device.h> -#include <linux/of.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -67,6 +62,13 @@ void __init s3c6410_map_io(void) s3c_cfcon_setname("s3c64xx-pata"); } +void __init s3c6410_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initialising clocks\n", __func__); + s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK); + s3c64xx_setup_clocks(); +} + void __init s3c6410_init_irq(void) { /* VIC0 is missing IRQ7, VIC1 is fully populated. */ @@ -84,10 +86,6 @@ static struct device s3c6410_dev = { static int __init s3c6410_core_init(void) { - /* Not applicable when using DT. */ - if (of_have_populated_dt()) - return 0; - return subsys_system_register(&s3c6410_subsys, NULL); } diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 9efdcc0..0b00304 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -223,7 +223,6 @@ static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = { static struct platform_pwm_backlight_data smdk6440_bl_data = { .pwm_id = 1, - .enable_gpio = -1, }; static void __init smdk6440_map_io(void) diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index c3cacc0..5949296 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -242,7 +242,6 @@ static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = { static struct platform_pwm_backlight_data smdk6450_bl_data = { .pwm_id = 1, - .enable_gpio = -1, }; static void __init smdk6450_map_io(void) diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 9e256b9..7c57a22 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -216,7 +216,6 @@ static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = { static struct platform_pwm_backlight_data smdkc100_bl_data = { .pwm_id = 0, - .enable_gpio = -1, }; static void __init smdkc100_map_io(void) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index e345584..032de66 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -147,6 +147,10 @@ #define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) #define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) +#define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) +#define S5P_MIPI_DPHY_ENABLE (1 << 0) +#define S5P_MIPI_DPHY_SRESETN (1 << 1) +#define S5P_MIPI_DPHY_MRESETN (1 << 2) #define S5P_INFORM0 S5P_CLKREG(0xF000) #define S5P_INFORM1 S5P_CLKREG(0xF004) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index f52cc15..6d72bb99 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -279,7 +279,6 @@ static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = { static struct platform_pwm_backlight_data smdkv210_bl_data = { .pwm_id = 3, .pwm_period_ns = 1000, - .enable_gpio = -1, }; static void __init smdkv210_map_io(void) diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index c9808c6..e838ba2 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -512,9 +512,6 @@ static void __init assabet_map_io(void) * Its called GPCLKR0 in my SA1110 manual. */ Ser1SDCR0 |= SDCR0_SUS; - MSC1 = (MSC1 & ~0xffff) | - MSC_NonBrst | MSC_32BitStMem | - MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0); if (!machine_has_neponset()) sa1100_register_uart_fns(&assabet_port_fns); diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index d4ea142..f25b611 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -42,31 +42,74 @@ EXPORT_SYMBOL(reset_status); /* * This table is setup for a 3.6864MHz Crystal. */ -struct cpufreq_frequency_table sa11x0_freq_table[NR_FREQS+1] = { - { .frequency = 59000, /* 59.0 MHz */}, - { .frequency = 73700, /* 73.7 MHz */}, - { .frequency = 88500, /* 88.5 MHz */}, - { .frequency = 103200, /* 103.2 MHz */}, - { .frequency = 118000, /* 118.0 MHz */}, - { .frequency = 132700, /* 132.7 MHz */}, - { .frequency = 147500, /* 147.5 MHz */}, - { .frequency = 162200, /* 162.2 MHz */}, - { .frequency = 176900, /* 176.9 MHz */}, - { .frequency = 191700, /* 191.7 MHz */}, - { .frequency = 206400, /* 206.4 MHz */}, - { .frequency = 221200, /* 221.2 MHz */}, - { .frequency = 235900, /* 235.9 MHz */}, - { .frequency = 250700, /* 250.7 MHz */}, - { .frequency = 265400, /* 265.4 MHz */}, - { .frequency = 280200, /* 280.2 MHz */}, - { .frequency = CPUFREQ_TABLE_END, }, +static const unsigned short cclk_frequency_100khz[NR_FREQS] = { + 590, /* 59.0 MHz */ + 737, /* 73.7 MHz */ + 885, /* 88.5 MHz */ + 1032, /* 103.2 MHz */ + 1180, /* 118.0 MHz */ + 1327, /* 132.7 MHz */ + 1475, /* 147.5 MHz */ + 1622, /* 162.2 MHz */ + 1769, /* 176.9 MHz */ + 1917, /* 191.7 MHz */ + 2064, /* 206.4 MHz */ + 2212, /* 221.2 MHz */ + 2359, /* 235.9 MHz */ + 2507, /* 250.7 MHz */ + 2654, /* 265.4 MHz */ + 2802 /* 280.2 MHz */ }; +/* rounds up(!) */ +unsigned int sa11x0_freq_to_ppcr(unsigned int khz) +{ + int i; + + khz /= 100; + + for (i = 0; i < NR_FREQS; i++) + if (cclk_frequency_100khz[i] >= khz) + break; + + return i; +} + +unsigned int sa11x0_ppcr_to_freq(unsigned int idx) +{ + unsigned int freq = 0; + if (idx < NR_FREQS) + freq = cclk_frequency_100khz[idx] * 100; + return freq; +} + + +/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on + * this platform, anyway. + */ +int sa11x0_verify_speed(struct cpufreq_policy *policy) +{ + unsigned int tmp; + if (policy->cpu) + return -EINVAL; + + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); + + /* make sure that at least one frequency is within the policy */ + tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100; + if (tmp > policy->max) + policy->max = tmp; + + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); + + return 0; +} + unsigned int sa11x0_getspeed(unsigned int cpu) { if (cpu) return 0; - return sa11x0_freq_table[PPCR & 0xf].frequency; + return cclk_frequency_100khz[PPCR & 0xf] * 100; } /* diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index 0d92e11..9a33695 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h @@ -3,7 +3,6 @@ * * Author: Nicolas Pitre */ -#include <linux/cpufreq.h> #include <linux/reboot.h> extern void sa1100_timer_init(void); @@ -20,8 +19,12 @@ extern void sa11x0_init_late(void); extern void sa1110_mb_enable(void); extern void sa1110_mb_disable(void); -extern struct cpufreq_frequency_table sa11x0_freq_table[]; +struct cpufreq_policy; + +extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz); +extern int sa11x0_verify_speed(struct cpufreq_policy *policy); extern unsigned int sa11x0_getspeed(unsigned int cpu); +extern unsigned int sa11x0_ppcr_to_freq(unsigned int idx); struct flash_platform_data; struct resource; diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h new file mode 100644 index 0000000..6a9eecf --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/gpio.h @@ -0,0 +1,55 @@ +/* + * arch/arm/mach-sa1100/include/mach/gpio.h + * + * SA1100 GPIO wrappers for arch-neutral GPIO calls + * + * Written by Philipp Zabel <philipp.zabel@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_SA1100_GPIO_H +#define __ASM_ARCH_SA1100_GPIO_H + +#include <linux/io.h> +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm-generic/gpio.h> + +#define __ARM_GPIOLIB_COMPLEX + +static inline int gpio_get_value(unsigned gpio) +{ + if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) + return GPLR & GPIO_GPIO(gpio); + else + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) + if (value) + GPSR = GPIO_GPIO(gpio); + else + GPCR = GPIO_GPIO(gpio); + else + __gpio_set_value(gpio, value); +} + +#define gpio_cansleep __gpio_cansleep + +#endif diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h index c810620..7d9df16 100644 --- a/arch/arm/mach-sa1100/include/mach/h3xxx.h +++ b/arch/arm/mach-sa1100/include/mach/h3xxx.h @@ -13,8 +13,6 @@ #ifndef _INCLUDE_H3XXX_H_ #define _INCLUDE_H3XXX_H_ -#include "hardware.h" /* Gives GPIO_MAX */ - /* Physical memory regions corresponding to chip selects */ #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) #define H3600_BANK_2_PHYS SA1100_CS2_PHYS diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 41e476e..bcbc945 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -19,7 +19,6 @@ #include <mach/hardware.h> #include <asm/setup.h> -#include <asm/irq.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-shark/Makefile b/arch/arm/mach-shark/Makefile new file mode 100644 index 0000000..2965718 --- /dev/null +++ b/arch/arm/mach-shark/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := core.o dma.o irq.o pci.o leds.o +obj-m := +obj-n := +obj- := diff --git a/arch/arm/mach-shark/Makefile.boot b/arch/arm/mach-shark/Makefile.boot new file mode 100644 index 0000000..e40e24e --- /dev/null +++ b/arch/arm/mach-shark/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y += 0x08008000 + diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c new file mode 100644 index 0000000..1d32c5e --- /dev/null +++ b/arch/arm/mach-shark/core.c @@ -0,0 +1,146 @@ +/* + * linux/arch/arm/mach-shark/arch.c + * + * Architecture specific stuff. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/sched.h> +#include <linux/serial_8250.h> +#include <linux/io.h> +#include <linux/cpu.h> +#include <linux/reboot.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/param.h> +#include <asm/system_misc.h> + +#include <asm/mach/map.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#define ROMCARD_SIZE 0x08000000 +#define ROMCARD_START 0x10000000 + +static void shark_restart(enum reboot_mode mode, const char *cmd) +{ + short temp; + /* Reset the Machine via pc[3] of the sequoia chipset */ + outw(0x09,0x24); + temp=inw(0x26); + temp = temp | (1<<3) | (1<<10); + outw(0x09,0x24); + outw(temp,0x26); +} + +static struct plat_serial8250_port serial_platform_data[] = { + { + .iobase = 0x3f8, + .irq = 4, + .uartclk = 1843200, + .regshift = 0, + .iotype = UPIO_PORT, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, + { + .iobase = 0x2f8, + .irq = 3, + .uartclk = 1843200, + .regshift = 0, + .iotype = UPIO_PORT, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + }, + { }, +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, +}; + +static struct resource rtc_resources[] = { + [0] = { + .start = 0x70, + .end = 0x73, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = IRQ_ISA_RTC_ALARM, + .end = IRQ_ISA_RTC_ALARM, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device rtc_device = { + .name = "rtc_cmos", + .id = -1, + .resource = rtc_resources, + .num_resources = ARRAY_SIZE(rtc_resources), +}; + +static int __init shark_init(void) +{ + int ret; + + if (machine_is_shark()) + { + ret = platform_device_register(&rtc_device); + if (ret) printk(KERN_ERR "Unable to register RTC device: %d\n", ret); + ret = platform_device_register(&serial_device); + if (ret) printk(KERN_ERR "Unable to register Serial device: %d\n", ret); + } + return 0; +} + +arch_initcall(shark_init); + +extern void shark_init_irq(void); + +#define IRQ_TIMER 0 +#define HZ_TIME ((1193180 + HZ/2) / HZ) + +static irqreturn_t +shark_timer_interrupt(int irq, void *dev_id) +{ + timer_tick(); + return IRQ_HANDLED; +} + +static struct irqaction shark_timer_irq = { + .name = "Shark Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = shark_timer_interrupt, +}; + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +static void __init shark_timer_init(void) +{ + outb(0x34, 0x43); /* binary, mode 0, LSB/MSB, Ch 0 */ + outb(HZ_TIME & 0xff, 0x40); /* LSB of count */ + outb(HZ_TIME >> 8, 0x40); + + setup_irq(IRQ_TIMER, &shark_timer_irq); +} + +static void shark_init_early(void) +{ + cpu_idle_poll_ctrl(true); +} + +MACHINE_START(SHARK, "Shark") + /* Maintainer: Alexander Schulz */ + .atag_offset = 0x3000, + .init_early = shark_init_early, + .init_irq = shark_init_irq, + .init_time = shark_timer_init, + .dma_zone_size = SZ_4M, + .restart = shark_restart, +MACHINE_END diff --git a/arch/arm/mach-shark/dma.c b/arch/arm/mach-shark/dma.c new file mode 100644 index 0000000..10b5b8b --- /dev/null +++ b/arch/arm/mach-shark/dma.c @@ -0,0 +1,23 @@ +/* + * linux/arch/arm/mach-shark/dma.c + * + * by Alexander Schulz + * + * derived from: + * arch/arm/kernel/dma-ebsa285.c + * Copyright (C) 1998 Phil Blundell + */ + +#include <linux/init.h> + +#include <asm/dma.h> +#include <asm/mach/dma.h> + +static int __init shark_dma_init(void) +{ +#ifdef CONFIG_ISA_DMA + isa_init_dma(); +#endif + return 0; +} +core_initcall(shark_dma_init); diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S new file mode 100644 index 0000000..d129119 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/debug-macro.S @@ -0,0 +1,34 @@ +/* arch/arm/mach-shark/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart, rp, rv, tmp + mov \rp, #0x3f8 + orr \rv, \rp, #0xfe000000 + orr \rv, \rv, #0x00e00000 + orr \rp, \rp, #0x40000000 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx] + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx + mov \rd, #0 +1001: add \rd, \rd, #1 + teq \rd, #0x10000 + bne 1001b + .endm + diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S new file mode 100644 index 0000000..c9e49f0 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/entry-macro.S @@ -0,0 +1,36 @@ +/* + * arch/arm/mach-shark/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Shark platform + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + .macro get_irqnr_preamble, base, tmp + mov \base, #0xfe000000 + orr \base, \base, #0x00e00000 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \irqstat, #0x0C + strb \irqstat, [\base, #0x20] @outb(0x0C, 0x20) /* Poll command */ + ldrb \irqnr, [\base, #0x20] @irq = inb(0x20) & 7 + and \irqstat, \irqnr, #0x80 + teq \irqstat, #0 + beq 43f + and \irqnr, \irqnr, #7 + teq \irqnr, #2 + bne 44f +43: mov \irqstat, #0x0C + strb \irqstat, [\base, #0xa0] @outb(0x0C, 0xA0) /* Poll command */ + ldrb \irqnr, [\base, #0xa0] @irq = (inb(0xA0) & 7) + 8 + and \irqstat, \irqnr, #0x80 + teq \irqstat, #0 + beq 44f + and \irqnr, \irqnr, #7 + add \irqnr, \irqnr, #8 +44: teq \irqstat, #0 + .endm + diff --git a/arch/arm/mach-shark/include/mach/framebuffer.h b/arch/arm/mach-shark/include/mach/framebuffer.h new file mode 100644 index 0000000..84a5bf6 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/framebuffer.h @@ -0,0 +1,16 @@ +/* + * arch/arm/mach-shark/include/mach/framebuffer.h + * + * by Alexander Schulz + * + */ + +#ifndef __ASM_ARCH_FRAMEBUFFER_H +#define __ASM_ARCH_FRAMEBUFFER_H + +/* defines for the Framebuffer */ +#define FB_START 0x06000000 +#define FB_SIZE 0x01000000 + +#endif + diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h new file mode 100644 index 0000000..663f952 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/hardware.h @@ -0,0 +1,16 @@ +/* + * arch/arm/mach-shark/include/mach/hardware.h + * + * by Alexander Schulz + * + * derived from: + * arch/arm/mach-ebsa110/include/mach/hardware.h + * Copyright (C) 1996-1999 Russell King. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#define UNCACHEABLE_ADDR 0xdf010000 + +#endif + diff --git a/arch/arm/mach-shark/include/mach/irqs.h b/arch/arm/mach-shark/include/mach/irqs.h new file mode 100644 index 0000000..c8e8a4e --- /dev/null +++ b/arch/arm/mach-shark/include/mach/irqs.h @@ -0,0 +1,13 @@ +/* + * arch/arm/mach-shark/include/mach/irqs.h + * + * by Alexander Schulz + */ + +#define NR_IRQS 16 + +#define IRQ_ISA_KEYBOARD 1 +#define IRQ_ISA_RTC_ALARM 8 +#define I8042_KBD_IRQ 1 +#define I8042_AUX_IRQ 12 +#define IRQ_HARDDISK 14 diff --git a/arch/arm/mach-shark/include/mach/isa-dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h new file mode 100644 index 0000000..96c43b8 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/isa-dma.h @@ -0,0 +1,13 @@ +/* + * arch/arm/mach-shark/include/mach/isa-dma.h + * + * by Alexander Schulz + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_CHANNELS 8 +#define DMA_ISA_CASCADE 4 + +#endif /* _ASM_ARCH_DMA_H */ + diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h new file mode 100644 index 0000000..1cf8d69 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-shark/include/mach/memory.h + * + * by Alexander Schulz + * + * derived from: + * arch/arm/mach-ebsa110/include/mach/memory.h + * Copyright (c) 1996-1999 Russell King. + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <asm/sizes.h> + +/* + * Physical DRAM offset. + */ +#define PLAT_PHYS_OFFSET UL(0x08000000) + +/* + * Cache flushing area + */ +#define FLUSH_BASE_PHYS 0x80000000 +#define FLUSH_BASE 0xdf000000 + +#endif diff --git a/arch/arm/mach-shark/include/mach/timex.h b/arch/arm/mach-shark/include/mach/timex.h new file mode 100644 index 0000000..bb6eeae --- /dev/null +++ b/arch/arm/mach-shark/include/mach/timex.h @@ -0,0 +1,7 @@ +/* + * arch/arm/mach-shark/include/mach/timex.h + * + * by Alexander Schulz + */ + +#define CLOCK_TICK_RATE 1193180 diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h new file mode 100644 index 0000000..a168435 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/uncompress.h @@ -0,0 +1,50 @@ +/* + * arch/arm/mach-shark/include/mach/uncompress.h + * by Alexander Schulz + * + * derived from: + * arch/arm/mach-footbridge/include/mach/uncompress.h + * Copyright (C) 1996,1997,1998 Russell King + */ + +#define SERIAL_BASE ((volatile unsigned char *)0x400003f8) + +static inline void putc(int c) +{ + volatile int t; + + SERIAL_BASE[0] = c; + t=0x10000; + while (t--); +} + +static inline void flush(void) +{ +} + +#ifdef DEBUG +static void putn(unsigned long z) +{ + int i; + char x; + + putc('0'); + putc('x'); + for (i=0;i<8;i++) { + x='0'+((z>>((7-i)*4))&0xf); + if (x>'9') x=x-'0'+'A'-10; + putc(x); + } +} + +static void putr() +{ + putc('\n'); + putc('\r'); +} +#endif + +/* + * nothing to do + */ +#define arch_decomp_setup() diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c new file mode 100644 index 0000000..5dce13e --- /dev/null +++ b/arch/arm/mach-shark/irq.c @@ -0,0 +1,108 @@ +/* + * linux/arch/arm/mach-shark/irq.c + * + * by Alexander Schulz + * + * derived from linux/arch/ppc/kernel/i8259.c and: + * arch/arm/mach-ebsa110/include/mach/irq.h + * Copyright (C) 1996-1998 Russell King + */ + +#include <linux/init.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/mach/irq.h> + +/* + * 8259A PIC functions to handle ISA devices: + */ + +/* + * This contains the irq mask for both 8259A irq controllers, + * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb) + */ +static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; + +/* + * These have to be protected by the irq controller spinlock + * before being called. + */ +static void shark_disable_8259A_irq(struct irq_data *d) +{ + unsigned int mask; + if (d->irq<8) { + mask = 1 << d->irq; + cached_irq_mask[0] |= mask; + outb(cached_irq_mask[1],0xA1); + } else { + mask = 1 << (d->irq-8); + cached_irq_mask[1] |= mask; + outb(cached_irq_mask[0],0x21); + } +} + +static void shark_enable_8259A_irq(struct irq_data *d) +{ + unsigned int mask; + if (d->irq<8) { + mask = ~(1 << d->irq); + cached_irq_mask[0] &= mask; + outb(cached_irq_mask[0],0x21); + } else { + mask = ~(1 << (d->irq-8)); + cached_irq_mask[1] &= mask; + outb(cached_irq_mask[1],0xA1); + } +} + +static void shark_ack_8259A_irq(struct irq_data *d){} + +static irqreturn_t bogus_int(int irq, void *dev_id) +{ + printk("Got interrupt %i!\n",irq); + return IRQ_NONE; +} + +static struct irqaction cascade; + +static struct irq_chip fb_chip = { + .name = "XT-PIC", + .irq_ack = shark_ack_8259A_irq, + .irq_mask = shark_disable_8259A_irq, + .irq_unmask = shark_enable_8259A_irq, +}; + +void __init shark_init_irq(void) +{ + int irq; + + for (irq = 0; irq < NR_IRQS; irq++) { + irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + + /* init master interrupt controller */ + outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/ + outb(0x00, 0x21); /* Vector base */ + outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ + outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ + outb(0x0A, 0x20); + /* init slave interrupt controller */ + outb(0x11, 0xA0); /* Start init sequence, edge triggered */ + outb(0x08, 0xA1); /* Vector base */ + outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */ + outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */ + outb(0x0A, 0xA0); + outb(cached_irq_mask[1],0xA1); + outb(cached_irq_mask[0],0x21); + //request_region(0x20,0x2,"pic1"); + //request_region(0xA0,0x2,"pic2"); + + cascade.handler = bogus_int; + cascade.name = "cascade"; + setup_irq(2,&cascade); +} + diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c new file mode 100644 index 0000000..081c778 --- /dev/null +++ b/arch/arm/mach-shark/leds.c @@ -0,0 +1,117 @@ +/* + * DIGITAL Shark LED control routines. + * + * Driver for the 3 user LEDs found on the Shark + * Based on Versatile and RealView machine LED code + * + * License terms: GNU General Public License (GPL) version 2 + * Author: Bryan Wu <bryan.wu@canonical.com> + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/slab.h> +#include <linux/leds.h> + +#include <asm/mach-types.h> + +#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) +struct shark_led { + struct led_classdev cdev; + u8 mask; +}; + +/* + * The triggers lines up below will only be used if the + * LED triggers are compiled in. + */ +static const struct { + const char *name; + const char *trigger; +} shark_leds[] = { + { "shark:amber0", "default-on", }, /* Bit 5 */ + { "shark:green", "heartbeat", }, /* Bit 6 */ + { "shark:amber1", "cpu0" }, /* Bit 7 */ +}; + +static u16 led_reg_read(void) +{ + outw(0x09, 0x24); + return inw(0x26); +} + +static void led_reg_write(u16 value) +{ + outw(0x09, 0x24); + outw(value, 0x26); +} + +static void shark_led_set(struct led_classdev *cdev, + enum led_brightness b) +{ + struct shark_led *led = container_of(cdev, + struct shark_led, cdev); + u16 reg = led_reg_read(); + + if (b != LED_OFF) + reg |= led->mask; + else + reg &= ~led->mask; + + led_reg_write(reg); +} + +static enum led_brightness shark_led_get(struct led_classdev *cdev) +{ + struct shark_led *led = container_of(cdev, + struct shark_led, cdev); + u16 reg = led_reg_read(); + + return (reg & led->mask) ? LED_FULL : LED_OFF; +} + +static int __init shark_leds_init(void) +{ + int i; + u16 reg; + + if (!machine_is_shark()) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(shark_leds); i++) { + struct shark_led *led; + + led = kzalloc(sizeof(*led), GFP_KERNEL); + if (!led) + break; + + led->cdev.name = shark_leds[i].name; + led->cdev.brightness_set = shark_led_set; + led->cdev.brightness_get = shark_led_get; + led->cdev.default_trigger = shark_leds[i].trigger; + + /* Count in 5 bits offset */ + led->mask = BIT(i + 5); + + if (led_classdev_register(NULL, &led->cdev) < 0) { + kfree(led); + break; + } + } + + /* Make LEDs independent of power-state */ + request_region(0x24, 4, "led_reg"); + reg = led_reg_read(); + reg |= 1 << 10; + led_reg_write(reg); + + return 0; +} + +/* + * Since we may have triggers on any subsystem, defer registration + * until after subsystem_init. + */ +fs_initcall(shark_leds_init); +#endif diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c new file mode 100644 index 0000000..6d91a91 --- /dev/null +++ b/arch/arm/mach-shark/pci.c @@ -0,0 +1,57 @@ +/* + * linux/arch/arm/mach-shark/pci.c + * + * PCI bios-type initialisation for PCI machines + * + * Bits taken from various places. + */ +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/io.h> +#include <video/vga.h> + +#include <asm/irq.h> +#include <asm/mach/pci.h> +#include <asm/mach-types.h> + +#define IO_START 0x40000000 + +static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (dev->bus->number == 0) + if (dev->devfn == 0) + return 255; + else + return 11; + else + return 255; +} + +extern void __init via82c505_preinit(void); + +static struct hw_pci shark_pci __initdata = { + .setup = via82c505_setup, + .map_irq = shark_map_irq, + .nr_controllers = 1, + .ops = &via82c505_ops, + .preinit = via82c505_preinit, +}; + +static int __init shark_pci_init(void) +{ + if (!machine_is_shark()) + return -ENODEV; + + pcibios_min_io = 0x6000; + pcibios_min_mem = 0x50000000; + vga_base = 0xe8000000; + + pci_ioremap_io(0, IO_START); + + pci_common_init(&shark_pci); + + return 0; +} + +subsys_initcall(shark_pci_init); diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index a4a4b75..1f94c31 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -22,10 +22,16 @@ config ARCH_EMEV2 comment "SH-Mobile Board Type" -config MACH_KZM9D - bool "KZM9D board" +config MACH_KZM9D_REFERENCE + bool "KZM9D board - Reference Device Tree Implementation" depends on ARCH_EMEV2 select REGULATOR_FIXED_VOLTAGE if REGULATOR + ---help--- + Use reference implementation of KZM9D board support + which makes a greater use of device tree at the expense + of not supporting a number of devices. + + This is intended to aid developers comment "SH-Mobile System Configuration" endif @@ -95,24 +101,12 @@ config ARCH_R8A7790 select SH_CLK_CPG select RENESAS_IRQC -config ARCH_R8A7791 - bool "R-Car M2 (R8A77910)" - select ARM_GIC - select CPU_V7 - select SH_CLK_CPG - config ARCH_EMEV2 bool "Emma Mobile EV2" select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC select CPU_V7 -config ARCH_R7S72100 - bool "RZ/A1H (R7S72100)" - select ARM_GIC - select CPU_V7 - select SH_CLK_CPG - comment "SH-Mobile Board Type" config MACH_APE6EVM @@ -168,8 +162,6 @@ config MACH_BOCKW select RENESAS_INTC_IRQPIN select REGULATOR_FIXED_VOLTAGE if REGULATOR select USE_OF - select SND_SOC_AK4554 if SND_SIMPLE_CARD - select SND_SOC_AK4642 if SND_SIMPLE_CARD config MACH_BOCKW_REFERENCE bool "BOCK-W - Reference Device Tree Implementation" @@ -185,11 +177,6 @@ config MACH_BOCKW_REFERENCE This is intended to aid developers -config MACH_GENMAI - bool "Genmai board" - depends on ARCH_R7S72100 - select USE_OF - config MACH_MARZEN bool "MARZEN board" depends on ARCH_R8A7779 @@ -226,17 +213,24 @@ config MACH_LAGER_REFERENCE This is intended to aid developers -config MACH_KOELSCH - bool "Koelsch board" - depends on ARCH_R8A7791 - select USE_OF - config MACH_KZM9D bool "KZM9D board" depends on ARCH_EMEV2 select REGULATOR_FIXED_VOLTAGE if REGULATOR select USE_OF +config MACH_KZM9D_REFERENCE + bool "KZM9D board - Reference Device Tree Implementation" + depends on ARCH_EMEV2 + select REGULATOR_FIXED_VOLTAGE if REGULATOR + select USE_OF + ---help--- + Use reference implementation of KZM9D board support + which makes a greater use of device tree at the expense + of not supporting a number of devices. + + This is intended to aid developers + config MACH_KZM9G bool "KZM-A9-GT board" depends on ARCH_SH73A0 diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 51db2bc..2705bfa 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -15,10 +15,7 @@ obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o -obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o setup-rcar-gen2.o -obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o setup-rcar-gen2.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o -obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o # Clock objects ifndef CONFIG_COMMON_CLK @@ -30,17 +27,13 @@ obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o -obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o -obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o endif # SMP objects smp-y := platsmp.o headsmp.o smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o -smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o platsmp-apmu.o -smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o platsmp-apmu.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o # IRQ objects @@ -55,26 +48,21 @@ obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o # Board objects -ifdef CONFIG_ARCH_SHMOBILE_MULTI -obj-$(CONFIG_MACH_KZM9D) += board-kzm9d-reference.o -else obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o -obj-$(CONFIG_MACH_GENMAI) += board-genmai.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o obj-$(CONFIG_MACH_LAGER) += board-lager.o obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o -obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o +obj-$(CONFIG_MACH_KZM9D_REFERENCE) += board-kzm9d-reference.o obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o -endif # Framework support obj-$(CONFIG_SMP) += $(smp-y) diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 391d72a..6a504fe 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -6,9 +6,8 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 -loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 -loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 +loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c index 3276afc..a23fa71 100644 --- a/arch/arm/mach-shmobile/board-ape6evm-reference.c +++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c @@ -57,7 +57,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(APE6EVM_DT, "ape6evm") - .init_early = r8a73a4_init_early, + .init_early = r8a73a4_init_delay, .init_machine = ape6evm_add_standard_devices, .dt_compat = ape6evm_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 0fa068e..24b87eea 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -86,7 +86,7 @@ static struct gpio_keys_button gpio_buttons[] = { GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"), }; -static struct gpio_keys_platform_data ape6evm_keys_pdata __initdata = { +static struct __initdata gpio_keys_platform_data ape6evm_keys_pdata = { .buttons = gpio_buttons, .nbuttons = ARRAY_SIZE(gpio_buttons), }; @@ -113,58 +113,22 @@ static const struct smsc911x_platform_config lan9220_data __initconst = { }; /* - * MMC0 power supplies: - * Both Vcc and VccQ to eMMC on APE6EVM are supplied by a tps80032 voltage - * regulator. Until support for it is added to this file we simulate the - * Vcc supply by a fixed always-on regulator + * On APE6EVM power is supplied to MMCIF by a tps80032 regulator. For now we + * model a VDD supply to MMCIF, using a fixed 3.3V regulator. Also use the + * static power supply for SDHI0 and SDHI1, whereas SDHI0's VccQ is also + * supplied by the same tps80032 regulator and thus can also be adjusted + * dynamically. */ -static struct regulator_consumer_supply vcc_mmc0_consumers[] = +static struct regulator_consumer_supply fixed3v3_power_consumers[] = { REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), -}; - -/* - * SDHI0 power supplies: - * Vcc to SDHI0 on APE6EVM is supplied by a GPIO-switchable regulator. VccQ is - * provided by the same tps80032 regulator as both MMC0 voltages - see comment - * above - */ -static struct regulator_consumer_supply vcc_sdhi0_consumers[] = -{ REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), -}; - -static struct regulator_init_data vcc_sdhi0_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), - .consumer_supplies = vcc_sdhi0_consumers, -}; - -static const struct fixed_voltage_config vcc_sdhi0_info __initconst = { - .supply_name = "SDHI0 Vcc", - .microvolts = 3300000, - .gpio = 76, - .enable_high = 1, - .init_data = &vcc_sdhi0_init_data, -}; - -/* - * SDHI1 power supplies: - * Vcc and VccQ to SDHI1 on APE6EVM are both fixed at 3.3V - */ -static struct regulator_consumer_supply vcc_sdhi1_consumers[] = -{ REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), }; /* MMCIF */ static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, - .slave_id_tx = SHDMA_SLAVE_MMCIF0_TX, - .slave_id_rx = SHDMA_SLAVE_MMCIF0_RX, - .ccs_unsupported = true, }; static const struct resource mmcif0_resources[] __initconst = { @@ -251,19 +215,14 @@ static void __init ape6evm_add_standard_devices(void) platform_device_register_resndata(&platform_bus, "smsc911x", -1, lan9220_res, ARRAY_SIZE(lan9220_res), &lan9220_data, sizeof(lan9220_data)); - - regulator_register_always_on(1, "MMC0 Vcc", vcc_mmc0_consumers, - ARRAY_SIZE(vcc_mmc0_consumers), 2800000); + regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); platform_device_register_resndata(&platform_bus, "sh_mmcif", 0, mmcif0_resources, ARRAY_SIZE(mmcif0_resources), &mmcif0_pdata, sizeof(mmcif0_pdata)); - platform_device_register_data(&platform_bus, "reg-fixed-voltage", 2, - &vcc_sdhi0_info, sizeof(vcc_sdhi0_info)); platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0, sdhi0_resources, ARRAY_SIZE(sdhi0_resources), &sdhi0_pdata, sizeof(sdhi0_pdata)); - regulator_register_always_on(3, "SDHI1 Vcc", vcc_sdhi1_consumers, - ARRAY_SIZE(vcc_sdhi1_consumers), 3300000); platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1, sdhi1_resources, ARRAY_SIZE(sdhi1_resources), &sdhi1_pdata, sizeof(sdhi1_pdata)); @@ -281,7 +240,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(APE6EVM_DT, "ape6evm") - .init_early = r8a73a4_init_early, + .init_early = r8a73a4_init_delay, .init_machine = ape6evm_add_standard_devices, .dt_compat = ape6evm_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 958e3cb..7f8f607 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -423,7 +423,6 @@ static struct platform_pwm_backlight_data pwm_backlight_data = { .max_brightness = 255, .dft_brightness = 255, .pwm_period_ns = 33333, /* 30kHz */ - .enable_gpio = -1, }; static struct platform_device pwm_backlight_device = { @@ -824,7 +823,6 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, - .ccs_unsupported = true, .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index ae88fda..1a7c893 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -36,35 +36,15 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { "scif0_ctrl", "scif0"), }; -#define FPGA 0x18200000 -#define IRQ0MR 0x30 -#define COMCTLR 0x101c static void __init bockw_init(void) { - static void __iomem *fpga; - r8a7778_clock_init(); - r8a7778_init_irq_extpin_dt(1); pinctrl_register_mappings(bockw_pinctrl_map, ARRAY_SIZE(bockw_pinctrl_map)); r8a7778_pinmux_init(); r8a7778_add_dt_devices(); - fpga = ioremap_nocache(FPGA, SZ_1M); - if (fpga) { - /* - * CAUTION - * - * IRQ0/1 is cascaded interrupt from FPGA. - * it should be cared in the future - * Now, it is assuming IRQ0 was used only from SMSC. - */ - u16 val = ioread16(fpga + IRQ0MR); - val &= ~(1 << 4); /* enable SMSC911x */ - iowrite16(val, fpga + IRQ0MR); - } - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 3861152..6b9faf3 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -32,19 +32,11 @@ #include <linux/smsc911x.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> -#include <linux/usb/renesas_usbhs.h> #include <media/soc_camera.h> #include <mach/common.h> #include <mach/irqs.h> #include <mach/r8a7778.h> #include <asm/mach/arch.h> -#include <sound/rcar_snd.h> -#include <sound/simple_card.h> - -#define FPGA 0x18200000 -#define IRQ0MR 0x30 -#define COMCTLR 0x101c -static void __iomem *fpga; /* * CN9(Upper side) SCIF/RCAN selection @@ -71,45 +63,6 @@ static void __iomem *fpga; * SW19 (MMC) 1 pin */ -/* - * SSI settings - * - * SW45: 1-4 side (SSI5 out, ROUT/LOUT CN19 Mid) - * SW46: 1101 (SSI6 Recorde) - * SW47: 1110 (SSI5 Playback) - * SW48: 11 (Recorde power) - * SW49: 1 (SSI slave mode) - * SW50: 1111 (SSI7, SSI8) - * SW51: 1111 (SSI3, SSI4) - * SW54: 1pin (ak4554 FPGA control) - * SW55: 1 (CLKB is 24.5760MHz) - * SW60: 1pin (ak4554 FPGA control) - * SW61: 3pin (use X11 clock) - * SW78: 3-6 (ak4642 connects I2C0) - * - * You can use sound as - * - * hw0: CN19: SSI56-AK4643 - * hw1: CN21: SSI3-AK4554(playback) - * hw2: CN21: SSI4-AK4554(capture) - * hw3: CN20: SSI7-AK4554(playback) - * hw4: CN20: SSI8-AK4554(capture) - * - * this command is required when playback on hw0. - * - * # amixer set "LINEOUT Mixer DACL" on - */ - -/* - * USB - * - * USB1 (CN29) can be Host/Function - * - * Host Func - * SW98 1 2 - * SW99 1 3 - */ - /* Dummy supplies, where voltage doesn't matter */ static struct regulator_consumer_supply dummy_supplies[] = { REGULATOR_SUPPLY("vddvario", "smsc911x"), @@ -128,76 +81,16 @@ static struct resource smsc911x_resources[] __initdata = { DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ }; -#if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) -/* - * When USB1 is Func - */ -static int usbhsf_get_id(struct platform_device *pdev) -{ - return USBHS_GADGET; -} - -#define SUSPMODE 0x102 -static int usbhsf_power_ctrl(struct platform_device *pdev, - void __iomem *base, int enable) -{ - enable = !!enable; - - r8a7778_usb_phy_power(enable); - - iowrite16(enable << 14, base + SUSPMODE); - - return 0; -} - -static struct resource usbhsf_resources[] __initdata = { - DEFINE_RES_MEM(0xffe60000, 0x110), - DEFINE_RES_IRQ(gic_iid(0x4f)), -}; - -static struct renesas_usbhs_platform_info usbhs_info __initdata = { - .platform_callback = { - .get_id = usbhsf_get_id, - .power_ctrl = usbhsf_power_ctrl, - }, - .driver_param = { - .buswait_bwait = 4, - }, -}; - -#define USB_PHY_SETTING {.port1_func = 1, .ovc_pin[1].active_high = 1,} -#define USB1_DEVICE "renesas_usbhs" -#define ADD_USB_FUNC_DEVICE_IF_POSSIBLE() \ - platform_device_register_resndata( \ - &platform_bus, "renesas_usbhs", -1, \ - usbhsf_resources, \ - ARRAY_SIZE(usbhsf_resources), \ - &usbhs_info, sizeof(struct renesas_usbhs_platform_info)) - -#else -/* - * When USB1 is Host - */ -#define USB_PHY_SETTING { } -#define USB1_DEVICE "ehci-platform" -#define ADD_USB_FUNC_DEVICE_IF_POSSIBLE() - -#endif - /* USB */ static struct resource usb_phy_resources[] __initdata = { DEFINE_RES_MEM(0xffe70800, 0x100), DEFINE_RES_MEM(0xffe76000, 0x100), }; -static struct rcar_phy_platform_data usb_phy_platform_data __initdata = - USB_PHY_SETTING; - +static struct rcar_phy_platform_data usb_phy_platform_data __initdata; /* SDHI */ static struct sh_mobile_sdhi_info sdhi0_info __initdata = { - .dma_slave_tx = HPBDMA_SLAVE_SDHI0_TX, - .dma_slave_rx = HPBDMA_SLAVE_SDHI0_RX, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, @@ -208,12 +101,6 @@ static struct resource sdhi0_resources[] __initdata = { DEFINE_RES_IRQ(gic_iid(0x77)), }; -/* Ether */ -static struct resource ether_resources[] __initdata = { - DEFINE_RES_MEM(0xfde00000, 0x400), - DEFINE_RES_IRQ(gic_iid(0x89)), -}; - static struct sh_eth_plat_data ether_platform_data __initdata = { .phy = 0x01, .edmac_endian = EDMAC_LITTLE_ENDIAN, @@ -231,9 +118,7 @@ static struct sh_eth_plat_data ether_platform_data __initdata = { static struct i2c_board_info i2c0_devices[] = { { I2C_BOARD_INFO("rx8581", 0x51), - }, { - I2C_BOARD_INFO("ak4643", 0x12), - } + }, }; /* HSPI*/ @@ -277,6 +162,10 @@ static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { MMC_CAP_NEEDS_POLL, }; +static struct rcar_vin_platform_data vin_platform_data __initdata = { + .flags = RCAR_VIN_BT656, +}; + /* In the default configuration both decoders reside on I2C bus 0 */ #define BOCKW_CAMERA(idx) \ static struct i2c_board_info camera##idx##_info = { \ @@ -292,237 +181,7 @@ static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = { \ BOCKW_CAMERA(0); BOCKW_CAMERA(1); -/* VIN */ -static struct rcar_vin_platform_data vin_platform_data __initdata = { - .flags = RCAR_VIN_BT656, -}; - -#define R8A7778_VIN(idx) \ -static struct resource vin##idx##_resources[] __initdata = { \ - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ - DEFINE_RES_IRQ(gic_iid(0x5a)), \ -}; \ - \ -static struct platform_device_info vin##idx##_info __initdata = { \ - .parent = &platform_bus, \ - .name = "r8a7778-vin", \ - .id = idx, \ - .res = vin##idx##_resources, \ - .num_res = ARRAY_SIZE(vin##idx##_resources), \ - .dma_mask = DMA_BIT_MASK(32), \ - .data = &vin_platform_data, \ - .size_data = sizeof(vin_platform_data), \ -} -R8A7778_VIN(0); -R8A7778_VIN(1); - -/* Sound */ -static struct resource rsnd_resources[] __initdata = { - [RSND_GEN1_SRU] = DEFINE_RES_MEM(0xffd90000, 0x1000), - [RSND_GEN1_SSI] = DEFINE_RES_MEM(0xffd91000, 0x1240), - [RSND_GEN1_ADG] = DEFINE_RES_MEM(0xfffe0000, 0x24), -}; - -static struct rsnd_ssi_platform_info rsnd_ssi[] = { - RSND_SSI_UNUSED, /* SSI 0 */ - RSND_SSI_UNUSED, /* SSI 1 */ - RSND_SSI_UNUSED, /* SSI 2 */ - RSND_SSI_SET(1, 0, gic_iid(0x85), RSND_SSI_PLAY), - RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE | RSND_SSI_CLK_FROM_ADG), - RSND_SSI_SET(0, 0, gic_iid(0x86), RSND_SSI_PLAY), - RSND_SSI_SET(0, 0, gic_iid(0x86), 0), - RSND_SSI_SET(3, 0, gic_iid(0x86), RSND_SSI_PLAY), - RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE | RSND_SSI_CLK_FROM_ADG), -}; - -static struct rsnd_scu_platform_info rsnd_scu[9] = { - /* no member at this point */ -}; - -enum { - AK4554_34 = 0, - AK4643_56, - AK4554_78, - SOUND_MAX, -}; - -static int rsnd_codec_power(int id, int enable) -{ - static int sound_user[SOUND_MAX] = {0, 0, 0}; - int *usr = NULL; - u32 bit; - - switch (id) { - case 3: - case 4: - usr = sound_user + AK4554_34; - bit = (1 << 10); - break; - case 5: - case 6: - usr = sound_user + AK4643_56; - bit = (1 << 6); - break; - case 7: - case 8: - usr = sound_user + AK4554_78; - bit = (1 << 7); - break; - } - - if (!usr) - return -EIO; - - if (enable) { - if (*usr == 0) { - u32 val = ioread16(fpga + COMCTLR); - val &= ~bit; - iowrite16(val, fpga + COMCTLR); - } - - (*usr)++; - } else { - if (*usr == 0) - return 0; - - (*usr)--; - - if (*usr == 0) { - u32 val = ioread16(fpga + COMCTLR); - val |= bit; - iowrite16(val, fpga + COMCTLR); - } - } - - return 0; -} - -static int rsnd_start(int id) -{ - return rsnd_codec_power(id, 1); -} - -static int rsnd_stop(int id) -{ - return rsnd_codec_power(id, 0); -} - -static struct rcar_snd_info rsnd_info = { - .flags = RSND_GEN1, - .ssi_info = rsnd_ssi, - .ssi_info_nr = ARRAY_SIZE(rsnd_ssi), - .scu_info = rsnd_scu, - .scu_info_nr = ARRAY_SIZE(rsnd_scu), - .start = rsnd_start, - .stop = rsnd_stop, -}; - -static struct asoc_simple_card_info rsnd_card_info[] = { - /* SSI5, SSI6 */ - { - .name = "AK4643", - .card = "SSI56-AK4643", - .codec = "ak4642-codec.0-0012", - .platform = "rcar_sound", - .daifmt = SND_SOC_DAIFMT_LEFT_J, - .cpu_dai = { - .name = "rsnd-dai.0", - .fmt = SND_SOC_DAIFMT_CBS_CFS, - }, - .codec_dai = { - .name = "ak4642-hifi", - .fmt = SND_SOC_DAIFMT_CBM_CFM, - .sysclk = 11289600, - }, - }, - /* SSI3 */ - { - .name = "AK4554", - .card = "SSI3-AK4554(playback)", - .codec = "ak4554-adc-dac.0", - .platform = "rcar_sound", - .cpu_dai = { - .name = "rsnd-dai.1", - .fmt = SND_SOC_DAIFMT_CBM_CFM | - SND_SOC_DAIFMT_RIGHT_J, - }, - .codec_dai = { - .name = "ak4554-hifi", - }, - }, - /* SSI4 */ - { - .name = "AK4554", - .card = "SSI4-AK4554(capture)", - .codec = "ak4554-adc-dac.0", - .platform = "rcar_sound", - .cpu_dai = { - .name = "rsnd-dai.2", - .fmt = SND_SOC_DAIFMT_CBM_CFM | - SND_SOC_DAIFMT_LEFT_J, - }, - .codec_dai = { - .name = "ak4554-hifi", - }, - }, - /* SSI7 */ - { - .name = "AK4554", - .card = "SSI7-AK4554(playback)", - .codec = "ak4554-adc-dac.1", - .platform = "rcar_sound", - .cpu_dai = { - .name = "rsnd-dai.3", - .fmt = SND_SOC_DAIFMT_CBM_CFM | - SND_SOC_DAIFMT_RIGHT_J, - }, - .codec_dai = { - .name = "ak4554-hifi", - }, - }, - /* SSI8 */ - { - .name = "AK4554", - .card = "SSI8-AK4554(capture)", - .codec = "ak4554-adc-dac.1", - .platform = "rcar_sound", - .cpu_dai = { - .name = "rsnd-dai.4", - .fmt = SND_SOC_DAIFMT_CBM_CFM | - SND_SOC_DAIFMT_LEFT_J, - }, - .codec_dai = { - .name = "ak4554-hifi", - }, - } -}; - static const struct pinctrl_map bockw_pinctrl_map[] = { - /* AUDIO */ - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "audio_clk_a", "audio_clk"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "audio_clk_b", "audio_clk"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi34_ctrl", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi3_data", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi4_data", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi5_ctrl", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi5_data", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi6_ctrl", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi6_data", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi78_ctrl", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi7_data", "ssi"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", - "ssi8_data", "ssi"), /* Ether */ PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", "ether_rmii", "ether"), @@ -542,7 +201,7 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { /* USB */ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", "usb0", "usb0"), - PIN_MAP_MUX_GROUP_DEFAULT(USB1_DEVICE, "pfc-r8a7778", + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", "usb1", "usb1"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", @@ -565,28 +224,22 @@ static const struct pinctrl_map bockw_pinctrl_map[] = { "vin1_data8", "vin1"), }; +#define FPGA 0x18200000 +#define IRQ0MR 0x30 #define PFC 0xfffc0000 #define PUPR4 0x110 static void __init bockw_init(void) { void __iomem *base; - struct clk *clk; - int i; r8a7778_clock_init(); r8a7778_init_irq_extpin(1); r8a7778_add_standard_devices(); - - platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - ðer_platform_data, - sizeof(ether_platform_data)); - - platform_device_register_full(&vin0_info); + r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_vin_device(0, &vin_platform_data); /* VIN1 has a pin conflict with Ether */ if (!IS_ENABLED(CONFIG_SH_ETH)) - platform_device_register_full(&vin1_info); + r8a7778_add_vin_device(1, &vin_platform_data); platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0, &iclink0_ml86v7667, sizeof(iclink0_ml86v7667)); @@ -616,8 +269,8 @@ static void __init bockw_init(void) /* for SMSC */ - fpga = ioremap_nocache(FPGA, SZ_1M); - if (fpga) { + base = ioremap_nocache(FPGA, SZ_1M); + if (base) { /* * CAUTION * @@ -625,9 +278,10 @@ static void __init bockw_init(void) * it should be cared in the future * Now, it is assuming IRQ0 was used only from SMSC. */ - u16 val = ioread16(fpga + IRQ0MR); + u16 val = ioread16(base + IRQ0MR); val &= ~(1 << 4); /* enable SMSC911x */ - iowrite16(val, fpga + IRQ0MR); + iowrite16(val, base + IRQ0MR); + iounmap(base); regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); @@ -654,42 +308,6 @@ static void __init bockw_init(void) sdhi0_resources, ARRAY_SIZE(sdhi0_resources), &sdhi0_info, sizeof(struct sh_mobile_sdhi_info)); } - - /* for Audio */ - clk = clk_get(NULL, "audio_clk_b"); - clk_set_rate(clk, 24576000); - clk_put(clk); - rsnd_codec_power(5, 1); /* enable ak4642 */ - - platform_device_register_simple( - "ak4554-adc-dac", 0, NULL, 0); - - platform_device_register_simple( - "ak4554-adc-dac", 1, NULL, 0); - - platform_device_register_resndata( - &platform_bus, "rcar_sound", -1, - rsnd_resources, ARRAY_SIZE(rsnd_resources), - &rsnd_info, sizeof(rsnd_info)); - - for (i = 0; i < ARRAY_SIZE(rsnd_card_info); i++) { - struct platform_device_info cardinfo = { - .parent = &platform_bus, - .name = "asoc-simple-card", - .id = i, - .data = &rsnd_card_info[i], - .size_data = sizeof(struct asoc_simple_card_info), - .dma_mask = ~0, - }; - - platform_device_register_full(&cardinfo); - } -} - -static void __init bockw_init_late(void) -{ - r8a7778_init_late(); - ADD_USB_FUNC_DEVICE_IF_POSSIBLE(); } static const char *bockw_boards_compat_dt[] __initdata = { @@ -702,5 +320,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw") .init_irq = r8a7778_init_irq_dt, .init_machine = bockw_init, .dt_compat = bockw_boards_compat_dt, - .init_late = bockw_init_late, + .init_late = r8a7778_init_late, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c deleted file mode 100644 index 3e92e3c..0000000 --- a/arch/arm/mach-shmobile/board-genmai.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Genmai board support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <mach/common.h> -#include <mach/r7s72100.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -static void __init genmai_add_standard_devices(void) -{ - r7s72100_clock_init(); - r7s72100_add_dt_devices(); -} - -static const char * const genmai_boards_compat_dt[] __initconst = { - "renesas,genmai", - NULL, -}; - -DT_MACHINE_START(GENMAI_DT, "genmai") - .init_early = r7s72100_init_early, - .init_machine = genmai_add_standard_devices, - .dt_compat = genmai_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c deleted file mode 100644 index ace1711..0000000 --- a/arch/arm/mach-shmobile/board-koelsch.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Koelsch board support - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <mach/common.h> -#include <mach/r8a7791.h> -#include <mach/rcar-gen2.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -static void __init koelsch_add_standard_devices(void) -{ - r8a7791_clock_init(); - r8a7791_add_standard_devices(); -} - -static const char * const koelsch_boards_compat_dt[] __initconst = { - "renesas,koelsch", - NULL, -}; - -DT_MACHINE_START(KOELSCH_DT, "koelsch") - .smp = smp_ops(r8a7791_smp_ops), - .init_early = r8a7791_init_early, - .init_machine = koelsch_add_standard_devices, - .init_time = rcar_gen2_timer_init, - .dt_compat = koelsch_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c index 054d8d5..8f8bb2f 100644 --- a/arch/arm/mach-shmobile/board-kzm9d-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c @@ -33,7 +33,6 @@ static void __init kzm9d_add_standard_devices(void) } static const char *kzm9d_boards_compat_dt[] __initdata = { - "renesas,kzm9d", "renesas,kzm9d-reference", NULL, }; diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index fe689b7..f199496 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -366,7 +366,6 @@ static struct resource sh_mmcif_resources[] = { static struct sh_mmcif_plat_data sh_mmcif_platdata = { .ocr = MMC_VDD_165_195, .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, - .ccs_unsupported = true, .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, }; diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 1a1a4a8..9c316a1 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -38,9 +38,8 @@ static const char *lager_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(LAGER_DT, "lager") - .smp = smp_ops(r8a7790_smp_ops), - .init_early = r8a7790_init_early, - .init_time = rcar_gen2_timer_init, + .init_early = r8a7790_init_delay, .init_machine = lager_add_standard_devices, + .init_time = r8a7790_timer_init, .dt_compat = lager_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index a8d3ce6..5930af8 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -28,7 +28,6 @@ #include <linux/mmc/sh_mmcif.h> #include <linux/pinctrl/machine.h> #include <linux/platform_data/gpio-rcar.h> -#include <linux/platform_data/rcar-du.h> #include <linux/platform_device.h> #include <linux/phy.h> #include <linux/regulator/fixed.h> @@ -40,62 +39,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -/* DU */ -static struct rcar_du_encoder_data lager_du_encoders[] = { - { - .type = RCAR_DU_ENCODER_VGA, - .output = RCAR_DU_OUTPUT_DPAD0, - }, { - .type = RCAR_DU_ENCODER_NONE, - .output = RCAR_DU_OUTPUT_LVDS1, - .connector.lvds.panel = { - .width_mm = 210, - .height_mm = 158, - .mode = { - .clock = 65000, - .hdisplay = 1024, - .hsync_start = 1048, - .hsync_end = 1184, - .htotal = 1344, - .vdisplay = 768, - .vsync_start = 771, - .vsync_end = 777, - .vtotal = 806, - .flags = 0, - }, - }, - }, -}; - -static const struct rcar_du_platform_data lager_du_pdata __initconst = { - .encoders = lager_du_encoders, - .num_encoders = ARRAY_SIZE(lager_du_encoders), -}; - -static const struct resource du_resources[] __initconst = { - DEFINE_RES_MEM(0xfeb00000, 0x70000), - DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), - DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"), - DEFINE_RES_IRQ(gic_spi(256)), - DEFINE_RES_IRQ(gic_spi(268)), - DEFINE_RES_IRQ(gic_spi(269)), -}; - -static void __init lager_add_du_device(void) -{ - struct platform_device_info info = { - .name = "rcar-du-r8a7790", - .id = -1, - .res = du_resources, - .num_res = ARRAY_SIZE(du_resources), - .data = &lager_du_pdata, - .size_data = sizeof(lager_du_pdata), - .dma_mask = DMA_BIT_MASK(32), - }; - - platform_device_register_full(&info); -} - /* LEDS */ static struct gpio_led lager_leds[] = { { @@ -113,7 +56,7 @@ static struct gpio_led lager_leds[] = { }, }; -static const struct gpio_led_platform_data lager_leds_pdata __initconst = { +static __initdata struct gpio_led_platform_data lager_leds_pdata = { .leds = lager_leds, .num_leds = ARRAY_SIZE(lager_leds), }; @@ -129,7 +72,7 @@ static struct gpio_keys_button gpio_buttons[] = { GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"), }; -static const struct gpio_keys_platform_data lager_keys_pdata __initconst = { +static __initdata struct gpio_keys_platform_data lager_keys_pdata = { .buttons = gpio_buttons, .nbuttons = ARRAY_SIZE(gpio_buttons), }; @@ -141,38 +84,29 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = }; /* MMCIF */ -static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = { +static struct sh_mmcif_plat_data mmcif1_pdata __initdata = { .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, - .clk_ctrl2_present = true, - .ccs_unsupported = true, }; -static const struct resource mmcif1_resources[] __initconst = { +static struct resource mmcif1_resources[] __initdata = { DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), DEFINE_RES_IRQ(gic_spi(170)), }; /* Ether */ -static const struct sh_eth_plat_data ether_pdata __initconst = { +static struct sh_eth_plat_data ether_pdata __initdata = { .phy = 0x1, .edmac_endian = EDMAC_LITTLE_ENDIAN, .phy_interface = PHY_INTERFACE_MODE_RMII, .ether_link_active_low = 1, }; -static const struct resource ether_resources[] __initconst = { +static struct resource ether_resources[] __initdata = { DEFINE_RES_MEM(0xee700000, 0x400), DEFINE_RES_IRQ(gic_spi(162)), }; static const struct pinctrl_map lager_pinctrl_map[] = { - /* DU (CN10: ARGB0, CN13: LVDS) */ - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", - "du_rgb666", "du"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", - "du_sync_1", "du"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790", - "du_clk_out_0", "du"), /* SCIF0 (CN19: DEBUG SERIAL0) */ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", "scif0_data", "scif0"), @@ -220,8 +154,6 @@ static void __init lager_add_standard_devices(void) ether_resources, ARRAY_SIZE(ether_resources), ðer_pdata, sizeof(ether_pdata)); - - lager_add_du_device(); } /* @@ -248,15 +180,14 @@ static void __init lager_init(void) phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup); } -static const char * const lager_boards_compat_dt[] __initconst = { +static const char *lager_boards_compat_dt[] __initdata = { "renesas,lager", NULL, }; DT_MACHINE_START(LAGER_DT, "lager") - .smp = smp_ops(r8a7790_smp_ops), - .init_early = r8a7790_init_early, - .init_time = rcar_gen2_timer_init, + .init_early = r8a7790_init_delay, + .init_time = r8a7790_timer_init, .init_machine = lager_init, .dt_compat = lager_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c index 2773936..3f4250a 100644 --- a/arch/arm/mach-shmobile/board-marzen-reference.c +++ b/arch/arm/mach-shmobile/board-marzen-reference.c @@ -28,7 +28,6 @@ static void __init marzen_init(void) { r8a7779_add_standard_devices_dt(); - r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */ } static const char *marzen_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index da1352f..3f5044f 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -30,7 +30,6 @@ #include <linux/dma-mapping.h> #include <linux/pinctrl/machine.h> #include <linux/platform_data/gpio-rcar.h> -#include <linux/platform_data/rcar-du.h> #include <linux/platform_data/usb-rcar-phy.h> #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> @@ -125,8 +124,6 @@ static struct resource sdhi0_resources[] = { }; static struct sh_mobile_sdhi_info sdhi0_platform_data = { - .dma_slave_tx = HPBDMA_SLAVE_SDHI0_TX, - .dma_slave_rx = HPBDMA_SLAVE_SDHI0_RX, .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, .tmio_caps = MMC_CAP_SD_HIGHSPEED, }; @@ -172,63 +169,6 @@ static struct platform_device hspi_device = { .num_resources = ARRAY_SIZE(hspi_resources), }; -/* - * DU - * - * The panel only specifies the [hv]display and [hv]total values. The position - * and width of the sync pulses don't matter, they're copied from VESA timings. - */ -static struct rcar_du_encoder_data du_encoders[] = { - { - .type = RCAR_DU_ENCODER_VGA, - .output = RCAR_DU_OUTPUT_DPAD0, - }, { - .type = RCAR_DU_ENCODER_LVDS, - .output = RCAR_DU_OUTPUT_DPAD1, - .connector.lvds.panel = { - .width_mm = 210, - .height_mm = 158, - .mode = { - .clock = 65000, - .hdisplay = 1024, - .hsync_start = 1048, - .hsync_end = 1184, - .htotal = 1344, - .vdisplay = 768, - .vsync_start = 771, - .vsync_end = 777, - .vtotal = 806, - .flags = 0, - }, - }, - }, -}; - -static const struct rcar_du_platform_data du_pdata __initconst = { - .encoders = du_encoders, - .num_encoders = ARRAY_SIZE(du_encoders), -}; - -static const struct resource du_resources[] __initconst = { - DEFINE_RES_MEM(0xfff80000, 0x40000), - DEFINE_RES_IRQ(gic_iid(0x3f)), -}; - -static void __init marzen_add_du_device(void) -{ - struct platform_device_info info = { - .name = "rcar-du-r8a7779", - .id = -1, - .res = du_resources, - .num_res = ARRAY_SIZE(du_resources), - .data = &du_pdata, - .size_data = sizeof(du_pdata), - .dma_mask = DMA_BIT_MASK(32), - }; - - platform_device_register_full(&info); -} - /* LEDS */ static struct gpio_led marzen_leds[] = { { @@ -297,19 +237,6 @@ static struct platform_device *marzen_devices[] __initdata = { }; static const struct pinctrl_map marzen_pinctrl_map[] = { - /* DU (CN10: ARGB0, CN13: LVDS) */ - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du0_rgb888", "du0"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du0_sync_1", "du0"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du0_clk_out_0", "du0"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du1_rgb666", "du1"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du1_sync_1", "du1"), - PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779", - "du1_clk_out", "du1"), /* HSPI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", "hspi0", "hspi0"), @@ -370,7 +297,6 @@ static void __init marzen_init(void) r8a7779_add_vin_device(1, &vin_platform_data); r8a7779_add_vin_device(3, &vin_platform_data); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); - marzen_add_du_device(); } static const char *marzen_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c deleted file mode 100644 index 4aba20c..0000000 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * r7a72100 clock framework support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2011 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> -#include <mach/common.h> -#include <mach/r7s72100.h> - -/* registers */ -#define FRQCR 0xfcfe0010 -#define FRQCR2 0xfcfe0014 -#define STBCR3 0xfcfe0420 -#define STBCR4 0xfcfe0424 - -#define PLL_RATE 30 - -static struct clk_mapping cpg_mapping = { - .phys = 0xfcfe0000, - .len = 0x1000, -}; - -/* Fixed 32 KHz root clock for RTC */ -static struct clk r_clk = { - .rate = 32768, -}; - -/* - * Default rate for the root input clock, reset this with clk_set_rate() - * from the platform code. - */ -static struct clk extal_clk = { - .rate = 13330000, - .mapping = &cpg_mapping, -}; - -static unsigned long pll_recalc(struct clk *clk) -{ - return clk->parent->rate * PLL_RATE; -} - -static struct sh_clk_ops pll_clk_ops = { - .recalc = pll_recalc, -}; - -static struct clk pll_clk = { - .ops = &pll_clk_ops, - .parent = &extal_clk, - .flags = CLK_ENABLE_ON_INIT, -}; - -static unsigned long bus_recalc(struct clk *clk) -{ - return clk->parent->rate * 2 / 3; -} - -static struct sh_clk_ops bus_clk_ops = { - .recalc = bus_recalc, -}; - -static struct clk bus_clk = { - .ops = &bus_clk_ops, - .parent = &pll_clk, - .flags = CLK_ENABLE_ON_INIT, -}; - -static unsigned long peripheral0_recalc(struct clk *clk) -{ - return clk->parent->rate / 12; -} - -static struct sh_clk_ops peripheral0_clk_ops = { - .recalc = peripheral0_recalc, -}; - -static struct clk peripheral0_clk = { - .ops = &peripheral0_clk_ops, - .parent = &pll_clk, - .flags = CLK_ENABLE_ON_INIT, -}; - -static unsigned long peripheral1_recalc(struct clk *clk) -{ - return clk->parent->rate / 6; -} - -static struct sh_clk_ops peripheral1_clk_ops = { - .recalc = peripheral1_recalc, -}; - -static struct clk peripheral1_clk = { - .ops = &peripheral1_clk_ops, - .parent = &pll_clk, - .flags = CLK_ENABLE_ON_INIT, -}; - -struct clk *main_clks[] = { - &r_clk, - &extal_clk, - &pll_clk, - &bus_clk, - &peripheral0_clk, - &peripheral1_clk, -}; - -static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */ -static int multipliers[] = { 1, 2, 1, 1 }; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = div2, - .nr_divisors = ARRAY_SIZE(div2), - .multipliers = multipliers, - .nr_multipliers = ARRAY_SIZE(multipliers), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, -}; - -enum { DIV4_I, - DIV4_NR }; - -#define DIV4(_reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) - -/* The mask field specifies the div2 entries that are valid */ -struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT - | CLK_ENABLE_ON_INIT), -}; - -enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, - MSTP33, MSTP_NR }; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ - [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ - [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ - [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */ - [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */ - [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */ - [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */ - [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */ - [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */ -}; - -static struct clk_lookup lookups[] = { - /* main clocks */ - CLKDEV_CON_ID("rclk", &r_clk), - CLKDEV_CON_ID("extal", &extal_clk), - CLKDEV_CON_ID("pll_clk", &pll_clk), - CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk), - - /* DIV4 clocks */ - CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), - - /* MSTP clocks */ - CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]), - CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]), -}; - -void __init r7s72100_clock_init(void) -{ - int k, ret = 0; - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup rza1 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 571409b..5bd2e85 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { - MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, MSTP411, MSTP410, MSTP409, @@ -519,7 +519,6 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ - [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */ [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ @@ -579,8 +578,6 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), - CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), - CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index fb6af83..c4bf2d8 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -69,15 +69,6 @@ static struct clk extal_clk = { .mapping = &cpg_mapping, }; -static struct clk audio_clk_a = { -}; - -static struct clk audio_clk_b = { -}; - -static struct clk audio_clk_c = { -}; - /* * clock ratio of these clock will be updated * on r8a7778_clock_init() @@ -109,23 +100,18 @@ static struct clk *main_clks[] = { &p_clk, &g_clk, &z_clk, - &audio_clk_a, - &audio_clk_b, - &audio_clk_c, }; enum { MSTP331, MSTP323, MSTP322, MSTP321, - MSTP311, MSTP310, - MSTP309, MSTP308, MSTP307, MSTP114, MSTP110, MSTP109, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, - MSTP016, MSTP015, MSTP012, MSTP011, MSTP010, - MSTP009, MSTP008, MSTP007, + MSTP016, MSTP015, + MSTP007, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { @@ -133,11 +119,6 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ - [MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */ - [MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */ - [MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */ - [MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */ - [MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */ [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ @@ -154,20 +135,11 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ - [MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */ - [MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */ - [MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */ - [MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */ - [MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */ [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ }; static struct clk_lookup lookups[] = { /* main */ - CLKDEV_CON_ID("audio_clk_a", &audio_clk_a), - CLKDEV_CON_ID("audio_clk_b", &audio_clk_b), - CLKDEV_CON_ID("audio_clk_c", &audio_clk_c), - CLKDEV_CON_ID("audio_clk_internal", &s1_clk), CLKDEV_CON_ID("shyway_clk", &s_clk), CLKDEV_CON_ID("peripheral_clk", &p_clk), @@ -181,7 +153,6 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ - CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ @@ -197,17 +168,6 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ - CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ - - CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), - CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]), - CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]), - CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]), - CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]), - CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]), - CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), - CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), - CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), }; void __init r8a7778_clock_init(void) diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1f7080f..bd6ad92 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -200,7 +200,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ - CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ + CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ }; void __init r8a7779_clock_init(void) diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index a64f965..fc36d3d 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -52,7 +52,6 @@ #define SMSTPCR5 0xe6150144 #define SMSTPCR7 0xe615014c #define SMSTPCR8 0xe6150990 -#define SMSTPCR9 0xe6150994 #define SDCKCR 0xE6150074 #define SD2CKCR 0xE6150078 @@ -182,9 +181,8 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { - MSTP931, MSTP930, MSTP929, MSTP928, MSTP813, - MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, + MSTP721, MSTP720, MSTP717, MSTP716, MSTP522, MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, @@ -194,16 +192,7 @@ enum { }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ - [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ - [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ - [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ - [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ - [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ - [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ - [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ - [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */ [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ @@ -262,11 +251,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), /* MSTP */ - CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), - CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), - CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), - CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), - CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -277,10 +261,6 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), - CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), - CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), - CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), - CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), @@ -310,7 +290,7 @@ static struct clk_lookup lookups[] = { void __init r8a7790_clock_init(void) { - u32 mode = rcar_gen2_read_mode_pins(); + u32 mode = r8a7790_read_mode_pins(); int k, ret = 0; switch (mode & (MD(14) | MD(13))) { diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c deleted file mode 100644 index c9a26f1..0000000 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * r8a7791 clock framework support - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <linux/init.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> -#include <mach/clock.h> -#include <mach/common.h> - -/* - * MD EXTAL PLL0 PLL1 PLL3 - * 14 13 19 (MHz) *1 *1 - *--------------------------------------------------- - * 0 0 0 15 x 1 x172/2 x208/2 x106 - * 0 0 1 15 x 1 x172/2 x208/2 x88 - * 0 1 0 20 x 1 x130/2 x156/2 x80 - * 0 1 1 20 x 1 x130/2 x156/2 x66 - * 1 0 0 26 / 2 x200/2 x240/2 x122 - * 1 0 1 26 / 2 x200/2 x240/2 x102 - * 1 1 0 30 / 2 x172/2 x208/2 x106 - * 1 1 1 30 / 2 x172/2 x208/2 x88 - * - * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) - * see "p1 / 2" on R8A7791_CLOCK_ROOT() below - */ - -#define MD(nr) (1 << nr) - -#define CPG_BASE 0xe6150000 -#define CPG_LEN 0x1000 - -#define SMSTPCR0 0xE6150130 -#define SMSTPCR1 0xE6150134 -#define SMSTPCR2 0xe6150138 -#define SMSTPCR3 0xE615013C -#define SMSTPCR5 0xE6150144 -#define SMSTPCR7 0xe615014c -#define SMSTPCR8 0xE6150990 -#define SMSTPCR9 0xE6150994 -#define SMSTPCR10 0xE6150998 -#define SMSTPCR11 0xE615099C - -#define MODEMR 0xE6160060 -#define SDCKCR 0xE6150074 -#define SD2CKCR 0xE6150078 -#define SD3CKCR 0xE615007C -#define MMC0CKCR 0xE6150240 -#define MMC1CKCR 0xE6150244 -#define SSPCKCR 0xE6150248 -#define SSPRSCKCR 0xE615024C - -static struct clk_mapping cpg_mapping = { - .phys = CPG_BASE, - .len = CPG_LEN, -}; - -static struct clk extal_clk = { - /* .rate will be updated on r8a7791_clock_init() */ - .mapping = &cpg_mapping, -}; - -static struct sh_clk_ops followparent_clk_ops = { - .recalc = followparent_recalc, -}; - -static struct clk main_clk = { - /* .parent will be set r8a73a4_clock_init */ - .ops = &followparent_clk_ops, -}; - -/* - * clock ratio of these clock will be updated - * on r8a7791_clock_init() - */ -SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1); - -/* fixed ratio clock */ -SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2); -SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2); - -SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2); -SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); -SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); -SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); -SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); - -static struct clk *main_clks[] = { - &extal_clk, - &extal_div2_clk, - &main_clk, - &pll1_clk, - &pll1_div2_clk, - &pll3_clk, - &hp_clk, - &p_clk, - &rclk_clk, - &mp_clk, - &cp_clk, -}; - -/* MSTP */ -enum { - MSTP721, MSTP720, - MSTP719, MSTP718, MSTP715, MSTP714, - MSTP216, MSTP207, MSTP206, - MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, - MSTP124, - MSTP_NR -}; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ - [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ - [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ - [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ - [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ - [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ - [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ - [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */ - [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */ - [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */ - [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */ -}; - -static struct clk_lookup lookups[] = { - - /* main clocks */ - CLKDEV_CON_ID("extal", &extal_clk), - CLKDEV_CON_ID("extal_div2", &extal_div2_clk), - CLKDEV_CON_ID("main", &main_clk), - CLKDEV_CON_ID("pll1", &pll1_clk), - CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), - CLKDEV_CON_ID("pll3", &pll3_clk), - CLKDEV_CON_ID("hp", &hp_clk), - CLKDEV_CON_ID("p", &p_clk), - CLKDEV_CON_ID("rclk", &rclk_clk), - CLKDEV_CON_ID("mp", &mp_clk), - CLKDEV_CON_ID("cp", &cp_clk), - CLKDEV_CON_ID("peripheral_clk", &hp_clk), - - /* MSTP */ - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */ - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */ - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */ - CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */ - CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */ - CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */ - CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */ - CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */ - CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */ - CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */ - CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ - CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ - CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), -}; - -#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ - extal_clk.rate = e * 1000 * 1000; \ - main_clk.parent = m; \ - SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \ - if (mode & MD(19)) \ - SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \ - else \ - SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1) - - -void __init r8a7791_clock_init(void) -{ - void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); - u32 mode; - int k, ret = 0; - - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); - - switch (mode & (MD(14) | MD(13))) { - case 0: - R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); - break; - case MD(13): - R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); - break; - case MD(14): - R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); - break; - case MD(13) | MD(14): - R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); - break; - } - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - goto epanic; - - return; - -epanic: - panic("failed to setup r8a7791 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index e5be5c8..f93751c 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -40,9 +40,6 @@ shmobile_boot_fn: .globl shmobile_boot_arg shmobile_boot_arg: 2: .space 4 - .globl shmobile_boot_size -shmobile_boot_size: - .long . - shmobile_boot_vector /* * Per-CPU SMP boot function/argument selection code based on MPIDR diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index e319805..7b93868 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -9,23 +9,16 @@ extern void shmobile_setup_console(void); extern void shmobile_boot_vector(void); extern unsigned long shmobile_boot_fn; extern unsigned long shmobile_boot_arg; -extern unsigned long shmobile_boot_size; extern void shmobile_smp_boot(void); extern void shmobile_smp_sleep(void); extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg); -extern int shmobile_smp_cpu_disable(unsigned int cpu); -extern void shmobile_invalidate_start(void); extern void shmobile_boot_scu(void); extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); +extern int shmobile_smp_scu_boot_secondary(unsigned int cpu, + struct task_struct *idle); extern void shmobile_smp_scu_cpu_die(unsigned int cpu); extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); -extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus); -extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu, - struct task_struct *idle); -extern void shmobile_smp_apmu_cpu_die(unsigned int cpu); -extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu); -extern void shmobile_invalidate_start(void); struct clk; extern int shmobile_clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); @@ -46,6 +39,7 @@ static inline int shmobile_cpuidle_init(void) { return 0; } #endif extern void __iomem *shmobile_scu_base; +extern void shmobile_smp_init_cpus(unsigned int ncores); static inline void __init shmobile_init_late(void) { diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/include/mach/r7s72100.h deleted file mode 100644 index 5f34b20..0000000 --- a/arch/arm/mach-shmobile/include/mach/r7s72100.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_R7S72100_H__ -#define __ASM_R7S72100_H__ - -void r7s72100_add_dt_devices(void); -void r7s72100_clock_init(void); -void r7s72100_init_early(void); - -#endif /* __ASM_R7S72100_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index ce8bdd1..f3a9b70 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -1,19 +1,10 @@ #ifndef __ASM_R8A73A4_H__ #define __ASM_R8A73A4_H__ -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_MMCIF0_TX, - SHDMA_SLAVE_MMCIF0_RX, - SHDMA_SLAVE_MMCIF1_TX, - SHDMA_SLAVE_MMCIF1_RX, -}; - void r8a73a4_add_standard_devices(void); void r8a73a4_add_dt_devices(void); void r8a73a4_clock_init(void); void r8a73a4_pinmux_init(void); -void r8a73a4_init_early(void); +void r8a73a4_init_delay(void); #endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 441886c..adfcf51 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -1,7 +1,6 @@ /* * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,15 +21,11 @@ #include <linux/sh_eth.h> #include <linux/platform_data/camera-rcar.h> -/* HPB-DMA slave IDs */ -enum { - HPBDMA_SLAVE_DUMMY, - HPBDMA_SLAVE_SDHI0_TX, - HPBDMA_SLAVE_SDHI0_RX, -}; - extern void r8a7778_add_standard_devices(void); extern void r8a7778_add_standard_devices_dt(void); +extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7778_add_vin_device(int id, + struct rcar_vin_platform_data *pdata); extern void r8a7778_add_dt_devices(void); extern void r8a7778_init_late(void); @@ -38,9 +33,6 @@ extern void r8a7778_init_delay(void); extern void r8a7778_init_irq_dt(void); extern void r8a7778_clock_init(void); extern void r8a7778_init_irq_extpin(int irlm); -extern void r8a7778_init_irq_extpin_dt(int irlm); extern void r8a7778_pinmux_init(void); -extern int r8a7778_usb_phy_power(bool enable); - #endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 17af34e..11c7400 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -6,13 +6,6 @@ #include <linux/sh_eth.h> #include <linux/platform_data/camera-rcar.h> -/* HPB-DMA slave IDs */ -enum { - HPBDMA_SLAVE_DUMMY, - HPBDMA_SLAVE_SDHI0_TX, - HPBDMA_SLAVE_SDHI0_RX, -}; - struct platform_device; struct r8a7779_pm_ch { @@ -33,7 +26,6 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) extern void r8a7779_init_delay(void); extern void r8a7779_init_irq_extpin(int irlm); -extern void r8a7779_init_irq_extpin_dt(int irlm); extern void r8a7779_init_irq_dt(void); extern void r8a7779_map_io(void); extern void r8a7779_earlytimer_init(void); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 5fbfa28..788d559 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -1,13 +1,14 @@ #ifndef __ASM_R8A7790_H__ #define __ASM_R8A7790_H__ -#include <mach/rcar-gen2.h> - void r8a7790_add_standard_devices(void); void r8a7790_add_dt_devices(void); void r8a7790_clock_init(void); void r8a7790_pinmux_init(void); -void r8a7790_init_early(void); -extern struct smp_operations r8a7790_smp_ops; +void r8a7790_init_delay(void); +void r8a7790_timer_init(void); + +#define MD(nr) BIT(nr) +u32 r8a7790_read_mode_pins(void); #endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h deleted file mode 100644 index 051ead3..0000000 --- a/arch/arm/mach-shmobile/include/mach/r8a7791.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __ASM_R8A7791_H__ -#define __ASM_R8A7791_H__ - -void r8a7791_add_standard_devices(void); -void r8a7791_add_dt_devices(void); -void r8a7791_clock_init(void); -void r8a7791_init_early(void); -extern struct smp_operations r8a7791_smp_ops; - -#endif /* __ASM_R8A7791_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/include/mach/rcar-gen2.h deleted file mode 100644 index 43f606e..0000000 --- a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_RCAR_GEN2_H__ -#define __ASM_RCAR_GEN2_H__ - -void rcar_gen2_timer_init(void); -#define MD(nr) BIT(nr) -u32 rcar_gen2_read_mode_pins(void); - -#endif /* __ASM_RCAR_GEN2_H__ */ diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c deleted file mode 100644 index 1da5a72..0000000 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * SMP support for SoCs with APMU - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/of_address.h> -#include <linux/smp.h> -#include <asm/cacheflush.h> -#include <asm/cp15.h> -#include <asm/smp_plat.h> -#include <mach/common.h> - -static struct { - void __iomem *iomem; - int bit; -} apmu_cpus[CONFIG_NR_CPUS]; - -#define WUPCR_OFFS 0x10 -#define PSTR_OFFS 0x40 -#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) - -static int apmu_power_on(void __iomem *p, int bit) -{ - /* request power on */ - writel_relaxed(BIT(bit), p + WUPCR_OFFS); - - /* wait for APMU to finish */ - while (readl_relaxed(p + WUPCR_OFFS) != 0) - ; - - return 0; -} - -static int apmu_power_off(void __iomem *p, int bit) -{ - /* request Core Standby for next WFI */ - writel_relaxed(3, p + CPUNCR_OFFS(bit)); - return 0; -} - -static int apmu_power_off_poll(void __iomem *p, int bit) -{ - int k; - - for (k = 0; k < 1000; k++) { - if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) - return 1; - - mdelay(1); - } - - return 0; -} - -static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu)) -{ - void __iomem *p = apmu_cpus[cpu].iomem; - - return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL; -} - -static void apmu_init_cpu(struct resource *res, int cpu, int bit) -{ - if (apmu_cpus[cpu].iomem) - return; - - apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res)); - apmu_cpus[cpu].bit = bit; - - pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit, - res->start, resource_size(res)); -} - -static struct { - struct resource iomem; - int cpus[4]; -} apmu_config[] = { - { - .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), - .cpus = { 0, 1, 2, 3 }, - }, - { - .iomem = DEFINE_RES_MEM(0xe6151000, 0x88), - .cpus = { 0x100, 0x101, 0x102, 0x103 }, - } -}; - -static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit)) -{ - u32 id; - int k; - int bit, index; - bool is_allowed; - - for (k = 0; k < ARRAY_SIZE(apmu_config); k++) { - /* only enable the cluster that includes the boot CPU */ - is_allowed = false; - for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { - id = apmu_config[k].cpus[bit]; - if (id >= 0) { - if (id == cpu_logical_map(0)) - is_allowed = true; - } - } - if (!is_allowed) - continue; - - for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) { - id = apmu_config[k].cpus[bit]; - if (id >= 0) { - index = get_logical_index(id); - if (index >= 0) - fn(&apmu_config[k].iomem, index, bit); - } - } - } -} - -void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus) -{ - /* install boot code shared by all CPUs */ - shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); - shmobile_boot_arg = MPIDR_HWID_BITMASK; - - /* perform per-cpu setup */ - apmu_parse_cfg(apmu_init_cpu); -} - -int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - /* For this particular CPU register boot vector */ - shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); - - return apmu_wrap(cpu, apmu_power_on); -} - -#ifdef CONFIG_HOTPLUG_CPU -/* nicked from arch/arm/mach-exynos/hotplug.c */ -static inline void cpu_enter_lowpower_a15(void) -{ - unsigned int v; - - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); - - flush_cache_louis(); - - asm volatile( - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (0x40) - : "cc"); - - isb(); - dsb(); -} - -void shmobile_smp_apmu_cpu_die(unsigned int cpu) -{ - /* For this particular CPU deregister boot vector */ - shmobile_smp_hook(cpu, 0, 0); - - /* Select next sleep mode using the APMU */ - apmu_wrap(cpu, apmu_power_off); - - /* Do ARM specific CPU shutdown */ - cpu_enter_lowpower_a15(); - - /* jump to shared mach-shmobile sleep / reset code */ - shmobile_smp_sleep(); -} - -int shmobile_smp_apmu_cpu_kill(unsigned int cpu) -{ - return apmu_wrap(cpu, apmu_power_off_poll); -} -#endif diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index 673ad6e..c96f501 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c @@ -7,7 +7,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <linux/cpu.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> @@ -17,26 +16,6 @@ #include <asm/smp_scu.h> #include <mach/common.h> -static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb, - unsigned long action, void *hcpu) -{ - unsigned int cpu = (long)hcpu; - - switch (action) { - case CPU_UP_PREPARE: - /* For this particular CPU register SCU SMP boot vector */ - shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), - (unsigned long)shmobile_scu_base); - break; - }; - - return NOTIFY_OK; -} - -static struct notifier_block shmobile_smp_scu_notifier = { - .notifier_call = shmobile_smp_scu_notifier_call, -}; - void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) { /* install boot code shared by all CPUs */ @@ -46,9 +25,14 @@ void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) /* enable SCU and cache coherency on booting CPU */ scu_enable(shmobile_scu_base); scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); +} - /* Use CPU notifier for reset vector control */ - register_cpu_notifier(&shmobile_smp_scu_notifier); +int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + /* For this particular CPU register SCU boot vector */ + shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), + (unsigned long)shmobile_scu_base); + return 0; } #ifdef CONFIG_HOTPLUG_CPU diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 9ebc246..d4ae616 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -11,10 +11,25 @@ * published by the Free Software Foundation. */ #include <linux/init.h> +#include <linux/smp.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> #include <mach/common.h> +void __init shmobile_smp_init_cpus(unsigned int ncores) +{ + unsigned int i; + + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", + ncores, nr_cpu_ids); + ncores = nr_cpu_ids; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} + extern unsigned long shmobile_smp_fn[]; extern unsigned long shmobile_smp_arg[]; extern unsigned long shmobile_smp_mpidr[]; @@ -29,10 +44,3 @@ void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg) shmobile_smp_arg[cpu] = arg; flush_cache_all(); } - -#ifdef CONFIG_HOTPLUG_CPU -int shmobile_smp_cpu_disable(unsigned int cpu) -{ - return 0; /* Hotplug of any CPU is supported */ -} -#endif diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c deleted file mode 100644 index d4eb509..0000000 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * r7s72100 processor support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/of_platform.h> -#include <linux/serial_sci.h> -#include <mach/common.h> -#include <mach/irqs.h> -#include <mach/r7s72100.h> -#include <asm/mach/arch.h> - -#define SCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - .type = PORT_SCIF, \ - .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scbrr_algo_id = SCBRR_ALGO_2, \ - .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ - SCSCR_REIE, \ - .mapbase = baseaddr, \ - .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ -} - -enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; - -static const struct plat_sci_port scif[] __initconst = { - SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ - SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ - SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ - SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ - SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ - SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ - SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ - SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */ -}; - -static inline void r7s72100_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} - -void __init r7s72100_add_dt_devices(void) -{ - r7s72100_register_scif(SCIF0); - r7s72100_register_scif(SCIF1); - r7s72100_register_scif(SCIF2); - r7s72100_register_scif(SCIF3); - r7s72100_register_scif(SCIF4); - r7s72100_register_scif(SCIF5); - r7s72100_register_scif(SCIF6); - r7s72100_register_scif(SCIF7); -} - -void __init r7s72100_init_early(void) -{ - shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */ -} - -#ifdef CONFIG_USE_OF -static const char *r7s72100_boards_compat_dt[] __initdata = { - "renesas,r7s72100", - NULL, -}; - -DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") - .init_early = r7s72100_init_early, - .dt_compat = r7s72100_boards_compat_dt, -MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index b0f2749..8949170 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -22,10 +22,8 @@ #include <linux/of_platform.h> #include <linux/platform_data/irq-renesas-irqc.h> #include <linux/serial_sci.h> -#include <linux/sh_dma.h> #include <linux/sh_timer.h> #include <mach/common.h> -#include <mach/dma-register.h> #include <mach/irqs.h> #include <mach/r8a73a4.h> #include <asm/mach/arch.h> @@ -201,104 +199,15 @@ void __init r8a73a4_add_dt_devices(void) r8a7790_register_cmt(10); } -/* DMA */ -static const struct sh_dmae_slave_config dma_slaves[] = { - { - .slave_id = SHDMA_SLAVE_MMCIF0_TX, - .addr = 0xee200034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF0_RX, - .addr = 0xee200034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xd2, - }, { - .slave_id = SHDMA_SLAVE_MMCIF1_TX, - .addr = 0xee220034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xe1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF1_RX, - .addr = 0xee220034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xe2, - }, -}; - -#define DMAE_CHANNEL(a, b) \ - { \ - .offset = (a) - 0x20, \ - .dmars = (a) - 0x20 + 0x40, \ - .chclr_bit = (b), \ - .chclr_offset = 0x80 - 0x20, \ - } - -static const struct sh_dmae_channel dma_channels[] = { - DMAE_CHANNEL(0x8000, 0), - DMAE_CHANNEL(0x8080, 1), - DMAE_CHANNEL(0x8100, 2), - DMAE_CHANNEL(0x8180, 3), - DMAE_CHANNEL(0x8200, 4), - DMAE_CHANNEL(0x8280, 5), - DMAE_CHANNEL(0x8300, 6), - DMAE_CHANNEL(0x8380, 7), - DMAE_CHANNEL(0x8400, 8), - DMAE_CHANNEL(0x8480, 9), - DMAE_CHANNEL(0x8500, 10), - DMAE_CHANNEL(0x8580, 11), - DMAE_CHANNEL(0x8600, 12), - DMAE_CHANNEL(0x8680, 13), - DMAE_CHANNEL(0x8700, 14), - DMAE_CHANNEL(0x8780, 15), - DMAE_CHANNEL(0x8800, 16), - DMAE_CHANNEL(0x8880, 17), - DMAE_CHANNEL(0x8900, 18), - DMAE_CHANNEL(0x8980, 19), -}; - -static const struct sh_dmae_pdata dma_pdata = { - .slave = dma_slaves, - .slave_num = ARRAY_SIZE(dma_slaves), - .channel = dma_channels, - .channel_num = ARRAY_SIZE(dma_channels), - .ts_low_shift = TS_LOW_SHIFT, - .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, - .ts_high_shift = TS_HI_SHIFT, - .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, - .ts_shift = dma_ts_shift, - .ts_shift_num = ARRAY_SIZE(dma_ts_shift), - .dmaor_init = DMAOR_DME, - .chclr_present = 1, - .chclr_bitwise = 1, -}; - -static struct resource dma_resources[] = { - DEFINE_RES_MEM(0xe6700020, 0x89e0), - DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), - { - /* IRQ for channels 0-19 */ - .start = gic_spi(200), - .end = gic_spi(219), - .flags = IORESOURCE_IRQ, - }, -}; - -#define r8a73a4_register_dmac() \ - platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \ - dma_resources, ARRAY_SIZE(dma_resources), \ - &dma_pdata, sizeof(dma_pdata)) - void __init r8a73a4_add_standard_devices(void) { r8a73a4_add_dt_devices(); r8a73a4_register_irqc(0); r8a73a4_register_irqc(1); r8a73a4_register_thermal(); - r8a73a4_register_dmac(); } -void __init r8a73a4_init_early(void) +void __init r8a73a4_init_delay(void) { #ifndef CONFIG_ARM_ARCH_TIMER shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */ @@ -313,7 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") - .init_early = r8a73a4_init_early, + .init_early = r8a73a4_init_delay, .dt_compat = r8a73a4_boards_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 03fcc59..6a2657e 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -24,7 +24,6 @@ #include <linux/irqchip/arm-gic.h> #include <linux/of.h> #include <linux/of_platform.h> -#include <linux/platform_data/dma-rcar-hpbdma.h> #include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <linux/platform_device.h> @@ -96,46 +95,29 @@ static struct sh_timer_config sh_tmu1_platform_data __initdata = { &sh_tmu##idx##_platform_data, \ sizeof(sh_tmu##idx##_platform_data)) -int r8a7778_usb_phy_power(bool enable) -{ - static struct usb_phy *phy = NULL; - int ret = 0; - - if (!phy) - phy = usb_get_phy(USB_PHY_TYPE_USB2); - - if (IS_ERR(phy)) { - pr_err("kernel doesn't have usb phy driver\n"); - return PTR_ERR(phy); - } - - if (enable) - ret = usb_phy_init(phy); - else - usb_phy_shutdown(phy); - - return ret; -} - /* USB */ +static struct usb_phy *phy; + static int usb_power_on(struct platform_device *pdev) { - int ret = r8a7778_usb_phy_power(true); - - if (ret) - return ret; + if (IS_ERR(phy)) + return PTR_ERR(phy); pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); + usb_phy_init(phy); + return 0; } static void usb_power_off(struct platform_device *pdev) { - if (r8a7778_usb_phy_power(false)) + if (IS_ERR(phy)) return; + usb_phy_shutdown(phy); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -192,6 +174,20 @@ static struct platform_device_info hci##_info __initdata = { \ USB_PLATFORM_INFO(ehci); USB_PLATFORM_INFO(ohci); +/* Ether */ +static struct resource ether_resources[] __initdata = { + DEFINE_RES_MEM(0xfde00000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x89)), +}; + +void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + pdata, sizeof(*pdata)); +} + /* PFC/GPIO */ static struct resource pfc_resources[] __initdata = { DEFINE_RES_MEM(0xfffc0000, 0x118), @@ -276,7 +272,7 @@ static struct resource hspi_resources[] __initdata = { DEFINE_RES_IRQ(gic_iid(0x75)), }; -static void __init r8a7778_register_hspi(int id) +void __init r8a7778_register_hspi(int id) { BUG_ON(id < 0 || id > 2); @@ -285,6 +281,40 @@ static void __init r8a7778_register_hspi(int id) hspi_resources + (2 * id), 2); } +/* VIN */ +#define R8A7778_VIN(idx) \ +static struct resource vin##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ + DEFINE_RES_IRQ(gic_iid(0x5a)), \ +}; \ + \ +static struct platform_device_info vin##idx##_info __initdata = { \ + .parent = &platform_bus, \ + .name = "r8a7778-vin", \ + .id = idx, \ + .res = vin##idx##_resources, \ + .num_res = ARRAY_SIZE(vin##idx##_resources), \ + .dma_mask = DMA_BIT_MASK(32), \ +} + +R8A7778_VIN(0); +R8A7778_VIN(1); + +static struct platform_device_info *vin_info_table[] __initdata = { + &vin0_info, + &vin1_info, +}; + +void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata) +{ + BUG_ON(id < 0 || id > 1); + + vin_info_table[id]->data = pdata; + vin_info_table[id]->size_data = sizeof(*pdata); + + platform_device_register_full(vin_info_table[id]); +} + void __init r8a7778_add_dt_devices(void) { int i; @@ -309,88 +339,6 @@ void __init r8a7778_add_dt_devices(void) r8a7778_register_tmu(1); } -/* HPB-DMA */ - -/* Asynchronous mode register (ASYNCMDR) bits */ -#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ - -static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { - { - .id = HPBDMA_SLAVE_SDHI0_TX, - .addr = 0xffe4c000 + 0x30, - .dcr = HPB_DMAE_DCR_SPDS_16BIT | - HPB_DMAE_DCR_DMDL | - HPB_DMAE_DCR_DPDS_16BIT, - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | - HPB_DMAE_ASYNCRSTR_ASRST22 | - HPB_DMAE_ASYNCRSTR_ASRST23, - .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, - .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, - .port = 0x0D0C, - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, - .dma_ch = 21, - }, { - .id = HPBDMA_SLAVE_SDHI0_RX, - .addr = 0xffe4c000 + 0x30, - .dcr = HPB_DMAE_DCR_SMDL | - HPB_DMAE_DCR_SPDS_16BIT | - HPB_DMAE_DCR_DPDS_16BIT, - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | - HPB_DMAE_ASYNCRSTR_ASRST22 | - HPB_DMAE_ASYNCRSTR_ASRST23, - .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, - .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, - .port = 0x0D0C, - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, - .dma_ch = 22, - }, -}; - -static const struct hpb_dmae_channel hpb_dmae_channels[] = { - HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ - HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ -}; - -static struct hpb_dmae_pdata dma_platform_data __initdata = { - .slaves = hpb_dmae_slaves, - .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), - .channels = hpb_dmae_channels, - .num_channels = ARRAY_SIZE(hpb_dmae_channels), - .ts_shift = { - [XMIT_SZ_8BIT] = 0, - [XMIT_SZ_16BIT] = 1, - [XMIT_SZ_32BIT] = 2, - }, - .num_hw_channels = 39, -}; - -static struct resource hpb_dmae_resources[] __initdata = { - /* Channel registers */ - DEFINE_RES_MEM(0xffc08000, 0x1000), - /* Common registers */ - DEFINE_RES_MEM(0xffc09000, 0x170), - /* Asynchronous reset registers */ - DEFINE_RES_MEM(0xffc00300, 4), - /* Asynchronous mode registers */ - DEFINE_RES_MEM(0xffc00400, 4), - /* IRQ for DMA channels */ - DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), -}; - -static void __init r8a7778_register_hpb_dmae(void) -{ - platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, - hpb_dmae_resources, - ARRAY_SIZE(hpb_dmae_resources), - &dma_platform_data, - sizeof(dma_platform_data)); -} - void __init r8a7778_add_standard_devices(void) { r8a7778_add_dt_devices(); @@ -401,12 +349,12 @@ void __init r8a7778_add_standard_devices(void) r8a7778_register_hspi(0); r8a7778_register_hspi(1); r8a7778_register_hspi(2); - - r8a7778_register_hpb_dmae(); } void __init r8a7778_init_late(void) { + phy = usb_get_phy(USB_PHY_TYPE_USB2); + platform_device_register_full(&ehci_info); platform_device_register_full(&ohci_info); } @@ -428,7 +376,7 @@ static struct resource irqpin_resources[] __initdata = { DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ }; -void __init r8a7778_init_irq_extpin_dt(int irlm) +void __init r8a7778_init_irq_extpin(int irlm) { void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); unsigned long tmp; @@ -446,11 +394,7 @@ void __init r8a7778_init_irq_extpin_dt(int irlm) tmp |= (1 << 21); /* LVLMODE = 1 */ iowrite32(tmp, icr0); iounmap(icr0); -} -void __init r8a7778_init_irq_extpin(int irlm) -{ - r8a7778_init_irq_extpin_dt(irlm); if (irlm) platform_device_register_resndata( &platform_bus, "renesas_intc_irqpin", -1, diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 13049e9..ecd0148 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -25,7 +25,6 @@ #include <linux/irqchip.h> #include <linux/irqchip/arm-gic.h> #include <linux/of_platform.h> -#include <linux/platform_data/dma-rcar-hpbdma.h> #include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <linux/platform_device.h> @@ -98,7 +97,7 @@ static struct resource irqpin0_resources[] __initdata = { DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ }; -void __init r8a7779_init_irq_extpin_dt(int irlm) +void __init r8a7779_init_irq_extpin(int irlm) { void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); u32 tmp; @@ -116,11 +115,7 @@ void __init r8a7779_init_irq_extpin_dt(int irlm) tmp |= (1 << 21); /* LVLMODE = 1 */ iowrite32(tmp, icr0); iounmap(icr0); -} -void __init r8a7779_init_irq_extpin(int irlm) -{ - r8a7779_init_irq_extpin_dt(irlm); if (irlm) platform_device_register_resndata( &platform_bus, "renesas_intc_irqpin", -1, @@ -637,158 +632,6 @@ static struct platform_device_info *vin_info_table[] __initdata = { &vin3_info, }; -/* HPB-DMA */ - -/* Asynchronous mode register bits */ -#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ -#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ -#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ -#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ -#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ -#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ -#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ - -static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { - { - .id = HPBDMA_SLAVE_SDHI0_TX, - .addr = 0xffe4c000 + 0x30, - .dcr = HPB_DMAE_DCR_SPDS_16BIT | - HPB_DMAE_DCR_DMDL | - HPB_DMAE_DCR_DPDS_16BIT, - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | - HPB_DMAE_ASYNCRSTR_ASRST22 | - HPB_DMAE_ASYNCRSTR_ASRST23, - .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | - HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, - .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | - HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, - .port = 0x0D0C, - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, - .dma_ch = 21, - }, { - .id = HPBDMA_SLAVE_SDHI0_RX, - .addr = 0xffe4c000 + 0x30, - .dcr = HPB_DMAE_DCR_SMDL | - HPB_DMAE_DCR_SPDS_16BIT | - HPB_DMAE_DCR_DPDS_16BIT, - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | - HPB_DMAE_ASYNCRSTR_ASRST22 | - HPB_DMAE_ASYNCRSTR_ASRST23, - .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | - HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, - .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | - HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, - .port = 0x0D0C, - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, - .dma_ch = 22, - }, -}; - -static const struct hpb_dmae_channel hpb_dmae_channels[] = { - HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ - HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ -}; - -static struct hpb_dmae_pdata dma_platform_data __initdata = { - .slaves = hpb_dmae_slaves, - .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), - .channels = hpb_dmae_channels, - .num_channels = ARRAY_SIZE(hpb_dmae_channels), - .ts_shift = { - [XMIT_SZ_8BIT] = 0, - [XMIT_SZ_16BIT] = 1, - [XMIT_SZ_32BIT] = 2, - }, - .num_hw_channels = 44, -}; - -static struct resource hpb_dmae_resources[] __initdata = { - /* Channel registers */ - DEFINE_RES_MEM(0xffc08000, 0x1000), - /* Common registers */ - DEFINE_RES_MEM(0xffc09000, 0x170), - /* Asynchronous reset registers */ - DEFINE_RES_MEM(0xffc00300, 4), - /* Asynchronous mode registers */ - DEFINE_RES_MEM(0xffc00400, 4), - /* IRQ for DMA channels */ - DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), -}; - -static void __init r8a7779_register_hpb_dmae(void) -{ - platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, - hpb_dmae_resources, - ARRAY_SIZE(hpb_dmae_resources), - &dma_platform_data, - sizeof(dma_platform_data)); -} - static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -822,7 +665,6 @@ void __init r8a7779_add_standard_devices(void) ARRAY_SIZE(r8a7779_devices_dt)); platform_add_devices(r8a7779_standard_devices, ARRAY_SIZE(r8a7779_standard_devices)); - r8a7779_register_hpb_dmae(); } void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c47bceb..d0f5c9f 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/clocksource.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/of_platform.h> @@ -30,18 +31,17 @@ #include <mach/r8a7790.h> #include <asm/mach/arch.h> -static const struct resource pfc_resources[] __initconst = { +static struct resource pfc_resources[] __initdata = { DEFINE_RES_MEM(0xe6060000, 0x250), }; #define R8A7790_GPIO(idx) \ -static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ +static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \ DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ }; \ \ -static const struct gpio_rcar_config \ -r8a7790_gpio##idx##_platform_data __initconst = { \ +static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \ .gpio_base = 32 * (idx), \ .irq_base = 0, \ .number_of_pins = 32, \ @@ -112,7 +112,7 @@ void __init r8a7790_pinmux_init(void) enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, HSCIF0, HSCIF1 }; -static const struct plat_sci_port scif[] __initconst = { +static struct plat_sci_port scif[] __initdata = { SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ @@ -131,11 +131,11 @@ static inline void r8a7790_register_scif(int idx) sizeof(struct plat_sci_port)); } -static const struct renesas_irqc_config irqc0_data __initconst = { +static struct renesas_irqc_config irqc0_data __initdata = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ }; -static const struct resource irqc0_resources[] __initconst = { +static struct resource irqc0_resources[] __initdata = { DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ @@ -150,7 +150,7 @@ static const struct resource irqc0_resources[] __initconst = { &irqc##idx##_data, \ sizeof(struct renesas_irqc_config)) -static const struct resource thermal_resources[] __initconst = { +static struct resource thermal_resources[] __initdata = { DEFINE_RES_MEM(0xe61f0000, 0x14), DEFINE_RES_MEM(0xe61f0100, 0x38), DEFINE_RES_IRQ(gic_spi(69)), @@ -161,13 +161,13 @@ static const struct resource thermal_resources[] __initconst = { thermal_resources, \ ARRAY_SIZE(thermal_resources)) -static const struct sh_timer_config cmt00_platform_data __initconst = { +static struct sh_timer_config cmt00_platform_data __initdata = { .name = "CMT00", .timer_bit = 0, .clockevent_rating = 80, }; -static const struct resource cmt00_resources[] __initconst = { +static struct resource cmt00_resources[] __initdata = { DEFINE_RES_MEM(0xffca0510, 0x0c), DEFINE_RES_MEM(0xffca0500, 0x04), DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ @@ -202,7 +202,72 @@ void __init r8a7790_add_standard_devices(void) r8a7790_register_thermal(); } -void __init r8a7790_init_early(void) +#define MODEMR 0xe6160060 + +u32 __init r8a7790_read_mode_pins(void) +{ + void __iomem *modemr = ioremap_nocache(MODEMR, 4); + u32 mode; + + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + return mode; +} + +#define CNTCR 0 +#define CNTFID0 0x20 + +void __init r8a7790_timer_init(void) +{ +#ifdef CONFIG_ARM_ARCH_TIMER + u32 mode = r8a7790_read_mode_pins(); + void __iomem *base; + int extal_mhz = 0; + u32 freq; + + /* At Linux boot time the r8a7790 arch timer comes up + * with the counter disabled. Moreover, it may also report + * a potentially incorrect fixed 13 MHz frequency. To be + * correct these registers need to be updated to use the + * frequency EXTAL / 2 which can be determined by the MD pins. + */ + + switch (mode & (MD(14) | MD(13))) { + case 0: + extal_mhz = 15; + break; + case MD(13): + extal_mhz = 20; + break; + case MD(14): + extal_mhz = 26; + break; + case MD(13) | MD(14): + extal_mhz = 30; + break; + } + + /* The arch timer frequency equals EXTAL / 2 */ + freq = extal_mhz * (1000000 / 2); + + /* Remap "armgcnt address map" space */ + base = ioremap(0xe6080000, PAGE_SIZE); + + /* Update registers with correct frequency */ + iowrite32(freq, base + CNTFID0); + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + /* make sure arch timer is started by setting bit 0 of CNTCR */ + iowrite32(1, base + CNTCR); + iounmap(base); +#endif /* CONFIG_ARM_ARCH_TIMER */ + + clocksource_of_init(); +} + +void __init r8a7790_init_delay(void) { #ifndef CONFIG_ARM_ARCH_TIMER shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ @@ -211,15 +276,14 @@ void __init r8a7790_init_early(void) #ifdef CONFIG_USE_OF -static const char * const r8a7790_boards_compat_dt[] __initconst = { +static const char *r8a7790_boards_compat_dt[] __initdata = { "renesas,r8a7790", NULL, }; DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") - .smp = smp_ops(r8a7790_smp_ops), - .init_early = r8a7790_init_early, - .init_time = rcar_gen2_timer_init, + .init_early = r8a7790_init_delay, + .init_time = r8a7790_timer_init, .dt_compat = r8a7790_boards_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c deleted file mode 100644 index d9393d6..0000000 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * r8a7791 processor support - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/of_platform.h> -#include <linux/platform_data/irq-renesas-irqc.h> -#include <linux/serial_sci.h> -#include <linux/sh_timer.h> -#include <mach/common.h> -#include <mach/irqs.h> -#include <mach/r8a7791.h> -#include <mach/rcar-gen2.h> -#include <asm/mach/arch.h> - -#define SCIF_COMMON(scif_type, baseaddr, irq) \ - .type = scif_type, \ - .mapbase = baseaddr, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .irqs = SCIx_IRQ_MUXED(irq) - -#define SCIFA_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define SCIFB_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define SCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_2, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define HSCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_6, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, - SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; - -static const struct plat_sci_port scif[] __initconst = { - SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ - SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ - SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ - SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ - SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ - SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ - SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ - SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ - SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ - SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ - SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ - SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ - SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ - SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ - SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ -}; - -static inline void r8a7791_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} - -static const struct sh_timer_config cmt00_platform_data __initconst = { - .name = "CMT00", - .timer_bit = 0, - .clockevent_rating = 80, -}; - -static const struct resource cmt00_resources[] __initconst = { - DEFINE_RES_MEM(0xffca0510, 0x0c), - DEFINE_RES_MEM(0xffca0500, 0x04), - DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */ -}; - -#define r8a7791_register_cmt(idx) \ - platform_device_register_resndata(&platform_bus, "sh_cmt", \ - idx, cmt##idx##_resources, \ - ARRAY_SIZE(cmt##idx##_resources), \ - &cmt##idx##_platform_data, \ - sizeof(struct sh_timer_config)) - -static struct renesas_irqc_config irqc0_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */ -}; - -static struct resource irqc0_resources[] = { - DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ - DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */ - DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */ -}; - -#define r8a7791_register_irqc(idx) \ - platform_device_register_resndata(&platform_bus, "renesas_irqc", \ - idx, irqc##idx##_resources, \ - ARRAY_SIZE(irqc##idx##_resources), \ - &irqc##idx##_data, \ - sizeof(struct renesas_irqc_config)) - -void __init r8a7791_add_dt_devices(void) -{ - r8a7791_register_scif(SCIFA0); - r8a7791_register_scif(SCIFA1); - r8a7791_register_scif(SCIFB0); - r8a7791_register_scif(SCIFB1); - r8a7791_register_scif(SCIFB2); - r8a7791_register_scif(SCIFA2); - r8a7791_register_scif(SCIF0); - r8a7791_register_scif(SCIF1); - r8a7791_register_scif(SCIF2); - r8a7791_register_scif(SCIF3); - r8a7791_register_scif(SCIF4); - r8a7791_register_scif(SCIF5); - r8a7791_register_scif(SCIFA3); - r8a7791_register_scif(SCIFA4); - r8a7791_register_scif(SCIFA5); - r8a7791_register_cmt(00); -} - -void __init r8a7791_add_standard_devices(void) -{ - r8a7791_add_dt_devices(); - r8a7791_register_irqc(0); -} - -void __init r8a7791_init_early(void) -{ -#ifndef CONFIG_ARM_ARCH_TIMER - shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ -#endif -} - -#ifdef CONFIG_USE_OF -static const char *r8a7791_boards_compat_dt[] __initdata = { - "renesas,r8a7791", - NULL, -}; - -DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)") - .smp = smp_ops(r8a7791_smp_ops), - .init_early = r8a7791_init_early, - .init_time = rcar_gen2_timer_init, - .dt_compat = r8a7791_boards_compat_dt, -MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c deleted file mode 100644 index 5734c24..0000000 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * R-Car Generation 2 support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <linux/clocksource.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <mach/common.h> -#include <mach/rcar-gen2.h> -#include <asm/mach/arch.h> - -#define MODEMR 0xe6160060 - -u32 __init rcar_gen2_read_mode_pins(void) -{ - void __iomem *modemr = ioremap_nocache(MODEMR, 4); - u32 mode; - - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); - - return mode; -} - -#define CNTCR 0 -#define CNTFID0 0x20 - -void __init rcar_gen2_timer_init(void) -{ -#ifdef CONFIG_ARM_ARCH_TIMER - u32 mode = rcar_gen2_read_mode_pins(); - void __iomem *base; - int extal_mhz = 0; - u32 freq; - - /* At Linux boot time the r8a7790 arch timer comes up - * with the counter disabled. Moreover, it may also report - * a potentially incorrect fixed 13 MHz frequency. To be - * correct these registers need to be updated to use the - * frequency EXTAL / 2 which can be determined by the MD pins. - */ - - switch (mode & (MD(14) | MD(13))) { - case 0: - extal_mhz = 15; - break; - case MD(13): - extal_mhz = 20; - break; - case MD(14): - extal_mhz = 26; - break; - case MD(13) | MD(14): - extal_mhz = 30; - break; - } - - /* The arch timer frequency equals EXTAL / 2 */ - freq = extal_mhz * (1000000 / 2); - - /* Remap "armgcnt address map" space */ - base = ioremap(0xe6080000, PAGE_SIZE); - - /* Update registers with correct frequency */ - iowrite32(freq, base + CNTFID0); - asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); - - /* make sure arch timer is started by setting bit 0 of CNTCR */ - iowrite32(1, base + CNTCR); - iounmap(base); -#endif /* CONFIG_ARM_ARCH_TIMER */ - - clocksource_of_init(); -} diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index f2ca923..522de5e 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -34,6 +34,12 @@ static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { + int ret; + + ret = shmobile_smp_scu_boot_secondary(cpu, idle); + if (ret) + return ret; + arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); return 0; } diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 627c1f0..0f05e9f 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -87,6 +87,10 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) unsigned int lcpu = cpu_logical_map(cpu); int ret; + ret = shmobile_smp_scu_boot_secondary(cpu, idle); + if (ret) + return ret; + if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[lcpu]; diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c deleted file mode 100644 index 015e275..0000000 --- a/arch/arm/mach-shmobile/smp-r8a7790.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * SMP support for r8a7790 - * - * Copyright (C) 2012-2013 Renesas Solutions Corp. - * Copyright (C) 2012 Takashi Yoshii <takashi.yoshii.ze@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/io.h> -#include <asm/smp_plat.h> -#include <mach/common.h> - -#define RST 0xe6160000 -#define CA15BAR 0x0020 -#define CA7BAR 0x0030 -#define CA15RESCNT 0x0040 -#define CA7RESCNT 0x0044 -#define MERAM 0xe8080000 - -static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus) -{ - void __iomem *p; - u32 bar; - - /* let APMU code install data related to shmobile_boot_vector */ - shmobile_smp_apmu_prepare_cpus(max_cpus); - - /* MERAM for jump stub, because BAR requires 256KB aligned address */ - p = ioremap_nocache(MERAM, shmobile_boot_size); - memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); - iounmap(p); - - /* setup reset vectors */ - p = ioremap_nocache(RST, 0x63); - bar = (MERAM >> 8) & 0xfffffc00; - writel_relaxed(bar, p + CA15BAR); - writel_relaxed(bar, p + CA7BAR); - writel_relaxed(bar | 0x10, p + CA15BAR); - writel_relaxed(bar | 0x10, p + CA7BAR); - - /* enable clocks to all CPUs */ - writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000, - p + CA15RESCNT); - writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000, - p + CA7RESCNT); - iounmap(p); -} - -struct smp_operations r8a7790_smp_ops __initdata = { - .smp_prepare_cpus = r8a7790_smp_prepare_cpus, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = shmobile_smp_cpu_disable, - .cpu_die = shmobile_smp_apmu_cpu_die, - .cpu_kill = shmobile_smp_apmu_cpu_kill, -#endif -}; diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c deleted file mode 100644 index 2df5bd1..0000000 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * SMP support for r8a7791 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/io.h> -#include <asm/smp_plat.h> -#include <mach/common.h> -#include <mach/r8a7791.h> - -#define RST 0xe6160000 -#define CA15BAR 0x0020 -#define CA15RESCNT 0x0040 -#define RAM 0xe6300000 - -static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) -{ - void __iomem *p; - u32 bar; - - /* let APMU code install data related to shmobile_boot_vector */ - shmobile_smp_apmu_prepare_cpus(max_cpus); - - /* RAM for jump stub, because BAR requires 256KB aligned address */ - p = ioremap_nocache(RAM, shmobile_boot_size); - memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); - iounmap(p); - - /* setup reset vectors */ - p = ioremap_nocache(RST, 0x63); - bar = (RAM >> 8) & 0xfffffc00; - writel_relaxed(bar, p + CA15BAR); - writel_relaxed(bar | 0x10, p + CA15BAR); - - /* enable clocks to all CPUs */ - writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000, - p + CA15RESCNT); - iounmap(p); -} - -struct smp_operations r8a7791_smp_ops __initdata = { - .smp_prepare_cpus = r8a7791_smp_prepare_cpus, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = shmobile_smp_cpu_disable, - .cpu_die = shmobile_smp_apmu_cpu_die, - .cpu_kill = shmobile_smp_apmu_cpu_kill, -#endif -}; diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 13ba36a..0baa244 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -46,6 +46,11 @@ void __init sh73a0_register_twd(void) static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned int lcpu = cpu_logical_map(cpu); + int ret; + + ret = shmobile_smp_scu_boot_secondary(cpu, idle); + if (ret) + return ret; if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) __raw_writel(1 << lcpu, WUPCR); /* wake up */ @@ -66,11 +71,18 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) shmobile_smp_scu_prepare_cpus(max_cpus); } +#ifdef CONFIG_HOTPLUG_CPU +static int sh73a0_cpu_disable(unsigned int cpu) +{ + return 0; /* CPU0 and CPU1 supported */ +} +#endif /* CONFIG_HOTPLUG_CPU */ + struct smp_operations sh73a0_smp_ops __initdata = { .smp_prepare_cpus = sh73a0_smp_prepare_cpus, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = shmobile_smp_cpu_disable, + .cpu_disable = sh73a0_cpu_disable, .cpu_die = shmobile_smp_scu_cpu_die, .cpu_kill = shmobile_smp_scu_cpu_kill, #endif diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index aee77f0..dd86db4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -4,13 +4,13 @@ config ARCH_SOCFPGA select ARM_AMBA select ARM_GIC select CACHE_L2X0 + select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select GPIO_PL061 if GPIOLIB select HAVE_ARM_SCU - select HAVE_ARM_TWD if SMP select HAVE_SMP select MFD_SYSCON select SPARSE_IRQ diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index dd0d49c..bfce964 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -14,6 +14,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ +#include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_irq.h> @@ -106,6 +107,7 @@ static void __init socfpga_cyclone5_init(void) { l2x0_of_init(0, ~0UL); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_clk_init(NULL); socfpga_init_clocks(); } diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig index ac1710e6..df0d59a 100644 --- a/arch/arm/mach-spear/Kconfig +++ b/arch/arm/mach-spear/Kconfig @@ -7,9 +7,11 @@ menuconfig PLAT_SPEAR default PLAT_SPEAR_SINGLE select ARCH_REQUIRE_GPIOLIB select ARM_AMBA + select CLKDEV_LOOKUP select CLKSRC_MMIO select COMMON_CLK select GENERIC_CLOCKEVENTS + select HAVE_CLK if PLAT_SPEAR diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index d71654b..835833e 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -12,7 +12,7 @@ menuconfig ARCH_STI select HAVE_ARM_SCU if SMP select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_764369 select ARM_ERRATA_775420 select PL310_ERRATA_753970 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_PL310 @@ -30,7 +30,7 @@ config SOC_STIH415 default y help This enables support for STMicroelectronics Digital Consumer - Electronics family StiH415 parts, primarily targeted at set-top-box + Electronics family StiH415 parts, primarily targetted at set-top-box and other digital audio/video applications using Flattned Device Trees. @@ -39,7 +39,7 @@ config SOC_STIH416 default y help This enables support for STMicroelectronics Digital Consumer - Electronics family StiH416 parts, primarily targeted at set-top-box + Electronics family StiH416 parts, primarily targetted at set-top-box and other digital audio/video applications using Flattened Device Trees. diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c index 1217fb5..8fe6f0c 100644 --- a/arch/arm/mach-sti/board-dt.c +++ b/arch/arm/mach-sti/board-dt.c @@ -7,8 +7,9 @@ * published by the Free Software Foundation. */ +#include <linux/clk-provider.h> +#include <linux/clocksource.h> #include <linux/irq.h> -#include <linux/of_platform.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> @@ -27,10 +28,11 @@ void __init stih41x_l2x0_init(void) l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); } -static void __init stih41x_machine_init(void) +static void __init stih41x_timer_init(void) { + of_clk_init(NULL); + clocksource_of_init(); stih41x_l2x0_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *stih41x_dt_match[] __initdata = { @@ -40,7 +42,7 @@ static const char *stih41x_dt_match[] __initdata = { }; DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree") - .init_machine = stih41x_machine_init, + .init_time = stih41x_timer_init, .smp = smp_ops(sti_smp_ops), .dt_compat = stih41x_dt_match, MACHINE_END diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index c9e72c8..3ab2f65 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,14 +1,14 @@ config ARCH_SUNXI bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB - select ARM_GIC select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP - select HAVE_SMP select PINCTRL - select PINCTRL_SUNXI select SPARSE_IRQ select SUN4I_TIMER + select PINCTRL_SUNXI + select ARM_GIC + select HAVE_SMP diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 61d3a38..e79fb34 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -10,6 +10,7 @@ * warranty of any kind, whether express or implied. */ +#include <linux/clocksource.h> #include <linux/delay.h> #include <linux/kernel.h> #include <linux/init.h> @@ -19,6 +20,8 @@ #include <linux/io.h> #include <linux/reboot.h> +#include <linux/clk/sunxi.h> + #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> @@ -90,13 +93,14 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd) } static struct of_device_id sunxi_restart_ids[] = { - { .compatible = "allwinner,sun4i-wdt" }, - { .compatible = "allwinner,sun6i-wdt" }, + { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, + { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart }, { /*sentinel*/ } }; static void sunxi_setup_restart(void) { + const struct of_device_id *of_id; struct device_node *np; np = of_find_matching_node(NULL, sunxi_restart_ids); @@ -105,6 +109,17 @@ static void sunxi_setup_restart(void) wdt_base = of_iomap(np, 0); WARN(!wdt_base, "failed to map watchdog base address"); + + of_id = of_match_node(sunxi_restart_ids, np); + WARN(!of_id, "restart function not available"); + + arm_pm_restart = of_id->data; +} + +static void __init sunxi_timer_init(void) +{ + sunxi_init_clocks(); + clocksource_of_init(); } static void __init sunxi_dt_init(void) @@ -118,33 +133,13 @@ static const char * const sunxi_board_dt_compat[] = { "allwinner,sun4i-a10", "allwinner,sun5i-a10s", "allwinner,sun5i-a13", - NULL, -}; - -DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") - .init_machine = sunxi_dt_init, - .dt_compat = sunxi_board_dt_compat, - .restart = sun4i_restart, -MACHINE_END - -static const char * const sun6i_board_dt_compat[] = { "allwinner,sun6i-a31", - NULL, -}; - -DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") - .init_machine = sunxi_dt_init, - .dt_compat = sun6i_board_dt_compat, - .restart = sun6i_restart, -MACHINE_END - -static const char * const sun7i_board_dt_compat[] = { "allwinner,sun7i-a20", NULL, }; -DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") +DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") .init_machine = sunxi_dt_init, - .dt_compat = sun7i_board_dt_compat, - .restart = sun4i_restart, + .init_time = sunxi_timer_init, + .dt_compat = sunxi_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f..67a76f2 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -3,6 +3,7 @@ config ARCH_TEGRA select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_GIC + select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK @@ -10,6 +11,7 @@ config ARCH_TEGRA select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI @@ -51,22 +53,14 @@ config ARCH_TEGRA_3x_SOC config ARCH_TEGRA_114_SOC bool "Enable support for Tegra114 family" - select ARM_ERRATA_798181 if SMP - select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER + select ARM_ERRATA_798181 + select ARM_L1_CACHE_SHIFT_6 select PINCTRL_TEGRA114 help Support for NVIDIA Tegra T114 processor family, based on the ARM CortexA15MP CPU -config ARCH_TEGRA_124_SOC - bool "Enable support for Tegra124 family" - select ARM_L1_CACHE_SHIFT_6 - select HAVE_ARM_ARCH_TIMER - help - Support for NVIDIA Tegra T124 processor family, based on the - ARM CortexA15MP CPU - config TEGRA_AHB bool "Enable AHB driver for NVIDIA Tegra SoCs" default y diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 019bb17..e7e5f45 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,5 +1,6 @@ asflags-y += -march=armv7-a +obj-y += common.o obj-y += io.o obj-y += irq.o obj-y += fuse.o @@ -35,10 +36,5 @@ obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o endif -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o -ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o -endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index bc47197..d7aa52e 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c @@ -114,7 +114,7 @@ static int do_dma_transfer(unsigned long apb_add, dma_desc->callback = apb_dma_complete; dma_desc->callback_param = NULL; - reinit_completion(&tegra_apb_wait); + INIT_COMPLETION(tegra_apb_wait); dmaengine_submit(dma_desc); dma_async_issue_pending(tegra_apb_dma_chan); diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 06f0240..740e16f 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -20,11 +20,12 @@ #include <linux/platform_device.h> #include <linux/rfkill-gpio.h> #include "board.h" +#include "board-paz00.h" static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { .name = "wifi_rfkill", - .reset_gpio = 25, /* PD1 */ - .shutdown_gpio = 85, /* PK5 */ + .reset_gpio = TEGRA_WIFI_RST, + .shutdown_gpio = TEGRA_WIFI_PWRN, .type = RFKILL_TYPE_WLAN, }; diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h new file mode 100644 index 0000000..25c08ec --- /dev/null +++ b/arch/arm/mach-tegra/board-paz00.h @@ -0,0 +1,25 @@ +/* + * arch/arm/mach-tegra/board-paz00.h + * + * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_PAZ00_H +#define _MACH_TEGRA_BOARD_PAZ00_H + +#include "gpio-names.h" + +#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5 +#define TEGRA_WIFI_RST TEGRA_GPIO_PD1 + +#endif diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index bcf5dbf..db6810d 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -25,8 +25,20 @@ #include <linux/types.h> #include <linux/reboot.h> +void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd); + +void __init tegra_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); +void __init tegra_dt_init_irq(void); + +void tegra_init_late(void); + +#ifdef CONFIG_DEBUG_FS +int tegra_clk_debugfs_init(void); +#else +static inline int tegra_clk_debugfs_init(void) { return 0; } +#endif int __init tegra_powergate_init(void); #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c new file mode 100644 index 0000000..94a119a --- /dev/null +++ b/arch/arm/mach-tegra/common.c @@ -0,0 +1,115 @@ +/* + * arch/arm/mach-tegra/common.c + * + * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/reboot.h> +#include <linux/irqchip.h> +#include <linux/clk-provider.h> + +#include <asm/hardware/cache-l2x0.h> + +#include "board.h" +#include "common.h" +#include "cpuidle.h" +#include "fuse.h" +#include "iomap.h" +#include "irq.h" +#include "pmc.h" +#include "apbio.h" +#include "sleep.h" +#include "pm.h" +#include "reset.h" + +/* + * Storage for debug-macro.S's state. + * + * This must be in .data not .bss so that it gets initialized each time the + * kernel is loaded. The data is declared here rather than debug-macro.S so + * that multiple inclusions of debug-macro.S point at the same data. + */ +u32 tegra_uart_config[4] = { + /* Debug UART initialization required */ + 1, + /* Debug UART physical address */ + 0, + /* Debug UART virtual address */ + 0, + /* Scratch space for debug macro */ + 0, +}; + +#ifdef CONFIG_OF +void __init tegra_dt_init_irq(void) +{ + of_clk_init(NULL); + tegra_pmc_init(); + tegra_init_irq(); + irqchip_init(); + tegra_legacy_irq_syscore_init(); +} +#endif + +void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd) +{ + void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); + u32 reg; + + reg = readl_relaxed(reset); + reg |= 0x10; + writel_relaxed(reg, reset); +} + +static void __init tegra_init_cache(void) +{ +#ifdef CONFIG_CACHE_L2X0 + int ret; + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + u32 aux_ctrl, cache_type; + + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x7C400001; + + ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); + if (!ret) + l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); +#endif + +} + +void __init tegra_init_early(void) +{ + tegra_cpu_reset_handler_init(); + tegra_apb_io_init(); + tegra_init_fuse(); + tegra_init_cache(); + tegra_powergate_init(); + tegra_hotplug_init(); +} + +void __init tegra_init_late(void) +{ + tegra_init_suspend(); + tegra_cpuidle_init(); + tegra_powergate_debugfs_init(); +} diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 7bc5d8d..0961dfc 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -39,9 +39,7 @@ void __init tegra_cpuidle_init(void) tegra30_cpuidle_init(); break; case TEGRA114: - case TEGRA124: - if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) tegra114_cpuidle_init(); break; } diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index ce8ab8a..5348543 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -87,7 +87,6 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) break; case TEGRA30: case TEGRA114: - case TEGRA124: /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ @@ -126,7 +125,6 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) break; case TEGRA30: case TEGRA114: - case TEGRA124: /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 9a4e910..e035cd2 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -21,26 +21,14 @@ #include <linux/kernel.h> #include <linux/io.h> #include <linux/export.h> -#include <linux/random.h> #include <linux/tegra-soc.h> #include "fuse.h" #include "iomap.h" #include "apbio.h" -/* Tegra20 only */ #define FUSE_UID_LOW 0x108 #define FUSE_UID_HIGH 0x10c - -/* Tegra30 and later */ -#define FUSE_VENDOR_CODE 0x200 -#define FUSE_FAB_CODE 0x204 -#define FUSE_LOT_CODE_0 0x208 -#define FUSE_LOT_CODE_1 0x20c -#define FUSE_WAFER_ID 0x210 -#define FUSE_X_COORDINATE 0x214 -#define FUSE_Y_COORDINATE 0x218 - #define FUSE_SKU_INFO 0x110 #define TEGRA20_FUSE_SPARE_BIT 0x200 @@ -124,51 +112,21 @@ u32 tegra_read_chipid(void) return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); } -static void __init tegra20_fuse_init_randomness(void) -{ - u32 randomness[2]; - - randomness[0] = tegra_fuse_readl(FUSE_UID_LOW); - randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH); - - add_device_randomness(randomness, sizeof(randomness)); -} - -/* Applies to Tegra30 or later */ -static void __init tegra30_fuse_init_randomness(void) -{ - u32 randomness[7]; - - randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE); - randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE); - randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0); - randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1); - randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID); - randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE); - randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE); - - add_device_randomness(randomness, sizeof(randomness)); -} - -void __init tegra_init_fuse(void) +void tegra_init_fuse(void) { u32 id; - u32 randomness[5]; u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); reg |= 1 << 28; writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); reg = tegra_fuse_readl(FUSE_SKU_INFO); - randomness[0] = reg; tegra_sku_id = reg & 0xFF; reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); - randomness[1] = reg; tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; id = tegra_read_chipid(); - randomness[2] = id; tegra_chip_id = (id >> 8) & 0xff; switch (tegra_chip_id) { @@ -191,21 +149,19 @@ void __init tegra_init_fuse(void) tegra_revision = tegra_get_revision(id); tegra_init_speedo_data(); - randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id; - randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id; - - add_device_randomness(randomness, sizeof(randomness)); - switch (tegra_chip_id) { - case TEGRA20: - tegra20_fuse_init_randomness(); - case TEGRA30: - case TEGRA114: - default: - tegra30_fuse_init_randomness(); - } pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", tegra_revision_name[tegra_revision], tegra_sku_id, tegra_cpu_process_id, tegra_core_process_id); } + +unsigned long long tegra_chip_uid(void) +{ + unsigned long long lo, hi; + + lo = tegra_fuse_readl(FUSE_UID_LOW); + hi = tegra_fuse_readl(FUSE_UID_HIGH); + return (hi << 32ull) | lo; +} +EXPORT_SYMBOL(tegra_chip_uid); diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index c01d047..def7968 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -29,7 +29,6 @@ #define TEGRA20 0x20 #define TEGRA30 0x30 #define TEGRA114 0x35 -#define TEGRA124 0x40 #ifndef __ASSEMBLY__ enum tegra_revision { diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h new file mode 100644 index 0000000..f28220a --- /dev/null +++ b/arch/arm/mach-tegra/gpio-names.h @@ -0,0 +1,247 @@ +/* + * arch/arm/mach-tegra/include/mach/gpio-names.h + * + * Copyright (c) 2010 Google, Inc + * + * Author: + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TEGRA_GPIO_NAMES_H +#define __MACH_TEGRA_GPIO_NAMES_H + +#define TEGRA_GPIO_PA0 0 +#define TEGRA_GPIO_PA1 1 +#define TEGRA_GPIO_PA2 2 +#define TEGRA_GPIO_PA3 3 +#define TEGRA_GPIO_PA4 4 +#define TEGRA_GPIO_PA5 5 +#define TEGRA_GPIO_PA6 6 +#define TEGRA_GPIO_PA7 7 +#define TEGRA_GPIO_PB0 8 +#define TEGRA_GPIO_PB1 9 +#define TEGRA_GPIO_PB2 10 +#define TEGRA_GPIO_PB3 11 +#define TEGRA_GPIO_PB4 12 +#define TEGRA_GPIO_PB5 13 +#define TEGRA_GPIO_PB6 14 +#define TEGRA_GPIO_PB7 15 +#define TEGRA_GPIO_PC0 16 +#define TEGRA_GPIO_PC1 17 +#define TEGRA_GPIO_PC2 18 +#define TEGRA_GPIO_PC3 19 +#define TEGRA_GPIO_PC4 20 +#define TEGRA_GPIO_PC5 21 +#define TEGRA_GPIO_PC6 22 +#define TEGRA_GPIO_PC7 23 +#define TEGRA_GPIO_PD0 24 +#define TEGRA_GPIO_PD1 25 +#define TEGRA_GPIO_PD2 26 +#define TEGRA_GPIO_PD3 27 +#define TEGRA_GPIO_PD4 28 +#define TEGRA_GPIO_PD5 29 +#define TEGRA_GPIO_PD6 30 +#define TEGRA_GPIO_PD7 31 +#define TEGRA_GPIO_PE0 32 +#define TEGRA_GPIO_PE1 33 +#define TEGRA_GPIO_PE2 34 +#define TEGRA_GPIO_PE3 35 +#define TEGRA_GPIO_PE4 36 +#define TEGRA_GPIO_PE5 37 +#define TEGRA_GPIO_PE6 38 +#define TEGRA_GPIO_PE7 39 +#define TEGRA_GPIO_PF0 40 +#define TEGRA_GPIO_PF1 41 +#define TEGRA_GPIO_PF2 42 +#define TEGRA_GPIO_PF3 43 +#define TEGRA_GPIO_PF4 44 +#define TEGRA_GPIO_PF5 45 +#define TEGRA_GPIO_PF6 46 +#define TEGRA_GPIO_PF7 47 +#define TEGRA_GPIO_PG0 48 +#define TEGRA_GPIO_PG1 49 +#define TEGRA_GPIO_PG2 50 +#define TEGRA_GPIO_PG3 51 +#define TEGRA_GPIO_PG4 52 +#define TEGRA_GPIO_PG5 53 +#define TEGRA_GPIO_PG6 54 +#define TEGRA_GPIO_PG7 55 +#define TEGRA_GPIO_PH0 56 +#define TEGRA_GPIO_PH1 57 +#define TEGRA_GPIO_PH2 58 +#define TEGRA_GPIO_PH3 59 +#define TEGRA_GPIO_PH4 60 +#define TEGRA_GPIO_PH5 61 +#define TEGRA_GPIO_PH6 62 +#define TEGRA_GPIO_PH7 63 +#define TEGRA_GPIO_PI0 64 +#define TEGRA_GPIO_PI1 65 +#define TEGRA_GPIO_PI2 66 +#define TEGRA_GPIO_PI3 67 +#define TEGRA_GPIO_PI4 68 +#define TEGRA_GPIO_PI5 69 +#define TEGRA_GPIO_PI6 70 +#define TEGRA_GPIO_PI7 71 +#define TEGRA_GPIO_PJ0 72 +#define TEGRA_GPIO_PJ1 73 +#define TEGRA_GPIO_PJ2 74 +#define TEGRA_GPIO_PJ3 75 +#define TEGRA_GPIO_PJ4 76 +#define TEGRA_GPIO_PJ5 77 +#define TEGRA_GPIO_PJ6 78 +#define TEGRA_GPIO_PJ7 79 +#define TEGRA_GPIO_PK0 80 +#define TEGRA_GPIO_PK1 81 +#define TEGRA_GPIO_PK2 82 +#define TEGRA_GPIO_PK3 83 +#define TEGRA_GPIO_PK4 84 +#define TEGRA_GPIO_PK5 85 +#define TEGRA_GPIO_PK6 86 +#define TEGRA_GPIO_PK7 87 +#define TEGRA_GPIO_PL0 88 +#define TEGRA_GPIO_PL1 89 +#define TEGRA_GPIO_PL2 90 +#define TEGRA_GPIO_PL3 91 +#define TEGRA_GPIO_PL4 92 +#define TEGRA_GPIO_PL5 93 +#define TEGRA_GPIO_PL6 94 +#define TEGRA_GPIO_PL7 95 +#define TEGRA_GPIO_PM0 96 +#define TEGRA_GPIO_PM1 97 +#define TEGRA_GPIO_PM2 98 +#define TEGRA_GPIO_PM3 99 +#define TEGRA_GPIO_PM4 100 +#define TEGRA_GPIO_PM5 101 +#define TEGRA_GPIO_PM6 102 +#define TEGRA_GPIO_PM7 103 +#define TEGRA_GPIO_PN0 104 +#define TEGRA_GPIO_PN1 105 +#define TEGRA_GPIO_PN2 106 +#define TEGRA_GPIO_PN3 107 +#define TEGRA_GPIO_PN4 108 +#define TEGRA_GPIO_PN5 109 +#define TEGRA_GPIO_PN6 110 +#define TEGRA_GPIO_PN7 111 +#define TEGRA_GPIO_PO0 112 +#define TEGRA_GPIO_PO1 113 +#define TEGRA_GPIO_PO2 114 +#define TEGRA_GPIO_PO3 115 +#define TEGRA_GPIO_PO4 116 +#define TEGRA_GPIO_PO5 117 +#define TEGRA_GPIO_PO6 118 +#define TEGRA_GPIO_PO7 119 +#define TEGRA_GPIO_PP0 120 +#define TEGRA_GPIO_PP1 121 +#define TEGRA_GPIO_PP2 122 +#define TEGRA_GPIO_PP3 123 +#define TEGRA_GPIO_PP4 124 +#define TEGRA_GPIO_PP5 125 +#define TEGRA_GPIO_PP6 126 +#define TEGRA_GPIO_PP7 127 +#define TEGRA_GPIO_PQ0 128 +#define TEGRA_GPIO_PQ1 129 +#define TEGRA_GPIO_PQ2 130 +#define TEGRA_GPIO_PQ3 131 +#define TEGRA_GPIO_PQ4 132 +#define TEGRA_GPIO_PQ5 133 +#define TEGRA_GPIO_PQ6 134 +#define TEGRA_GPIO_PQ7 135 +#define TEGRA_GPIO_PR0 136 +#define TEGRA_GPIO_PR1 137 +#define TEGRA_GPIO_PR2 138 +#define TEGRA_GPIO_PR3 139 +#define TEGRA_GPIO_PR4 140 +#define TEGRA_GPIO_PR5 141 +#define TEGRA_GPIO_PR6 142 +#define TEGRA_GPIO_PR7 143 +#define TEGRA_GPIO_PS0 144 +#define TEGRA_GPIO_PS1 145 +#define TEGRA_GPIO_PS2 146 +#define TEGRA_GPIO_PS3 147 +#define TEGRA_GPIO_PS4 148 +#define TEGRA_GPIO_PS5 149 +#define TEGRA_GPIO_PS6 150 +#define TEGRA_GPIO_PS7 151 +#define TEGRA_GPIO_PT0 152 +#define TEGRA_GPIO_PT1 153 +#define TEGRA_GPIO_PT2 154 +#define TEGRA_GPIO_PT3 155 +#define TEGRA_GPIO_PT4 156 +#define TEGRA_GPIO_PT5 157 +#define TEGRA_GPIO_PT6 158 +#define TEGRA_GPIO_PT7 159 +#define TEGRA_GPIO_PU0 160 +#define TEGRA_GPIO_PU1 161 +#define TEGRA_GPIO_PU2 162 +#define TEGRA_GPIO_PU3 163 +#define TEGRA_GPIO_PU4 164 +#define TEGRA_GPIO_PU5 165 +#define TEGRA_GPIO_PU6 166 +#define TEGRA_GPIO_PU7 167 +#define TEGRA_GPIO_PV0 168 +#define TEGRA_GPIO_PV1 169 +#define TEGRA_GPIO_PV2 170 +#define TEGRA_GPIO_PV3 171 +#define TEGRA_GPIO_PV4 172 +#define TEGRA_GPIO_PV5 173 +#define TEGRA_GPIO_PV6 174 +#define TEGRA_GPIO_PV7 175 +#define TEGRA_GPIO_PW0 176 +#define TEGRA_GPIO_PW1 177 +#define TEGRA_GPIO_PW2 178 +#define TEGRA_GPIO_PW3 179 +#define TEGRA_GPIO_PW4 180 +#define TEGRA_GPIO_PW5 181 +#define TEGRA_GPIO_PW6 182 +#define TEGRA_GPIO_PW7 183 +#define TEGRA_GPIO_PX0 184 +#define TEGRA_GPIO_PX1 185 +#define TEGRA_GPIO_PX2 186 +#define TEGRA_GPIO_PX3 187 +#define TEGRA_GPIO_PX4 188 +#define TEGRA_GPIO_PX5 189 +#define TEGRA_GPIO_PX6 190 +#define TEGRA_GPIO_PX7 191 +#define TEGRA_GPIO_PY0 192 +#define TEGRA_GPIO_PY1 193 +#define TEGRA_GPIO_PY2 194 +#define TEGRA_GPIO_PY3 195 +#define TEGRA_GPIO_PY4 196 +#define TEGRA_GPIO_PY5 197 +#define TEGRA_GPIO_PY6 198 +#define TEGRA_GPIO_PY7 199 +#define TEGRA_GPIO_PZ0 200 +#define TEGRA_GPIO_PZ1 201 +#define TEGRA_GPIO_PZ2 202 +#define TEGRA_GPIO_PZ3 203 +#define TEGRA_GPIO_PZ4 204 +#define TEGRA_GPIO_PZ5 205 +#define TEGRA_GPIO_PZ6 206 +#define TEGRA_GPIO_PZ7 207 +#define TEGRA_GPIO_PAA0 208 +#define TEGRA_GPIO_PAA1 209 +#define TEGRA_GPIO_PAA2 210 +#define TEGRA_GPIO_PAA3 211 +#define TEGRA_GPIO_PAA4 212 +#define TEGRA_GPIO_PAA5 213 +#define TEGRA_GPIO_PAA6 214 +#define TEGRA_GPIO_PAA7 215 +#define TEGRA_GPIO_PBB0 216 +#define TEGRA_GPIO_PBB1 217 +#define TEGRA_GPIO_PBB2 218 +#define TEGRA_GPIO_PBB3 219 +#define TEGRA_GPIO_PBB4 220 +#define TEGRA_GPIO_PBB5 221 +#define TEGRA_GPIO_PBB6 222 +#define TEGRA_GPIO_PBB7 223 + +#endif diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index ff26af2..04de2e8 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -57,6 +57,4 @@ void __init tegra_hotplug_init(void) tegra_hotplug_shutdown = tegra30_hotplug_shutdown; if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) tegra_hotplug_shutdown = tegra30_hotplug_shutdown; - if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124) - tegra_hotplug_shutdown = tegra30_hotplug_shutdown; } diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 26b1c2a..3f5fa07 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -24,12 +24,44 @@ #define TEGRA_IRAM_BASE 0x40000000 #define TEGRA_IRAM_SIZE SZ_256K +#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) + +#define TEGRA_HOST1X_BASE 0x50000000 +#define TEGRA_HOST1X_SIZE 0x24000 + #define TEGRA_ARM_PERIF_BASE 0x50040000 #define TEGRA_ARM_PERIF_SIZE SZ_8K +#define TEGRA_ARM_PL310_BASE 0x50043000 +#define TEGRA_ARM_PL310_SIZE SZ_4K + #define TEGRA_ARM_INT_DIST_BASE 0x50041000 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K +#define TEGRA_MPE_BASE 0x54040000 +#define TEGRA_MPE_SIZE SZ_256K + +#define TEGRA_VI_BASE 0x54080000 +#define TEGRA_VI_SIZE SZ_256K + +#define TEGRA_ISP_BASE 0x54100000 +#define TEGRA_ISP_SIZE SZ_256K + +#define TEGRA_DISPLAY_BASE 0x54200000 +#define TEGRA_DISPLAY_SIZE SZ_256K + +#define TEGRA_DISPLAY2_BASE 0x54240000 +#define TEGRA_DISPLAY2_SIZE SZ_256K + +#define TEGRA_HDMI_BASE 0x54280000 +#define TEGRA_HDMI_SIZE SZ_256K + +#define TEGRA_GART_BASE 0x58000000 +#define TEGRA_GART_SIZE SZ_32M + +#define TEGRA_RES_SEMA_BASE 0x60001000 +#define TEGRA_RES_SEMA_SIZE SZ_4K + #define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 #define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 @@ -66,15 +98,51 @@ #define TEGRA_FLOW_CTRL_BASE 0x60007000 #define TEGRA_FLOW_CTRL_SIZE 20 +#define TEGRA_AHB_DMA_BASE 0x60008000 +#define TEGRA_AHB_DMA_SIZE SZ_4K + +#define TEGRA_AHB_DMA_CH0_BASE 0x60009000 +#define TEGRA_AHB_DMA_CH0_SIZE 32 + +#define TEGRA_APB_DMA_BASE 0x6000A000 +#define TEGRA_APB_DMA_SIZE SZ_4K + +#define TEGRA_APB_DMA_CH0_BASE 0x6000B000 +#define TEGRA_APB_DMA_CH0_SIZE 32 + +#define TEGRA_AHB_GIZMO_BASE 0x6000C004 +#define TEGRA_AHB_GIZMO_SIZE 0x10C + #define TEGRA_SB_BASE 0x6000C200 #define TEGRA_SB_SIZE 256 +#define TEGRA_STATMON_BASE 0x6000C400 +#define TEGRA_STATMON_SIZE SZ_1K + +#define TEGRA_GPIO_BASE 0x6000D000 +#define TEGRA_GPIO_SIZE SZ_4K + #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K #define TEGRA_APB_MISC_BASE 0x70000000 #define TEGRA_APB_MISC_SIZE SZ_4K +#define TEGRA_APB_MISC_DAS_BASE 0x70000c00 +#define TEGRA_APB_MISC_DAS_SIZE SZ_128 + +#define TEGRA_AC97_BASE 0x70002000 +#define TEGRA_AC97_SIZE SZ_512 + +#define TEGRA_SPDIF_BASE 0x70002400 +#define TEGRA_SPDIF_SIZE SZ_512 + +#define TEGRA_I2S1_BASE 0x70002800 +#define TEGRA_I2S1_SIZE SZ_256 + +#define TEGRA_I2S2_BASE 0x70002A00 +#define TEGRA_I2S2_SIZE SZ_256 + #define TEGRA_UARTA_BASE 0x70006000 #define TEGRA_UARTA_SIZE SZ_64 @@ -90,27 +158,108 @@ #define TEGRA_UARTE_BASE 0x70006400 #define TEGRA_UARTE_SIZE SZ_256 +#define TEGRA_NAND_BASE 0x70008000 +#define TEGRA_NAND_SIZE SZ_256 + +#define TEGRA_HSMMC_BASE 0x70008500 +#define TEGRA_HSMMC_SIZE SZ_256 + +#define TEGRA_SNOR_BASE 0x70009000 +#define TEGRA_SNOR_SIZE SZ_4K + +#define TEGRA_PWFM_BASE 0x7000A000 +#define TEGRA_PWFM_SIZE SZ_256 + +#define TEGRA_PWFM0_BASE 0x7000A000 +#define TEGRA_PWFM0_SIZE 4 + +#define TEGRA_PWFM1_BASE 0x7000A010 +#define TEGRA_PWFM1_SIZE 4 + +#define TEGRA_PWFM2_BASE 0x7000A020 +#define TEGRA_PWFM2_SIZE 4 + +#define TEGRA_PWFM3_BASE 0x7000A030 +#define TEGRA_PWFM3_SIZE 4 + +#define TEGRA_MIPI_BASE 0x7000B000 +#define TEGRA_MIPI_SIZE SZ_256 + +#define TEGRA_I2C_BASE 0x7000C000 +#define TEGRA_I2C_SIZE SZ_256 + +#define TEGRA_TWC_BASE 0x7000C100 +#define TEGRA_TWC_SIZE SZ_256 + +#define TEGRA_SPI_BASE 0x7000C380 +#define TEGRA_SPI_SIZE 48 + +#define TEGRA_I2C2_BASE 0x7000C400 +#define TEGRA_I2C2_SIZE SZ_256 + +#define TEGRA_I2C3_BASE 0x7000C500 +#define TEGRA_I2C3_SIZE SZ_256 + +#define TEGRA_OWR_BASE 0x7000C600 +#define TEGRA_OWR_SIZE 80 + +#define TEGRA_DVC_BASE 0x7000D000 +#define TEGRA_DVC_SIZE SZ_512 + +#define TEGRA_SPI1_BASE 0x7000D400 +#define TEGRA_SPI1_SIZE SZ_512 + +#define TEGRA_SPI2_BASE 0x7000D600 +#define TEGRA_SPI2_SIZE SZ_512 + +#define TEGRA_SPI3_BASE 0x7000D800 +#define TEGRA_SPI3_SIZE SZ_512 + +#define TEGRA_SPI4_BASE 0x7000DA00 +#define TEGRA_SPI4_SIZE SZ_512 + +#define TEGRA_RTC_BASE 0x7000E000 +#define TEGRA_RTC_SIZE SZ_256 + +#define TEGRA_KBC_BASE 0x7000E200 +#define TEGRA_KBC_SIZE SZ_256 + #define TEGRA_PMC_BASE 0x7000E400 #define TEGRA_PMC_SIZE SZ_256 +#define TEGRA_MC_BASE 0x7000F000 +#define TEGRA_MC_SIZE SZ_1K + #define TEGRA_EMC_BASE 0x7000F400 #define TEGRA_EMC_SIZE SZ_1K #define TEGRA_FUSE_BASE 0x7000F800 #define TEGRA_FUSE_SIZE SZ_1K +#define TEGRA_KFUSE_BASE 0x7000FC00 +#define TEGRA_KFUSE_SIZE SZ_1K + #define TEGRA_EMC0_BASE 0x7001A000 #define TEGRA_EMC0_SIZE SZ_2K #define TEGRA_EMC1_BASE 0x7001A800 #define TEGRA_EMC1_SIZE SZ_2K -#define TEGRA124_EMC_BASE 0x7001B000 -#define TEGRA124_EMC_SIZE SZ_2K - #define TEGRA_CSITE_BASE 0x70040000 #define TEGRA_CSITE_SIZE SZ_256K +#define TEGRA_SDMMC1_BASE 0xC8000000 +#define TEGRA_SDMMC1_SIZE SZ_512 + +#define TEGRA_SDMMC2_BASE 0xC8000200 +#define TEGRA_SDMMC2_SIZE SZ_512 + +#define TEGRA_SDMMC3_BASE 0xC8000400 +#define TEGRA_SDMMC3_SIZE SZ_512 + +#define TEGRA_SDMMC4_BASE 0xC8000600 +#define TEGRA_SDMMC4_SIZE SZ_512 + /* On TEGRA, many peripherals are very closely packed in * two 256MB io windows (that actually only use about 64KB * at the start of each). diff --git a/arch/arm/mach-tegra/irammap.h b/arch/arm/mach-tegra/irammap.h index e32e174..501952a 100644 --- a/arch/arm/mach-tegra/irammap.h +++ b/arch/arm/mach-tegra/irammap.h @@ -23,10 +23,4 @@ #define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 #define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K -/* - * This area is used for LPx resume vector, only while LPx power state is - * active. At other times, the AVP may use this area for arbitrary purposes - */ -#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K) - #endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index eb72ae7..2d02036 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -176,8 +176,6 @@ static int tegra_boot_secondary(unsigned int cpu, return tegra30_boot_secondary(cpu, idle); if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) return tegra114_boot_secondary(cpu, idle); - if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124) - return tegra114_boot_secondary(cpu, idle); return -EINVAL; } diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 4ae0286..ed294a0 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -59,10 +59,8 @@ static void tegra_tear_down_cpu_init(void) break; case TEGRA30: case TEGRA114: - case TEGRA124: if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) + IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) tegra_tear_down_cpu = tegra30_tear_down_cpu; break; } @@ -218,10 +216,8 @@ static bool tegra_lp1_iram_hook(void) break; case TEGRA30: case TEGRA114: - case TEGRA124: if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) + IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) tegra30_lp1_iram_hook(); break; default: @@ -248,10 +244,8 @@ static bool tegra_sleep_core_init(void) break; case TEGRA30: case TEGRA114: - case TEGRA124: if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || - IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) + IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) tegra30_sleep_core_init(); break; default: @@ -269,10 +263,10 @@ static void tegra_suspend_enter_lp1(void) tegra_pmc_suspend(); /* copy the reset vector & SDRAM shutdown code into IRAM */ - memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), + memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA), + iram_save_size); + memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr, iram_save_size); - memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), - tegra_lp1_iram.start_addr, iram_save_size); *((u32 *)tegra_cpu_lp1_mask) = 1; } @@ -282,7 +276,7 @@ static void tegra_suspend_exit_lp1(void) tegra_pmc_resume(); /* restore IRAM */ - memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, + memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr, iram_save_size); *(u32 *)tegra_cpu_lp1_mask = 0; diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 6e92a7c..fe204e5 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -37,6 +37,9 @@ void tegra30_sleep_core_init(void); extern unsigned long l2x0_saved_regs_addr; +void save_cpu_arch_register(void); +void restore_cpu_arch_register(void); + void tegra_clear_cpu_in_lp2(void); bool tegra_set_cpu_in_lp2(void); diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index fb79202..8acb881 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -20,7 +20,6 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/tegra-powergate.h> #include "flowctrl.h" #include "fuse.h" @@ -44,6 +43,12 @@ #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc +#define TEGRA_POWERGATE_PCIE 3 +#define TEGRA_POWERGATE_VDEC 4 +#define TEGRA_POWERGATE_CPU1 9 +#define TEGRA_POWERGATE_CPU2 10 +#define TEGRA_POWERGATE_CPU3 11 + static u8 tegra_cpu_domains[] = { 0xFF, /* not available for CPU0 */ TEGRA_POWERGATE_CPU1, @@ -161,15 +166,6 @@ int tegra_pmc_cpu_remove_clamping(int cpuid) return tegra_pmc_powergate_remove_clamping(id); } -void tegra_pmc_restart(enum reboot_mode mode, const char *cmd) -{ - u32 val; - - val = tegra_pmc_readl(0); - val |= 0x10; - tegra_pmc_writel(val, 0); -} - #ifdef CONFIG_PM_SLEEP static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) { @@ -283,35 +279,13 @@ void tegra_pmc_suspend_init(void) #endif static const struct of_device_id matches[] __initconst = { - { .compatible = "nvidia,tegra124-pmc" }, { .compatible = "nvidia,tegra114-pmc" }, { .compatible = "nvidia,tegra30-pmc" }, { .compatible = "nvidia,tegra20-pmc" }, { } }; -void __init tegra_pmc_init_irq(void) -{ - struct device_node *np; - u32 val; - - np = of_find_matching_node(NULL, matches); - BUG_ON(!np); - - tegra_pmc_base = of_iomap(np, 0); - - tegra_pmc_invert_interrupt = of_property_read_bool(np, - "nvidia,invert-interrupt"); - - val = tegra_pmc_readl(PMC_CTRL); - if (tegra_pmc_invert_interrupt) - val |= PMC_CTRL_INTR_LOW; - else - val &= ~PMC_CTRL_INTR_LOW; - tegra_pmc_writel(val, PMC_CTRL); -} - -void __init tegra_pmc_init(void) +static void __init tegra_pmc_parse_dt(void) { struct device_node *np; u32 prop; @@ -322,6 +296,10 @@ void __init tegra_pmc_init(void) np = of_find_matching_node(NULL, matches); BUG_ON(!np); + tegra_pmc_base = of_iomap(np, 0); + + tegra_pmc_invert_interrupt = of_property_read_bool(np, + "nvidia,invert-interrupt"); tegra_pclk = of_clk_get_by_name(np, "pclk"); WARN_ON(IS_ERR(tegra_pclk)); @@ -387,3 +365,17 @@ void __init tegra_pmc_init(void) pmc_pm_data.suspend_mode = suspend_mode; } + +void __init tegra_pmc_init(void) +{ + u32 val; + + tegra_pmc_parse_dt(); + + val = tegra_pmc_readl(PMC_CTRL); + if (tegra_pmc_invert_interrupt) + val |= PMC_CTRL_INTR_LOW; + else + val &= ~PMC_CTRL_INTR_LOW; + tegra_pmc_writel(val, PMC_CTRL); +} diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index 59e19c34..549f8c7 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h @@ -18,8 +18,6 @@ #ifndef __MACH_TEGRA_PMC_H #define __MACH_TEGRA_PMC_H -#include <linux/reboot.h> - enum tegra_suspend_mode { TEGRA_SUSPEND_NONE = 0, TEGRA_SUSPEND_LP2, /* CPU voltage off */ @@ -41,9 +39,6 @@ bool tegra_pmc_cpu_is_powered(int cpuid); int tegra_pmc_cpu_power_on(int cpuid); int tegra_pmc_cpu_remove_clamping(int cpuid); -void tegra_pmc_restart(enum reboot_mode mode, const char *cmd); - -void tegra_pmc_init_irq(void); void tegra_pmc_init(void); #endif diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 85d28e7..f076f0f 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -42,16 +42,8 @@ static int tegra_num_powerdomains; static int tegra_num_cpu_domains; -static const u8 *tegra_cpu_domains; - -static const u8 tegra30_cpu_domains[] = { - TEGRA_POWERGATE_CPU, - TEGRA_POWERGATE_CPU1, - TEGRA_POWERGATE_CPU2, - TEGRA_POWERGATE_CPU3, -}; - -static const u8 tegra114_cpu_domains[] = { +static u8 *tegra_cpu_domains; +static u8 tegra30_cpu_domains[] = { TEGRA_POWERGATE_CPU0, TEGRA_POWERGATE_CPU1, TEGRA_POWERGATE_CPU2, @@ -197,11 +189,6 @@ int __init tegra_powergate_init(void) tegra_num_cpu_domains = 4; tegra_cpu_domains = tegra30_cpu_domains; break; - case TEGRA114: - tegra_num_powerdomains = 23; - tegra_num_cpu_domains = 4; - tegra_cpu_domains = tegra114_cpu_domains; - break; default: /* Unknown Tegra variant. Disable powergating */ tegra_num_powerdomains = 0; @@ -242,27 +229,6 @@ static const char * const powergate_name_t30[] = { [TEGRA_POWERGATE_3D1] = "3d1", }; -static const char * const powergate_name_t114[] = { - [TEGRA_POWERGATE_CPU] = "cpu0", - [TEGRA_POWERGATE_3D] = "3d", - [TEGRA_POWERGATE_VENC] = "venc", - [TEGRA_POWERGATE_VDEC] = "vdec", - [TEGRA_POWERGATE_MPE] = "mpe", - [TEGRA_POWERGATE_HEG] = "heg", - [TEGRA_POWERGATE_CPU1] = "cpu1", - [TEGRA_POWERGATE_CPU2] = "cpu2", - [TEGRA_POWERGATE_CPU3] = "cpu3", - [TEGRA_POWERGATE_CELP] = "celp", - [TEGRA_POWERGATE_CPU0] = "cpu0", - [TEGRA_POWERGATE_C0NC] = "c0nc", - [TEGRA_POWERGATE_C1NC] = "c1nc", - [TEGRA_POWERGATE_DIS] = "dis", - [TEGRA_POWERGATE_DISB] = "disb", - [TEGRA_POWERGATE_XUSBA] = "xusba", - [TEGRA_POWERGATE_XUSBB] = "xusbb", - [TEGRA_POWERGATE_XUSBC] = "xusbc", -}; - static int powergate_show(struct seq_file *s, void *data) { int i; @@ -270,14 +236,9 @@ static int powergate_show(struct seq_file *s, void *data) seq_printf(s, " powergate powered\n"); seq_printf(s, "------------------\n"); - for (i = 0; i < tegra_num_powerdomains; i++) { - if (!powergate_name[i]) - continue; - + for (i = 0; i < tegra_num_powerdomains; i++) seq_printf(s, " %9s %7s\n", powergate_name[i], tegra_powergate_is_powered(i) ? "yes" : "no"); - } - return 0; } @@ -304,9 +265,6 @@ int __init tegra_powergate_debugfs_init(void) case TEGRA30: powergate_name = powergate_name_t30; break; - case TEGRA114: - powergate_name = powergate_name_t114; - break; } if (powergate_name) { diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 8c1ba4f..f527b2c 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -45,11 +45,17 @@ ENTRY(tegra_resume) check_cpu_part_num 0xc09, r8, r9 bleq v7_invalidate_l1 + blne tegra_init_l2_for_a15 cpu_id r0 + tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + cmp r6, #TEGRA114 + beq no_cpu0_chk + cmp r0, #0 @ CPU0? THUMB( it ne ) bne cpu_resume @ no +no_cpu0_chk: /* Are we on Tegra20? */ cmp r6, #TEGRA20 @@ -69,7 +75,7 @@ ENTRY(tegra_resume) mov32 r9, 0xc09 cmp r8, r9 - bne end_ca9_scu_l2_resume + bne not_ca9 #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ mov32 r0, TEGRA_ARM_PERIF_BASE @@ -80,10 +86,7 @@ ENTRY(tegra_resume) /* L2 cache resume & re-enable */ l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr -end_ca9_scu_l2_resume: - mov32 r9, 0xc0f - cmp r8, r9 - bleq tegra_init_l2_for_a15 +not_ca9: b cpu_resume ENDPROC(tegra_resume) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 568f5bb..fd0bbf8 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -82,7 +82,7 @@ void __init tegra_cpu_reset_handler_init(void) #ifdef CONFIG_PM_SLEEP __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = - TEGRA_IRAM_LPx_RESUME_AREA; + TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index aaaf3ab..5c3bd11 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -25,7 +25,6 @@ #include <asm/cp15.h> #include <asm/cache.h> -#include "irammap.h" #include "sleep.h" #include "flowctrl.h" @@ -236,7 +235,7 @@ ENTRY(tegra20_sleep_core_finish) mov32 r0, tegra20_tear_down_core mov32 r1, tegra20_iram_start sub r0, r0, r1 - mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA + mov32 r1, TEGRA_IRAM_CODE_AREA add r0, r0, r1 mov pc, r3 @@ -329,7 +328,7 @@ tegra20_iram_start: * The physical address of tegra_resume expected to be stored in * PMC_SCRATCH41. * - * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. + * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. */ ENTRY(tegra20_lp1_reset) /* diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index b16d4a57..63fa91b 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -20,7 +20,6 @@ #include <asm/asm-offsets.h> #include <asm/cache.h> -#include "irammap.h" #include "fuse.h" #include "sleep.h" #include "flowctrl.h" @@ -263,7 +262,7 @@ ENTRY(tegra30_sleep_core_finish) mov32 r0, tegra30_tear_down_core mov32 r1, tegra30_iram_start sub r0, r0, r1 - mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA + mov32 r1, TEGRA_IRAM_CODE_AREA add r0, r0, r1 mov pc, r3 @@ -315,7 +314,7 @@ tegra30_iram_start: * The physical address of tegra_resume expected to be stored in * PMC_SCRATCH41. * - * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. + * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. */ ENTRY(tegra30_lp1_reset) /* @@ -383,7 +382,7 @@ _pll_m_c_x_done: add r1, r1, #LOCK_DELAY wait_until r1, r7, r3 - adr r5, tegra_sdram_pad_save + adr r5, tegra30_sdram_pad_save ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] @@ -408,12 +407,8 @@ _pll_m_c_x_done: cmp r10, #TEGRA30 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base movteq r0, #:upper16:TEGRA_EMC_BASE - cmp r10, #TEGRA114 - movweq r0, #:lower16:TEGRA_EMC0_BASE - movteq r0, #:upper16:TEGRA_EMC0_BASE - cmp r10, #TEGRA124 - movweq r0, #:lower16:TEGRA124_EMC_BASE - movteq r0, #:upper16:TEGRA124_EMC_BASE + movwne r0, #:lower16:TEGRA_EMC0_BASE + movtne r0, #:upper16:TEGRA_EMC0_BASE exit_self_refresh: ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL @@ -542,7 +537,6 @@ tegra30_sdram_pad_address: .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c -tegra30_sdram_pad_address_end: tegra114_sdram_pad_address: .word TEGRA_EMC0_BASE + EMC_CFG @0x0 @@ -558,28 +552,16 @@ tegra114_sdram_pad_address: .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 -tegra114_sdram_pad_adress_end: - -tegra124_sdram_pad_address: - .word TEGRA124_EMC_BASE + EMC_CFG @0x0 - .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 - .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 - .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc - .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 - .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c -tegra124_sdram_pad_address_end: tegra30_sdram_pad_size: - .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address + .word tegra114_sdram_pad_address - tegra30_sdram_pad_address tegra114_sdram_pad_size: - .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address + .word tegra30_sdram_pad_size - tegra114_sdram_pad_address - .type tegra_sdram_pad_save, %object -tegra_sdram_pad_save: - .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4 + .type tegra30_sdram_pad_save, %object +tegra30_sdram_pad_save: + .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4 .long 0 .endr @@ -710,18 +692,13 @@ halted: */ tegra30_sdram_self_refresh: - adr r8, tegra_sdram_pad_save + adr r8, tegra30_sdram_pad_save tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 cmp r10, #TEGRA30 adreq r2, tegra30_sdram_pad_address ldreq r3, tegra30_sdram_pad_size - cmp r10, #TEGRA114 - adreq r2, tegra114_sdram_pad_address - ldreq r3, tegra114_sdram_pad_size - cmp r10, #TEGRA124 - adreq r2, tegra124_sdram_pad_address - ldreq r3, tegra30_sdram_pad_size - + adrne r2, tegra114_sdram_pad_address + ldrne r3, tegra114_sdram_pad_size mov r9, #0 padsave: @@ -739,10 +716,7 @@ padsave_done: cmp r10, #TEGRA30 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr - cmp r10, #TEGRA114 - ldreq r0, =TEGRA_EMC0_BASE - cmp r10, #TEGRA124 - ldreq r0, =TEGRA124_EMC_BASE + ldrne r0, =TEGRA_EMC0_BASE enter_self_refresh: cmp r10, #TEGRA30 diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 7336817..5b86055 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -16,6 +16,7 @@ * */ +#include <linux/clocksource.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> @@ -33,78 +34,16 @@ #include <linux/sys_soc.h> #include <linux/usb/tegra_usb_phy.h> #include <linux/clk/tegra.h> -#include <linux/irqchip.h> -#include <asm/hardware/cache-l2x0.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> -#include "apbio.h" #include "board.h" #include "common.h" -#include "cpuidle.h" #include "fuse.h" #include "iomap.h" -#include "irq.h" -#include "pmc.h" -#include "pm.h" -#include "reset.h" -#include "sleep.h" - -/* - * Storage for debug-macro.S's state. - * - * This must be in .data not .bss so that it gets initialized each time the - * kernel is loaded. The data is declared here rather than debug-macro.S so - * that multiple inclusions of debug-macro.S point at the same data. - */ -u32 tegra_uart_config[4] = { - /* Debug UART initialization required */ - 1, - /* Debug UART physical address */ - 0, - /* Debug UART virtual address */ - 0, - /* Scratch space for debug macro */ - 0, -}; - -static void __init tegra_init_cache(void) -{ -#ifdef CONFIG_CACHE_L2X0 - int ret; - void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; - u32 aux_ctrl, cache_type; - - cache_type = readl(p + L2X0_CACHE_TYPE); - aux_ctrl = (cache_type & 0x700) << (17-8); - aux_ctrl |= 0x7C400001; - - ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); - if (!ret) - l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); -#endif -} - -static void __init tegra_init_early(void) -{ - tegra_apb_io_init(); - tegra_init_fuse(); - tegra_cpu_reset_handler_init(); - tegra_init_cache(); - tegra_powergate_init(); - tegra_hotplug_init(); -} - -static void __init tegra_dt_init_irq(void) -{ - tegra_pmc_init_irq(); - tegra_init_irq(); - irqchip_init(); - tegra_legacy_irq_syscore_init(); -} static void __init tegra_dt_init(void) { @@ -112,8 +51,6 @@ static void __init tegra_dt_init(void) struct soc_device *soc_dev; struct device *parent = NULL; - tegra_pmc_init(); - tegra_clocks_apply_init_table(); soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -160,9 +97,7 @@ static void __init tegra_dt_init_late(void) { int i; - tegra_init_suspend(); - tegra_cpuidle_init(); - tegra_powergate_debugfs_init(); + tegra_init_late(); for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { if (of_machine_is_compatible(board_init_funcs[i].machine)) { @@ -173,7 +108,6 @@ static void __init tegra_dt_init_late(void) } static const char * const tegra_dt_board_compat[] = { - "nvidia,tegra124", "nvidia,tegra114", "nvidia,tegra30", "nvidia,tegra20", @@ -185,8 +119,9 @@ DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") .smp = smp_ops(tegra_smp_ops), .init_early = tegra_init_early, .init_irq = tegra_dt_init_irq, + .init_time = clocksource_of_init, .init_machine = tegra_dt_init, .init_late = tegra_dt_init_late, - .restart = tegra_pmc_restart, + .restart = tegra_assert_system_reset, .dt_compat = tegra_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 8e23071..a165986 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -5,6 +5,7 @@ config ARCH_U300 select ARM_AMBA select ARM_PATCH_PHYS_VIRT select ARM_VIC + select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF select COMMON_CLK diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 9a5f9fb..b5db207 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -358,7 +358,8 @@ static struct delay_timer u300_delay_timer; */ static void __init u300_timer_init_of(struct device_node *np) { - unsigned int irq; + struct resource irq_res; + int irq; struct clk *clk; unsigned long rate; @@ -367,11 +368,11 @@ static void __init u300_timer_init_of(struct device_node *np) panic("could not ioremap system timer\n"); /* Get the IRQ for the GP1 timer */ - irq = irq_of_parse_and_map(np, 2); - if (!irq) + irq = of_irq_to_resource(np, 2, &irq_res); + if (irq <= 0) panic("no IRQ for system timer\n"); - pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq); + pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq); /* Clock the interrupt controller */ clk = of_clk_get(np, 0); diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 0034d2c..99a28d6 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,34 +1,40 @@ config ARCH_U8500 bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7 depends on MMU - select AB8500_CORE - select ABX500_CORE select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_AMBA - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP - select ARM_GIC - select CACHE_L2X0 - select CLKSRC_NOMADIK_MTU - select COMMON_CLK + select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select PINCTRL - select PINCTRL_ABX500 - select PINCTRL_NOMADIK - select PL310_ERRATA_753970 if CACHE_PL310 help Support for ST-Ericsson's Ux500 architecture if ARCH_U8500 +config UX500_SOC_COMMON + bool + default y + select ABX500_CORE + select AB8500_CORE + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select ARM_GIC + select CACHE_L2X0 + select CLKSRC_NOMADIK_MTU + select COMMON_CLK + select PINCTRL + select PINCTRL_NOMADIK + select PINCTRL_ABX500 + select PL310_ERRATA_753970 if CACHE_PL310 + config UX500_SOC_DB8500 bool + select CPU_FREQ_TABLE if CPU_FREQ select MFD_DB8500_PRCMU select PINCTRL_DB8500 select PINCTRL_DB8540 diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 616b96e..fe1f3e2 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,11 +2,14 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := cpu.o devices.o id.o timer.o pm.o +obj-y := cpu.o devices.o devices-common.o \ + id.o usb.o timer.o pm.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-regulators.o \ + board-mop500-uib.o board-mop500-stuib.o \ + board-mop500-u8500uib.o \ board-mop500-pins.o \ board-mop500-audio.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 154e15f..ec08072 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -68,6 +68,40 @@ static struct stedma40_chan_cfg msp2_dma_tx = { .phy_channel = 1, }; +static struct platform_device *db8500_add_msp_i2s(struct device *parent, + int id, + resource_size_t base, int irq, + struct msp_i2s_platform_data *pdata) +{ + struct platform_device *pdev; + struct resource res[] = { + DEFINE_RES_MEM(base, SZ_4K), + DEFINE_RES_IRQ(irq), + }; + + pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n", + id, irq); + pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); + if (!pdev) { + pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n", + id); + return NULL; + } + + return pdev; +} + +/* Platform device for ASoC MOP500 machine */ +static struct platform_device snd_soc_mop500 = { + .name = "snd-soc-mop500", + .id = 0, + .dev = { + .platform_data = NULL, + }, +}; + struct msp_i2s_platform_data msp2_platform_data = { .id = MSP_I2S_2, .msp_i2s_dma_rx = &msp2_dma_rx, @@ -79,3 +113,19 @@ struct msp_i2s_platform_data msp3_platform_data = { .msp_i2s_dma_rx = &msp1_dma_rx, .msp_i2s_dma_tx = NULL, }; + +void mop500_audio_init(struct device *parent) +{ + pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); + platform_device_register(&snd_soc_mop500); + + pr_info("Initialize MSP I2S-devices.\n"); + db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, + &msp0_platform_data); + db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, + &msp1_platform_data); + db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, + &msp2_platform_data); + db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, + &msp3_platform_data); +} diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 26600a1..b3e61a3 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -65,6 +65,18 @@ struct mmci_platform_data mop500_sdi0_data = { #endif }; +static void sdi0_configure(struct device *parent) +{ + /* Add the device, force v2 to subrevision 1 */ + db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID); +} + +void mop500_sdi_tc35892_init(struct device *parent) +{ + mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD; + sdi0_configure(parent); +} + /* * SDI1 (SDIO WLAN) */ @@ -166,3 +178,42 @@ struct mmci_platform_data mop500_sdi4_data = { .dma_tx_param = &mop500_sdi4_dma_cfg_tx, #endif }; + +void __init mop500_sdi_init(struct device *parent) +{ + /* PoP:ed eMMC */ + db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID); + /* On-board eMMC */ + db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + + /* + * On boards with the TC35892 GPIO expander, sdi0 will finally + * be added when the TC35892 initializes and calls + * mop500_sdi_tc35892_init() above. + */ +} + +void __init snowball_sdi_init(struct device *parent) +{ + /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */ + mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED; + /* On-board eMMC */ + db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ + mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; + mop500_sdi0_data.cd_invert = true; + sdi0_configure(parent); +} + +void __init hrefv60_sdi_init(struct device *parent) +{ + /* PoP:ed eMMC */ + db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID); + /* On-board eMMC */ + db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); + /* External Micro SD slot */ + mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; + sdi0_configure(parent); + /* WLAN SDIO channel */ + db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID); +} diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c new file mode 100644 index 0000000..7e1f294 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-stuib.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mfd/stmpe.h> +#include <linux/input/bu21013.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/input/matrix_keypad.h> +#include <asm/mach-types.h> + +#include "board-mop500.h" + +/* STMPE/SKE keypad use this key layout */ +static const unsigned int mop500_keymap[] = { + KEY(2, 5, KEY_END), + KEY(4, 1, KEY_POWER), + KEY(3, 5, KEY_VOLUMEDOWN), + KEY(1, 3, KEY_3), + KEY(5, 2, KEY_RIGHT), + KEY(5, 0, KEY_9), + + KEY(0, 5, KEY_MENU), + KEY(7, 6, KEY_ENTER), + KEY(4, 5, KEY_0), + KEY(6, 7, KEY_2), + KEY(3, 4, KEY_UP), + KEY(3, 3, KEY_DOWN), + + KEY(6, 4, KEY_SEND), + KEY(6, 2, KEY_BACK), + KEY(4, 2, KEY_VOLUMEUP), + KEY(5, 5, KEY_1), + KEY(4, 3, KEY_LEFT), + KEY(3, 2, KEY_7), +}; + +static const struct matrix_keymap_data mop500_keymap_data = { + .keymap = mop500_keymap, + .keymap_size = ARRAY_SIZE(mop500_keymap), +}; +/* + * STMPE1601 + */ +static struct stmpe_keypad_platform_data stmpe1601_keypad_data = { + .debounce_ms = 64, + .scan_count = 8, + .no_autorepeat = true, + .keymap_data = &mop500_keymap_data, +}; + +static struct stmpe_platform_data stmpe1601_data = { + .id = 1, + .blocks = STMPE_BLOCK_KEYPAD, + .irq_trigger = IRQF_TRIGGER_FALLING, + .irq_base = MOP500_STMPE1601_IRQ(0), + .keypad = &stmpe1601_keypad_data, + .autosleep = true, + .autosleep_timeout = 1024, +}; + +static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = { + { + I2C_BOARD_INFO("stmpe1601", 0x40), + .irq = NOMADIK_GPIO_TO_IRQ(218), + .platform_data = &stmpe1601_data, + .flags = I2C_CLIENT_WAKE, + }, +}; + +/* + * BU21013 ROHM touchscreen interface on the STUIBs + */ + +#define TOUCH_GPIO_PIN 84 + +#define TOUCH_XMAX 384 +#define TOUCH_YMAX 704 + +#define PRCMU_CLOCK_OCR 0x1CC +#define TSC_EXT_CLOCK_9_6MHZ 0x840000 + +static struct bu21013_platform_device tsc_plat_device = { + .touch_pin = TOUCH_GPIO_PIN, + .touch_x_max = TOUCH_XMAX, + .touch_y_max = TOUCH_YMAX, + .ext_clk = false, + .x_flip = false, + .y_flip = true, +}; + +static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { + { + I2C_BOARD_INFO("bu21013_tp", 0x5C), + .platform_data = &tsc_plat_device, + }, + { + I2C_BOARD_INFO("bu21013_tp", 0x5D), + .platform_data = &tsc_plat_device, + }, +}; + +void __init mop500_stuib_init(void) +{ + if (machine_is_hrefv60()) + tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO; + else + tsc_plat_device.cs_pin = GPIO_BU21013_CS; + + mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib, + ARRAY_SIZE(mop500_i2c0_devices_stuib)); + + mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib, + ARRAY_SIZE(u8500_i2c3_devices_stuib)); +} diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c new file mode 100644 index 0000000..d397c19 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Board data for the U8500 UIB, also known as the New UIB + * License terms: GNU General Public License (GPL), version 2 + */ +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/mfd/tc3589x.h> +#include <linux/input/matrix_keypad.h> + +#include "irqs.h" + +#include "board-mop500.h" + +static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = { + { + I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B), + .irq = NOMADIK_GPIO_TO_IRQ(84), + }, +}; + +/* + * TC35893 + */ +static const unsigned int u8500_keymap[] = { + KEY(3, 1, KEY_END), + KEY(4, 1, KEY_POWER), + KEY(6, 4, KEY_VOLUMEDOWN), + KEY(4, 2, KEY_EMAIL), + KEY(3, 3, KEY_RIGHT), + KEY(2, 5, KEY_BACKSPACE), + + KEY(6, 7, KEY_MENU), + KEY(5, 0, KEY_ENTER), + KEY(4, 3, KEY_0), + KEY(3, 4, KEY_DOT), + KEY(5, 2, KEY_UP), + KEY(3, 5, KEY_DOWN), + + KEY(4, 5, KEY_SEND), + KEY(0, 5, KEY_BACK), + KEY(6, 2, KEY_VOLUMEUP), + KEY(1, 3, KEY_SPACE), + KEY(7, 6, KEY_LEFT), + KEY(5, 5, KEY_SEARCH), +}; + +static struct matrix_keymap_data u8500_keymap_data = { + .keymap = u8500_keymap, + .keymap_size = ARRAY_SIZE(u8500_keymap), +}; + +static struct tc3589x_keypad_platform_data tc35893_data = { + .krow = TC_KPD_ROWS, + .kcol = TC_KPD_COLUMNS, + .debounce_period = TC_KPD_DEBOUNCE_PERIOD, + .settle_time = TC_KPD_SETTLE_TIME, + .irqtype = IRQF_TRIGGER_FALLING, + .enable_wakeup = true, + .keymap_data = &u8500_keymap_data, + .no_autorepeat = true, +}; + +static struct tc3589x_platform_data tc3589x_keypad_data = { + .block = TC3589x_BLOCK_KEYPAD, + .keypad = &tc35893_data, + .irq_base = MOP500_EGPIO_IRQ_BASE, +}; + +static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = { + { + I2C_BOARD_INFO("tc3589x", 0x44), + .platform_data = &tc3589x_keypad_data, + .irq = NOMADIK_GPIO_TO_IRQ(218), + .flags = I2C_CLIENT_WAKE, + }, +}; + + +void __init mop500_u8500uib_init(void) +{ + mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500, + ARRAY_SIZE(mop500_i2c3_devices_u8500)); + + mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500, + ARRAY_SIZE(mop500_i2c0_devices_u8500)); + +} diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c new file mode 100644 index 0000000..bdaa422 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-uib.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2 + */ + +#define pr_fmt(fmt) "mop500-uib: " fmt + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/i2c.h> + +#include "board-mop500.h" +#include "id.h" + +enum mop500_uib { + STUIB, + U8500UIB, +}; + +struct uib { + const char *name; + const char *option; + void (*init)(void); +}; + +static struct uib __initdata mop500_uibs[] = { + [STUIB] = { + .name = "ST-UIB", + .option = "stuib", + .init = mop500_stuib_init, + }, + [U8500UIB] = { + .name = "U8500-UIB", + .option = "u8500uib", + .init = mop500_u8500uib_init, + }, +}; + +static struct uib *mop500_uib; + +static int __init mop500_uib_setup(char *str) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) { + struct uib *uib = &mop500_uibs[i]; + + if (!strcmp(str, uib->option)) { + mop500_uib = uib; + break; + } + } + + if (i == ARRAY_SIZE(mop500_uibs)) + pr_err("invalid uib= option (%s)\n", str); + + return 1; +} +__setup("uib=", mop500_uib_setup); + +/* + * The UIBs are detected after the I2C host controllers are registered, so + * i2c_register_board_info() can't be used. + */ +void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, + unsigned n) +{ + struct i2c_adapter *adap; + struct i2c_client *client; + int i; + + adap = i2c_get_adapter(busnum); + if (!adap) { + pr_err("failed to get adapter i2c%d\n", busnum); + return; + } + + for (i = 0; i < n; i++) { + client = i2c_new_device(adap, &info[i]); + if (!client) + pr_err("failed to register %s to i2c%d\n", + info[i].type, busnum); + } + + i2c_put_adapter(adap); +} + +static void __init __mop500_uib_init(struct uib *uib, const char *why) +{ + pr_info("%s (%s)\n", uib->name, why); + uib->init(); +} + +/* + * Detect the UIB attached based on the presence or absence of i2c devices. + */ +int __init mop500_uib_init(void) +{ + struct uib *uib = mop500_uib; + struct i2c_adapter *i2c0; + int ret; + + if (!cpu_is_u8500_family()) + return -ENODEV; + + if (uib) { + __mop500_uib_init(uib, "from uib= boot argument"); + return 0; + } + + i2c0 = i2c_get_adapter(0); + if (!i2c0) { + __mop500_uib_init(&mop500_uibs[STUIB], + "fallback, could not get i2c0"); + return -ENODEV; + } + + /* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */ + ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0, + I2C_SMBUS_QUICK, NULL); + i2c_put_adapter(i2c0); + + if (ret == 0) + uib = &mop500_uibs[U8500UIB]; + else + uib = &mop500_uibs[STUIB]; + + __mop500_uib_init(uib, "detected"); + + return 0; +} diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 514d40b..ad0806e 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -14,16 +14,27 @@ #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/i2c.h> +#include <linux/platform_data/i2c-nomadik.h> #include <linux/platform_data/db8500_thermal.h> +#include <linux/gpio.h> #include <linux/amba/bus.h> #include <linux/amba/pl022.h> +#include <linux/amba/serial.h> +#include <linux/spi/spi.h> #include <linux/mfd/abx500/ab8500.h> #include <linux/regulator/ab8500.h> #include <linux/regulator/fixed.h> #include <linux/regulator/driver.h> +#include <linux/regulator/gpio-regulator.h> +#include <linux/mfd/tc3589x.h> #include <linux/mfd/tps6105x.h> +#include <linux/mfd/abx500/ab8500-gpio.h> +#include <linux/mfd/abx500/ab8500-codec.h> #include <linux/platform_data/leds-lp55xx.h> #include <linux/input.h> +#include <linux/smsc911x.h> +#include <linux/gpio_keys.h> #include <linux/delay.h> #include <linux/leds.h> #include <linux/pinctrl/consumer.h> @@ -35,6 +46,7 @@ #include "setup.h" #include "devices.h" #include "irqs.h" +#include <linux/platform_data/crypto-ux500.h> #include "ste-dma40-db8500.h" #include "db8500-regs.h" @@ -42,9 +54,401 @@ #include "board-mop500.h" #include "board-mop500-regulators.h" +static struct gpio_led snowball_led_array[] = { + { + .name = "user_led", + .default_trigger = "heartbeat", + .gpio = 142, + }, +}; + +static struct gpio_led_platform_data snowball_led_data = { + .leds = snowball_led_array, + .num_leds = ARRAY_SIZE(snowball_led_array), +}; + +static struct platform_device snowball_led_dev = { + .name = "leds-gpio", + .dev = { + .platform_data = &snowball_led_data, + }, +}; + +static struct fixed_voltage_config snowball_gpio_en_3v3_data = { + .supply_name = "EN-3V3", + .gpio = SNOWBALL_EN_3V3_ETH_GPIO, + .microvolts = 3300000, + .enable_high = 1, + .init_data = &gpio_en_3v3_regulator, + .startup_delay = 5000, /* 1200us */ +}; + +static struct platform_device snowball_gpio_en_3v3_regulator_dev = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &snowball_gpio_en_3v3_data, + }, +}; + +/* Dynamically populated. */ +static struct gpio sdi0_reg_gpios[] = { + { 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" }, +}; + +static struct gpio_regulator_state sdi0_reg_states[] = { + { .value = 2900000, .gpios = (0 << 0) }, + { .value = 1800000, .gpios = (1 << 0) }, +}; + +static struct gpio_regulator_config sdi0_reg_info = { + .supply_name = "ext-mmc-level-shifter", + .gpios = sdi0_reg_gpios, + .nr_gpios = ARRAY_SIZE(sdi0_reg_gpios), + .states = sdi0_reg_states, + .nr_states = ARRAY_SIZE(sdi0_reg_states), + .type = REGULATOR_VOLTAGE, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &sdi0_reg_init_data, + .startup_delay = 100, +}; + +static struct platform_device sdi0_regulator = { + .name = "gpio-regulator", + .id = -1, + .dev = { + .platform_data = &sdi0_reg_info, + }, +}; + +static struct abx500_gpio_platform_data ab8500_gpio_pdata = { + .gpio_base = MOP500_AB8500_PIN_GPIO(1), +}; + +/* ab8500-codec */ +static struct ab8500_codec_platform_data ab8500_codec_pdata = { + .amics = { + .mic1_type = AMIC_TYPE_DIFFERENTIAL, + .mic2_type = AMIC_TYPE_DIFFERENTIAL, + .mic1a_micbias = AMIC_MICBIAS_VAMIC1, + .mic1b_micbias = AMIC_MICBIAS_VAMIC1, + .mic2_micbias = AMIC_MICBIAS_VAMIC2 + }, + .ear_cmv = EAR_CMV_0_95V +}; + +static struct gpio_keys_button snowball_key_array[] = { + { + .gpio = 32, + .type = EV_KEY, + .code = KEY_1, + .desc = "userpb", + .active_low = 1, + .debounce_interval = 50, + .wakeup = 1, + }, + { + .gpio = 151, + .type = EV_KEY, + .code = KEY_2, + .desc = "extkb1", + .active_low = 1, + .debounce_interval = 50, + .wakeup = 1, + }, + { + .gpio = 152, + .type = EV_KEY, + .code = KEY_3, + .desc = "extkb2", + .active_low = 1, + .debounce_interval = 50, + .wakeup = 1, + }, + { + .gpio = 161, + .type = EV_KEY, + .code = KEY_4, + .desc = "extkb3", + .active_low = 1, + .debounce_interval = 50, + .wakeup = 1, + }, + { + .gpio = 162, + .type = EV_KEY, + .code = KEY_5, + .desc = "extkb4", + .active_low = 1, + .debounce_interval = 50, + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data snowball_key_data = { + .buttons = snowball_key_array, + .nbuttons = ARRAY_SIZE(snowball_key_array), +}; + +static struct platform_device snowball_key_dev = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &snowball_key_data, + } +}; + +static struct smsc911x_platform_config snowball_sbnet_cfg = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, + .shift = 1, +}; + +static struct resource sbnet_res[] = { + { + .name = "smsc911x-memory", + .start = (0x5000 << 16), + .end = (0x5000 << 16) + 0xffff, + .flags = IORESOURCE_MEM, + }, + { + .start = NOMADIK_GPIO_TO_IRQ(140), + .end = NOMADIK_GPIO_TO_IRQ(140), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; + +static struct platform_device snowball_sbnet_dev = { + .name = "smsc911x", + .num_resources = ARRAY_SIZE(sbnet_res), + .resource = sbnet_res, + .dev = { + .platform_data = &snowball_sbnet_cfg, + }, +}; + struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, .regulator = &ab8500_regulator_plat_data, + .gpio = &ab8500_gpio_pdata, + .codec = &ab8500_codec_pdata, +}; + +static struct platform_device u8500_cpufreq_cooling_device = { + .name = "db8500-cpufreq-cooling", +}; + +/* + * TPS61052 + */ + +static struct tps6105x_platform_data mop500_tps61052_data = { + .mode = TPS6105X_MODE_VOLTAGE, + .regulator_data = &tps61052_regulator, +}; + +/* + * TC35892 + */ + +static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) +{ + struct device *parent = NULL; +#if 0 + /* FIXME: Is the sdi actually part of tc3589x? */ + parent = tc3589x->dev; +#endif + mop500_sdi_tc35892_init(parent); +} + +static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { + .gpio_base = MOP500_EGPIO(0), + .setup = mop500_tc35892_init, +}; + +static struct tc3589x_platform_data mop500_tc35892_data = { + .block = TC3589x_BLOCK_GPIO, + .gpio = &mop500_tc35892_gpio_data, + .irq_base = MOP500_EGPIO_IRQ_BASE, +}; + +static struct lp55xx_led_config lp5521_pri_led[] = { + [0] = { + .chan_nr = 0, + .led_current = 0x2f, + .max_current = 0x5f, + }, + [1] = { + .chan_nr = 1, + .led_current = 0x2f, + .max_current = 0x5f, + }, + [2] = { + .chan_nr = 2, + .led_current = 0x2f, + .max_current = 0x5f, + }, +}; + +static struct lp55xx_platform_data __initdata lp5521_pri_data = { + .label = "lp5521_pri", + .led_config = &lp5521_pri_led[0], + .num_channels = 3, + .clock_mode = LP55XX_CLOCK_EXT, +}; + +static struct lp55xx_led_config lp5521_sec_led[] = { + [0] = { + .chan_nr = 0, + .led_current = 0x2f, + .max_current = 0x5f, + }, + [1] = { + .chan_nr = 1, + .led_current = 0x2f, + .max_current = 0x5f, + }, + [2] = { + .chan_nr = 2, + .led_current = 0x2f, + .max_current = 0x5f, + }, +}; + +static struct lp55xx_platform_data __initdata lp5521_sec_data = { + .label = "lp5521_sec", + .led_config = &lp5521_sec_led[0], + .num_channels = 3, + .clock_mode = LP55XX_CLOCK_EXT, +}; + +/* I2C0 devices only available on the first HREF/MOP500 */ +static struct i2c_board_info __initdata mop500_i2c0_devices[] = { + { + I2C_BOARD_INFO("tc3589x", 0x42), + .irq = NOMADIK_GPIO_TO_IRQ(217), + .platform_data = &mop500_tc35892_data, + }, + { + I2C_BOARD_INFO("tps61052", 0x33), + .platform_data = &mop500_tps61052_data, + }, +}; + +static struct i2c_board_info __initdata mop500_i2c2_devices[] = { + { + /* lp5521 LED driver, 1st device */ + I2C_BOARD_INFO("lp5521", 0x33), + .platform_data = &lp5521_pri_data, + }, + { + /* lp5521 LED driver, 2st device */ + I2C_BOARD_INFO("lp5521", 0x34), + .platform_data = &lp5521_sec_data, + }, + { + /* Light sensor Rohm BH1780GLI */ + I2C_BOARD_INFO("bh1780", 0x29), + }, +}; + +static int __init mop500_i2c_board_init(void) +{ + if (machine_is_u8500()) + mop500_uib_i2c_add(0, mop500_i2c0_devices, + ARRAY_SIZE(mop500_i2c0_devices)); + mop500_uib_i2c_add(2, mop500_i2c2_devices, + ARRAY_SIZE(mop500_i2c2_devices)); + return 0; +} +device_initcall(mop500_i2c_board_init); + +static void __init mop500_i2c_init(struct device *parent) +{ + db8500_add_i2c0(parent, NULL); + db8500_add_i2c1(parent, NULL); + db8500_add_i2c2(parent, NULL); + db8500_add_i2c3(parent, NULL); +} + +static struct gpio_keys_button mop500_gpio_keys[] = { + { + .desc = "SFH7741 Proximity Sensor", + .type = EV_SW, + .code = SW_FRONT_PROXIMITY, + .active_low = 0, + .can_disable = 1, + } +}; + +static struct regulator *prox_regulator; +static int mop500_prox_activate(struct device *dev); +static void mop500_prox_deactivate(struct device *dev); + +static struct gpio_keys_platform_data mop500_gpio_keys_data = { + .buttons = mop500_gpio_keys, + .nbuttons = ARRAY_SIZE(mop500_gpio_keys), + .enable = mop500_prox_activate, + .disable = mop500_prox_deactivate, +}; + +static struct platform_device mop500_gpio_keys_device = { + .name = "gpio-keys", + .id = 0, + .dev = { + .platform_data = &mop500_gpio_keys_data, + }, +}; + +static int mop500_prox_activate(struct device *dev) +{ + prox_regulator = regulator_get(&mop500_gpio_keys_device.dev, + "vcc"); + if (IS_ERR(prox_regulator)) { + dev_err(&mop500_gpio_keys_device.dev, + "no regulator\n"); + return PTR_ERR(prox_regulator); + } + + return regulator_enable(prox_regulator); +} + +static void mop500_prox_deactivate(struct device *dev) +{ + regulator_disable(prox_regulator); + regulator_put(prox_regulator); +} + +static struct cryp_platform_data u8500_cryp1_platform_data = { + .mem_to_engine = { + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV48_CAC1, + .mode = STEDMA40_MODE_LOGICAL, + }, + .engine_to_mem = { + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV48_CAC1, + .mode = STEDMA40_MODE_LOGICAL, + } +}; + +static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV50_HAC1_TX, + .mode = STEDMA40_MODE_LOGICAL, +}; + +static struct hash_platform_data u8500_hash1_platform_data = { + .mem_to_engine = &u8500_hash_dma_cfg_tx, + .dma_filter = stedma40_filter, +}; + +/* add any platform devices here - TODO */ +static struct platform_device *mop500_platform_devs[] __initdata = { + &mop500_gpio_keys_device, + &sdi0_regulator, }; #ifdef CONFIG_STE_DMA40 @@ -76,3 +480,236 @@ struct pl022_ssp_controller ssp0_plat = { */ .num_chipselect = 5, }; + +static void __init mop500_spi_init(struct device *parent) +{ + db8500_add_ssp0(parent, &ssp0_plat); +} + +#ifdef CONFIG_STE_DMA40 +static struct stedma40_chan_cfg uart0_dma_cfg_rx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV13_UART0, +}; + +static struct stedma40_chan_cfg uart0_dma_cfg_tx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV13_UART0, +}; + +static struct stedma40_chan_cfg uart1_dma_cfg_rx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV12_UART1, +}; + +static struct stedma40_chan_cfg uart1_dma_cfg_tx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV12_UART1, +}; + +static struct stedma40_chan_cfg uart2_dma_cfg_rx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_DEV_TO_MEM, + .dev_type = DB8500_DMA_DEV11_UART2, +}; + +static struct stedma40_chan_cfg uart2_dma_cfg_tx = { + .mode = STEDMA40_MODE_LOGICAL, + .dir = DMA_MEM_TO_DEV, + .dev_type = DB8500_DMA_DEV11_UART2, +}; +#endif + +struct amba_pl011_data uart0_plat = { +#ifdef CONFIG_STE_DMA40 + .dma_filter = stedma40_filter, + .dma_rx_param = &uart0_dma_cfg_rx, + .dma_tx_param = &uart0_dma_cfg_tx, +#endif +}; + +struct amba_pl011_data uart1_plat = { +#ifdef CONFIG_STE_DMA40 + .dma_filter = stedma40_filter, + .dma_rx_param = &uart1_dma_cfg_rx, + .dma_tx_param = &uart1_dma_cfg_tx, +#endif +}; + +struct amba_pl011_data uart2_plat = { +#ifdef CONFIG_STE_DMA40 + .dma_filter = stedma40_filter, + .dma_rx_param = &uart2_dma_cfg_rx, + .dma_tx_param = &uart2_dma_cfg_tx, +#endif +}; + +static void __init mop500_uart_init(struct device *parent) +{ + db8500_add_uart0(parent, &uart0_plat); + db8500_add_uart1(parent, &uart1_plat); + db8500_add_uart2(parent, &uart2_plat); +} + +static void __init u8500_cryp1_hash1_init(struct device *parent) +{ + db8500_add_cryp1(parent, &u8500_cryp1_platform_data); + db8500_add_hash1(parent, &u8500_hash1_platform_data); +} + +static struct platform_device *snowball_platform_devs[] __initdata = { + &snowball_led_dev, + &snowball_key_dev, + &snowball_sbnet_dev, + &snowball_gpio_en_3v3_regulator_dev, + &u8500_cpufreq_cooling_device, + &sdi0_regulator, +}; + +static void __init mop500_init_machine(void) +{ + struct device *parent = NULL; + int i; + + platform_device_register(&db8500_prcmu_device); + mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; + + sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN; + sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL; + + mop500_pinmaps_init(); + parent = u8500_init_devices(); + + for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) + mop500_platform_devs[i]->dev.parent = parent; + + platform_add_devices(mop500_platform_devs, + ARRAY_SIZE(mop500_platform_devs)); + + mop500_i2c_init(parent); + mop500_sdi_init(parent); + mop500_spi_init(parent); + mop500_audio_init(parent); + mop500_uart_init(parent); + u8500_cryp1_hash1_init(parent); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + + +static void __init snowball_init_machine(void) +{ + struct device *parent = NULL; + int i; + + platform_device_register(&db8500_prcmu_device); + + sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO; + sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO; + + snowball_pinmaps_init(); + parent = u8500_init_devices(); + + for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) + snowball_platform_devs[i]->dev.parent = parent; + + platform_add_devices(snowball_platform_devs, + ARRAY_SIZE(snowball_platform_devs)); + + mop500_i2c_init(parent); + snowball_sdi_init(parent); + mop500_spi_init(parent); + mop500_audio_init(parent); + mop500_uart_init(parent); + + u8500_cryp1_hash1_init(parent); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +static void __init hrefv60_init_machine(void) +{ + struct device *parent = NULL; + int i; + + platform_device_register(&db8500_prcmu_device); + /* + * The HREFv60 board removed a GPIO expander and routed + * all these GPIO pins to the internal GPIO controller + * instead. + */ + mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; + + sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO; + sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO; + + hrefv60_pinmaps_init(); + parent = u8500_init_devices(); + + for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) + mop500_platform_devs[i]->dev.parent = parent; + + platform_add_devices(mop500_platform_devs, + ARRAY_SIZE(mop500_platform_devs)); + + mop500_i2c_init(parent); + hrefv60_sdi_init(parent); + mop500_spi_init(parent); + mop500_audio_init(parent); + mop500_uart_init(parent); + + /* This board has full regulator constraints */ + regulator_has_full_constraints(); +} + +MACHINE_START(U8500, "ST-Ericsson MOP500 platform") + /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ + .atag_offset = 0x100, + .smp = smp_ops(ux500_smp_ops), + .map_io = u8500_map_io, + .init_irq = ux500_init_irq, + /* we re-use nomadik timer here */ + .init_time = ux500_timer_init, + .init_machine = mop500_init_machine, + .init_late = ux500_init_late, + .restart = ux500_restart, +MACHINE_END + +MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") + .atag_offset = 0x100, + .map_io = u8500_map_io, + .init_irq = ux500_init_irq, + .init_time = ux500_timer_init, + .init_machine = mop500_init_machine, + .init_late = ux500_init_late, + .restart = ux500_restart, +MACHINE_END + +MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") + .atag_offset = 0x100, + .smp = smp_ops(ux500_smp_ops), + .map_io = u8500_map_io, + .init_irq = ux500_init_irq, + .init_time = ux500_timer_init, + .init_machine = hrefv60_init_machine, + .init_late = ux500_init_late, + .restart = ux500_restart, +MACHINE_END + +MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") + .atag_offset = 0x100, + .smp = smp_ops(ux500_smp_ops), + .map_io = u8500_map_io, + .init_irq = ux500_init_irq, + /* we re-use nomadik timer here */ + .init_time = ux500_timer_init, + .init_machine = snowball_init_machine, + .init_late = NULL, + .restart = ux500_restart, +MACHINE_END diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 511d6fe..d6fab16 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -79,6 +79,7 @@ #define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ struct device; +struct i2c_board_info; extern struct mmci_platform_data mop500_sdi0_data; extern struct mmci_platform_data mop500_sdi1_data; extern struct mmci_platform_data mop500_sdi2_data; @@ -87,10 +88,25 @@ extern struct msp_i2s_platform_data msp0_platform_data; extern struct msp_i2s_platform_data msp1_platform_data; extern struct msp_i2s_platform_data msp2_platform_data; extern struct msp_i2s_platform_data msp3_platform_data; +extern struct arm_pmu_platdata db8500_pmu_platdata; +extern struct amba_pl011_data uart0_plat; +extern struct amba_pl011_data uart1_plat; +extern struct amba_pl011_data uart2_plat; extern struct pl022_ssp_controller ssp0_plat; +extern struct stedma40_platform_data dma40_plat_data; +extern void mop500_sdi_init(struct device *parent); +extern void snowball_sdi_init(struct device *parent); +extern void hrefv60_sdi_init(struct device *parent); +extern void mop500_sdi_tc35892_init(struct device *parent); +void __init mop500_u8500uib_init(void); +void __init mop500_stuib_init(void); void __init mop500_pinmaps_init(void); void __init snowball_pinmaps_init(void); void __init hrefv60_pinmaps_init(void); +void mop500_audio_init(struct device *parent); +int __init mop500_uib_init(void); +void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, + unsigned n); #endif diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 12c7e5c..301c346 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -32,6 +32,7 @@ #include "irqs.h" #include "devices-db8500.h" +#include "ste-dma40-db8500.h" #include "db8500-regs.h" #include "board-mop500.h" #include "id.h" @@ -92,6 +93,14 @@ void __init u8500_map_io(void) iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); } +static struct resource db8500_pmu_resources[] = { + [0] = { + .start = IRQ_DB8500_PMU, + .end = IRQ_DB8500_PMU, + .flags = IORESOURCE_IRQ, + }, +}; + /* * The PMU IRQ lines of two cores are wired together into a single interrupt. * Bounce the interrupt to the other core if it's not ours. @@ -116,6 +125,54 @@ struct arm_pmu_platdata db8500_pmu_platdata = { .handle_irq = db8500_pmu_handler, }; +static struct platform_device db8500_pmu_device = { + .name = "arm-pmu", + .id = -1, + .num_resources = ARRAY_SIZE(db8500_pmu_resources), + .resource = db8500_pmu_resources, + .dev.platform_data = &db8500_pmu_platdata, +}; + +static struct platform_device *platform_devs[] __initdata = { + &u8500_dma40_device, + &db8500_pmu_device, +}; + +static resource_size_t __initdata db8500_gpio_base[] = { + U8500_GPIOBANK0_BASE, + U8500_GPIOBANK1_BASE, + U8500_GPIOBANK2_BASE, + U8500_GPIOBANK3_BASE, + U8500_GPIOBANK4_BASE, + U8500_GPIOBANK5_BASE, + U8500_GPIOBANK6_BASE, + U8500_GPIOBANK7_BASE, + U8500_GPIOBANK8_BASE, +}; + +static void __init db8500_add_gpios(struct device *parent) +{ + struct nmk_gpio_platform_data pdata = { + .supports_sleepmode = true, + }; + + dbx500_add_gpios(parent, db8500_gpio_base, + ARRAY_SIZE(db8500_gpio_base), + IRQ_DB8500_GPIO0, &pdata); + dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); +} + +static int usb_db8500_dma_cfg[] = { + DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9, + DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10, + DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11, + DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12, + DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13, + DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14, + DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15, + DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 +}; + static const char *db8500_read_soc_id(void) { void __iomem *uid = __io_address(U8500_BB_UID_BASE); @@ -135,26 +192,60 @@ static struct device * __init db8500_soc_device_init(void) return ux500_soc_device_init(soc_id); } +/* + * This function is called from the board init + */ +struct device * __init u8500_init_devices(void) +{ + struct device *parent; + int i; + + parent = db8500_soc_device_init(); + + db8500_add_rtc(parent); + db8500_add_gpios(parent); + db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg); + + for (i = 0; i < ARRAY_SIZE(platform_devs); i++) + platform_devs[i]->dev.parent = parent; + + platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); + + return parent; +} + #ifdef CONFIG_MACH_UX500_DT static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { /* Requires call-back bindings. */ OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), /* Requires DMA bindings. */ - OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), - OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, - "ux500-msp-i2s.0", &msp0_platform_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, - "ux500-msp-i2s.1", &msp1_platform_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, - "ux500-msp-i2s.2", &msp2_platform_data), - OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, - "ux500-msp-i2s.3", &msp3_platform_data), - /* Requires non-DT:able platform data. */ + OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL), + OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), + OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), + OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), + OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL), + OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", NULL), + OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", NULL), + OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL), + /* Requires clock name bindings. */ + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), + OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), + OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL), OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", &db8500_prcmu_pdata), + OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL), OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL), OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL), OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0", @@ -162,6 +253,17 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE, "pinctrl-db8500", NULL), + /* Requires clock name and DMA bindings. */ + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, + "ux500-msp-i2s.0", &msp0_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, + "ux500-msp-i2s.1", &msp1_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, + "ux500-msp-i2s.2", &msp2_platform_data), + OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, + "ux500-msp-i2s.3", &msp3_platform_data), + /* Requires clock name bindings and channel address lookup table. */ + OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL), {}, }; diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index f84d439..5d7eebc 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -78,17 +78,9 @@ void __init ux500_init_irq(void) if (cpu_is_u8500_family()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); - - if (of_have_populated_dt()) - u8500_of_clk_init(U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); - else - u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); + u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); @@ -104,6 +96,11 @@ void __init ux500_init_irq(void) } } +void __init ux500_init_late(void) +{ + mop500_uib_init(); +} + static const char * __init ux500_get_machine(void) { return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber()); diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c new file mode 100644 index 0000000..f71b3d7 --- /dev/null +++ b/arch/arm/mach-ux500/devices-common.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/platform_data/pinctrl-nomadik.h> + +#include "irqs.h" + +#include "devices-common.h" + +static struct platform_device * +dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq, + struct nmk_gpio_platform_data *pdata) +{ + struct resource resources[] = { + { + .start = addr, + .end = addr + 127, + .flags = IORESOURCE_MEM, + }, + { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + } + }; + + return platform_device_register_resndata( + parent, + "gpio", + id, + resources, + ARRAY_SIZE(resources), + pdata, + sizeof(*pdata)); +} + +void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, + int irq, struct nmk_gpio_platform_data *pdata) +{ + int first = 0; + int i; + + for (i = 0; i < num; i++, first += 32, irq++) { + pdata->first_gpio = first; + pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); + pdata->num_gpio = 32; + + dbx500_add_gpio(parent, i, base[i], irq, pdata); + } +} diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h new file mode 100644 index 0000000..96fa4ac --- /dev/null +++ b/arch/arm/mach-ux500/devices-common.h @@ -0,0 +1,149 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __DEVICES_COMMON_H +#define __DEVICES_COMMON_H + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/sys_soc.h> +#include <linux/amba/bus.h> +#include <linux/platform_data/i2c-nomadik.h> +#include <linux/platform_data/crypto-ux500.h> + +struct spi_master_cntlr; + +static inline struct amba_device * +dbx500_add_msp_spi(struct device *parent, const char *name, + resource_size_t base, int irq, + struct spi_master_cntlr *pdata) +{ + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, 0); +} + +static inline struct amba_device * +dbx500_add_spi(struct device *parent, const char *name, resource_size_t base, + int irq, struct spi_master_cntlr *pdata, + u32 periphid) +{ + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, periphid); +} + +struct mmci_platform_data; + +static inline struct amba_device * +dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base, + int irq, struct mmci_platform_data *pdata, u32 periphid) +{ + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, + pdata, periphid); +} + +struct amba_pl011_data; + +static inline struct amba_device * +dbx500_add_uart(struct device *parent, const char *name, resource_size_t base, + int irq, struct amba_pl011_data *pdata) +{ + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); +} + +struct nmk_i2c_controller; + +static inline struct amba_device * +dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq, + struct nmk_i2c_controller *data) +{ + /* Conjure a name similar to what the platform device used to have */ + char name[16]; + + snprintf(name, sizeof(name), "nmk-i2c.%d", id); + return amba_apb_device_add(parent, name, base, SZ_4K, irq, 0, data, 0); +} + +static inline struct amba_device * +dbx500_add_rtc(struct device *parent, resource_size_t base, int irq) +{ + return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq, + 0, NULL, 0); +} + +struct cryp_platform_data; + +static inline struct platform_device * +dbx500_add_cryp1(struct device *parent, int id, resource_size_t base, int irq, + struct cryp_platform_data *pdata) +{ + struct resource res[] = { + DEFINE_RES_MEM(base, SZ_4K), + DEFINE_RES_IRQ(irq), + }; + + struct platform_device_info pdevinfo = { + .parent = parent, + .name = "cryp1", + .id = id, + .res = res, + .num_res = ARRAY_SIZE(res), + .data = pdata, + .size_data = sizeof(*pdata), + .dma_mask = DMA_BIT_MASK(32), + }; + + return platform_device_register_full(&pdevinfo); +} + +struct hash_platform_data; + +static inline struct platform_device * +dbx500_add_hash1(struct device *parent, int id, resource_size_t base, + struct hash_platform_data *pdata) +{ + struct resource res[] = { + DEFINE_RES_MEM(base, SZ_4K), + }; + + struct platform_device_info pdevinfo = { + .parent = parent, + .name = "hash1", + .id = id, + .res = res, + .num_res = ARRAY_SIZE(res), + .data = pdata, + .size_data = sizeof(*pdata), + .dma_mask = DMA_BIT_MASK(32), + }; + + return platform_device_register_full(&pdevinfo); +} + +struct nmk_gpio_platform_data; + +void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, + int irq, struct nmk_gpio_platform_data *pdata); + +static inline void +dbx500_add_pinctrl(struct device *parent, const char *name, + resource_size_t base) +{ + struct resource res[] = { + DEFINE_RES_MEM(base, SZ_8K), + }; + struct platform_device_info pdevinfo = { + .parent = parent, + .name = name, + .id = -1, + .res = res, + .num_res = ARRAY_SIZE(res), + }; + + platform_device_register_full(&pdevinfo); +} + +#endif diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index c59f89d..bc31606 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -9,8 +9,10 @@ #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/amba/bus.h> #include <linux/amba/pl022.h> +#include <linux/platform_data/dma-ste-dma40.h> #include <linux/mfd/dbx500-prcmu.h> #include "setup.h" @@ -18,6 +20,62 @@ #include "db8500-regs.h" #include "devices-db8500.h" +#include "ste-dma40-db8500.h" + +static struct resource dma40_resources[] = { + [0] = { + .start = U8500_DMA_BASE, + .end = U8500_DMA_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + .name = "base", + }, + [1] = { + .start = U8500_DMA_LCPA_BASE, + .end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + .name = "lcpa", + }, + [2] = { + .start = IRQ_DB8500_DMA, + .end = IRQ_DB8500_DMA, + .flags = IORESOURCE_IRQ, + } +}; + +struct stedma40_platform_data dma40_plat_data = { + .disabled_channels = {-1}, +}; + +struct platform_device u8500_dma40_device = { + .dev = { + .platform_data = &dma40_plat_data, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .name = "dma40", + .id = 0, + .num_resources = ARRAY_SIZE(dma40_resources), + .resource = dma40_resources +}; + +struct resource keypad_resources[] = { + [0] = { + .start = U8500_SKE_BASE, + .end = U8500_SKE_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DB8500_KB, + .end = IRQ_DB8500_KB, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device u8500_ske_keypad_device = { + .name = "nmk-ske-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; struct prcmu_pdata db8500_prcmu_pdata = { .ab_platdata = &ab8500_platdata, @@ -26,3 +84,39 @@ struct prcmu_pdata db8500_prcmu_pdata = { .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, }; + +static struct resource db8500_prcmu_res[] = { + { + .name = "prcmu", + .start = U8500_PRCMU_BASE, + .end = U8500_PRCMU_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "prcmu-tcdm", + .start = U8500_PRCMU_TCDM_BASE, + .end = U8500_PRCMU_TCDM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "irq", + .start = IRQ_DB8500_PRCMU1, + .end = IRQ_DB8500_PRCMU1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "prcmu-tcpm", + .start = U8500_PRCMU_TCPM_BASE, + .end = U8500_PRCMU_TCPM_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device db8500_prcmu_device = { + .name = "db8500-prcmu", + .resource = db8500_prcmu_res, + .num_resources = ARRAY_SIZE(db8500_prcmu_res), + .dev = { + .platform_data = &db8500_prcmu_pdata, + }, +}; diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index b8ffc99..3219983 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -8,12 +8,122 @@ #ifndef __DEVICES_DB8500_H #define __DEVICES_DB8500_H +#include <linux/platform_data/usb-musb-ux500.h> #include "irqs.h" #include "db8500-regs.h" +#include "devices-common.h" +struct ske_keypad_platform_data; +struct pl022_ssp_controller; struct platform_device; extern struct ab8500_platform_data ab8500_platdata; extern struct prcmu_pdata db8500_prcmu_pdata; +extern struct platform_device db8500_prcmu_device; +static inline struct platform_device * +db8500_add_ske_keypad(struct device *parent, + struct ske_keypad_platform_data *pdata, + size_t size) +{ + struct resource resources[] = { + DEFINE_RES_MEM(U8500_SKE_BASE, SZ_4K), + DEFINE_RES_IRQ(IRQ_DB8500_KB), + }; + + return platform_device_register_resndata(parent, "nmk-ske-keypad", -1, + resources, 2, pdata, size); +} + +static inline struct amba_device * +db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, + int irq, struct pl022_ssp_controller *pdata) +{ + return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0); +} + +#define db8500_add_i2c0(parent, pdata) \ + dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) +#define db8500_add_i2c1(parent, pdata) \ + dbx500_add_i2c(parent, 1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata) +#define db8500_add_i2c2(parent, pdata) \ + dbx500_add_i2c(parent, 2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata) +#define db8500_add_i2c3(parent, pdata) \ + dbx500_add_i2c(parent, 3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata) +#define db8500_add_i2c4(parent, pdata) \ + dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) + +#define db8500_add_msp0_spi(parent, pdata) \ + dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \ + IRQ_DB8500_MSP0, pdata) +#define db8500_add_msp1_spi(parent, pdata) \ + dbx500_add_msp_spi(parent, "msp1", U8500_MSP1_BASE, \ + IRQ_DB8500_MSP1, pdata) +#define db8500_add_msp2_spi(parent, pdata) \ + dbx500_add_msp_spi(parent, "msp2", U8500_MSP2_BASE, \ + IRQ_DB8500_MSP2, pdata) +#define db8500_add_msp3_spi(parent, pdata) \ + dbx500_add_msp_spi(parent, "msp3", U8500_MSP3_BASE, \ + IRQ_DB8500_MSP1, pdata) + +#define db8500_add_rtc(parent) \ + dbx500_add_rtc(parent, U8500_RTC_BASE, IRQ_DB8500_RTC); + +#define db8500_add_usb(parent, rx_cfg, tx_cfg) \ + ux500_add_usb(parent, U8500_USBOTG_BASE, \ + IRQ_DB8500_USBOTG, rx_cfg, tx_cfg) + +#define db8500_add_sdi0(parent, pdata, pid) \ + dbx500_add_sdi(parent, "sdi0", U8500_SDI0_BASE, \ + IRQ_DB8500_SDMMC0, pdata, pid) +#define db8500_add_sdi1(parent, pdata, pid) \ + dbx500_add_sdi(parent, "sdi1", U8500_SDI1_BASE, \ + IRQ_DB8500_SDMMC1, pdata, pid) +#define db8500_add_sdi2(parent, pdata, pid) \ + dbx500_add_sdi(parent, "sdi2", U8500_SDI2_BASE, \ + IRQ_DB8500_SDMMC2, pdata, pid) +#define db8500_add_sdi3(parent, pdata, pid) \ + dbx500_add_sdi(parent, "sdi3", U8500_SDI3_BASE, \ + IRQ_DB8500_SDMMC3, pdata, pid) +#define db8500_add_sdi4(parent, pdata, pid) \ + dbx500_add_sdi(parent, "sdi4", U8500_SDI4_BASE, \ + IRQ_DB8500_SDMMC4, pdata, pid) +#define db8500_add_sdi5(parent, pdata, pid) \ + dbx500_add_sdi(parent, "sdi5", U8500_SDI5_BASE, \ + IRQ_DB8500_SDMMC5, pdata, pid) + +#define db8500_add_ssp0(parent, pdata) \ + db8500_add_ssp(parent, "ssp0", U8500_SSP0_BASE, \ + IRQ_DB8500_SSP0, pdata) +#define db8500_add_ssp1(parent, pdata) \ + db8500_add_ssp(parent, "ssp1", U8500_SSP1_BASE, \ + IRQ_DB8500_SSP1, pdata) + +#define db8500_add_spi0(parent, pdata) \ + dbx500_add_spi(parent, "spi0", U8500_SPI0_BASE, \ + IRQ_DB8500_SPI0, pdata, 0) +#define db8500_add_spi1(parent, pdata) \ + dbx500_add_spi(parent, "spi1", U8500_SPI1_BASE, \ + IRQ_DB8500_SPI1, pdata, 0) +#define db8500_add_spi2(parent, pdata) \ + dbx500_add_spi(parent, "spi2", U8500_SPI2_BASE, \ + IRQ_DB8500_SPI2, pdata, 0) +#define db8500_add_spi3(parent, pdata) \ + dbx500_add_spi(parent, "spi3", U8500_SPI3_BASE, \ + IRQ_DB8500_SPI3, pdata, 0) + +#define db8500_add_uart0(parent, pdata) \ + dbx500_add_uart(parent, "uart0", U8500_UART0_BASE, \ + IRQ_DB8500_UART0, pdata) +#define db8500_add_uart1(parent, pdata) \ + dbx500_add_uart(parent, "uart1", U8500_UART1_BASE, \ + IRQ_DB8500_UART1, pdata) +#define db8500_add_uart2(parent, pdata) \ + dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \ + IRQ_DB8500_UART2, pdata) + +#define db8500_add_cryp1(parent, pdata) \ + dbx500_add_cryp1(parent, -1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata) +#define db8500_add_hash1(parent, pdata) \ + dbx500_add_hash1(parent, -1, U8500_HASH1_BASE, pdata) #endif diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h index 5bca7c6..cbc6f1e 100644 --- a/arch/arm/mach-ux500/devices.h +++ b/arch/arm/mach-ux500/devices.h @@ -10,6 +10,14 @@ struct platform_device; struct amba_device; +extern struct platform_device u8500_gpio_devs[]; + extern struct amba_device ux500_pl031_device; +extern struct platform_device ux500_hash1_device; +extern struct platform_device ux500_cryp1_device; + +extern struct platform_device u8500_dma40_device; +extern struct platform_device ux500_ske_keypad_device; + #endif diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index bdb3564..656324a 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -24,6 +24,7 @@ extern void __init u8500_map_io(void); extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); +extern void __init ux500_init_late(void); extern struct device *ux500_soc_device_init(const char *soc_id); diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 05a4ff7..b6bd0ef 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -97,8 +97,8 @@ dt_fail: * sched_clock with higher rating then MTU since is always-on. * */ - if (!of_have_populated_dt()) - nmdk_timer_init(mtu_timer_base, IRQ_MTU0); + + nmdk_timer_init(mtu_timer_base, IRQ_MTU0); clksrc_dbx500_prcmu_init(prcmu_timer_base); ux500_twd_init(); } diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c new file mode 100644 index 0000000..b7bd8d3 --- /dev/null +++ b/arch/arm/mach-ux500/usb.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> + * License terms: GNU General Public License (GPL) version 2 + */ +#include <linux/platform_device.h> +#include <linux/usb/musb.h> +#include <linux/dma-mapping.h> +#include <linux/platform_data/usb-musb-ux500.h> +#include <linux/platform_data/dma-ste-dma40.h> + +#include "db8500-regs.h" + +#define MUSB_DMA40_RX_CH { \ + .mode = STEDMA40_MODE_LOGICAL, \ + .dir = DMA_DEV_TO_MEM, \ + } + +#define MUSB_DMA40_TX_CH { \ + .mode = STEDMA40_MODE_LOGICAL, \ + .dir = DMA_MEM_TO_DEV, \ + } + +static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] + = { + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH, + MUSB_DMA40_RX_CH +}; + +static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] + = { + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, + MUSB_DMA40_TX_CH, +}; + +static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = { + &musb_dma_rx_ch[0], + &musb_dma_rx_ch[1], + &musb_dma_rx_ch[2], + &musb_dma_rx_ch[3], + &musb_dma_rx_ch[4], + &musb_dma_rx_ch[5], + &musb_dma_rx_ch[6], + &musb_dma_rx_ch[7] +}; + +static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = { + &musb_dma_tx_ch[0], + &musb_dma_tx_ch[1], + &musb_dma_tx_ch[2], + &musb_dma_tx_ch[3], + &musb_dma_tx_ch[4], + &musb_dma_tx_ch[5], + &musb_dma_tx_ch[6], + &musb_dma_tx_ch[7] +}; + +static struct ux500_musb_board_data musb_board_data = { + .dma_rx_param_array = ux500_dma_rx_param_array, + .dma_tx_param_array = ux500_dma_tx_param_array, + .dma_filter = stedma40_filter, +}; + +static struct musb_hdrc_platform_data musb_platform_data = { + .mode = MUSB_OTG, + .board_data = &musb_board_data, +}; + +static struct resource usb_resources[] = { + [0] = { + .name = "usb-mem", + .flags = IORESOURCE_MEM, + }, + + [1] = { + .name = "mc", /* hard-coded in musb */ + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ux500_musb_device = { + .name = "musb-ux500", + .id = 0, + .dev = { + .platform_data = &musb_platform_data, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(usb_resources), + .resource = usb_resources, +}; + +static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type) +{ + u32 idx; + + for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++) + musb_dma_rx_ch[idx].dev_type = dev_type[idx]; +} + +static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type) +{ + u32 idx; + + for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++) + musb_dma_tx_ch[idx].dev_type = dev_type[idx]; +} + +void ux500_add_usb(struct device *parent, resource_size_t base, int irq, + int *dma_rx_cfg, int *dma_tx_cfg) +{ + ux500_musb_device.resource[0].start = base; + ux500_musb_device.resource[0].end = base + SZ_64K - 1; + ux500_musb_device.resource[1].start = irq; + ux500_musb_device.resource[1].end = irq; + + ux500_usb_dma_update_rx_ch_config(dma_rx_cfg); + ux500_usb_dma_update_tx_ch_config(dma_tx_cfg); + + ux500_musb_device.dev.parent = parent; + + platform_device_register(&ux500_musb_device); +} diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 4a70be4..3657954 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -1,16 +1,17 @@ config ARCH_VEXPRESS bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB - select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select CLKDEV_LOOKUP select COMMON_CLK select COMMON_CLK_VERSATILE select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select HAVE_CLK select HAVE_PATA_PLATFORM select HAVE_SMP select ICST @@ -65,22 +66,10 @@ config ARCH_VEXPRESS_DCSCB This is needed to provide CPU and cluster power management on RTSM implementing big.LITTLE. -config ARCH_VEXPRESS_SPC - bool "Versatile Express Serial Power Controller (SPC)" - select ARCH_HAS_CPUFREQ - select ARCH_HAS_OPP - select PM_OPP - help - The TC2 (A15x2 A7x3) versatile express core tile integrates a logic - block called Serial Power Controller (SPC) that provides the interface - between the dual cluster test-chip and the M3 microcontroller that - carries out power management. - config ARCH_VEXPRESS_TC2_PM bool "Versatile Express TC2 power management" depends on MCPM select ARM_CCI - select ARCH_VEXPRESS_SPC help Support for CPU and cluster power management on Versatile Express with a TC2 (A15x2 A7x3) big.LITTLE core tile. diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 0997e0b..505e64a 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -8,8 +8,7 @@ obj-y := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o CFLAGS_dcscb.o += -march=armv7-a -obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o -obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o +obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o spc.o CFLAGS_tc2_pm.o += -march=armv7-a obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 14d4996..3a6384c 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c @@ -133,8 +133,38 @@ static void dcscb_power_down(void) if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { arch_spin_unlock(&dcscb_lock); - /* Flush all cache levels for this cluster. */ - v7_exit_coherency_flush(all); + /* + * Flush all cache levels for this cluster. + * + * To do so we do: + * - Clear the SCTLR.C bit to prevent further cache allocations + * - Flush the whole cache + * - Clear the ACTLR "SMP" bit to disable local coherency + * + * Let's do it in the safest possible way i.e. with + * no memory access within the following sequence + * including to the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. + */ + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_all \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); /* * This is a harmless no-op. On platforms with a real @@ -153,8 +183,26 @@ static void dcscb_power_down(void) } else { arch_spin_unlock(&dcscb_lock); - /* Disable and flush the local CPU cache. */ - v7_exit_coherency_flush(louis); + /* + * Flush the local CPU cache. + * Let's do it in the safest possible way as above. + */ + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_louis \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); } __mcpm_cpu_down(cpu, cluster); diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index c26ef5b..eefb029 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c @@ -17,31 +17,14 @@ * GNU General Public License for more details. */ -#include <linux/clk-provider.h> -#include <linux/clkdev.h> -#include <linux/cpu.h> -#include <linux/delay.h> #include <linux/err.h> -#include <linux/interrupt.h> #include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/pm_opp.h> #include <linux/slab.h> -#include <linux/semaphore.h> #include <asm/cacheflush.h> #define SPCLOG "vexpress-spc: " -#define PERF_LVL_A15 0x00 -#define PERF_REQ_A15 0x04 -#define PERF_LVL_A7 0x08 -#define PERF_REQ_A7 0x0c -#define COMMS 0x10 -#define COMMS_REQ 0x14 -#define PWC_STATUS 0x18 -#define PWC_FLAG 0x1c - /* SPC wake-up IRQs status and mask */ #define WAKE_INT_MASK 0x24 #define WAKE_INT_RAW 0x28 @@ -53,50 +36,12 @@ #define A15_BX_ADDR0 0x68 #define A7_BX_ADDR0 0x78 -/* SPC CPU/cluster reset statue */ -#define STANDBYWFI_STAT 0x3c -#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu)) -#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu))) - -/* SPC system config interface registers */ -#define SYSCFG_WDATA 0x70 -#define SYSCFG_RDATA 0x74 - -/* A15/A7 OPP virtual register base */ -#define A15_PERFVAL_BASE 0xC10 -#define A7_PERFVAL_BASE 0xC30 - -/* Config interface control bits */ -#define SYSCFG_START (1 << 31) -#define SYSCFG_SCC (6 << 20) -#define SYSCFG_STAT (14 << 20) - /* wake-up interrupt masks */ #define GBL_WAKEUP_INT_MSK (0x3 << 10) /* TC2 static dual-cluster configuration */ #define MAX_CLUSTERS 2 -/* - * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS - * operation, the operation could start just before jiffie is about - * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz - */ -#define TIMEOUT_US 20000 - -#define MAX_OPPS 8 -#define CA15_DVFS 0 -#define CA7_DVFS 1 -#define SPC_SYS_CFG 2 -#define STAT_COMPLETE(type) ((1 << 0) << (type << 2)) -#define STAT_ERR(type) ((1 << 1) << (type << 2)) -#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type)) - -struct ve_spc_opp { - unsigned long freq; - unsigned long u_volt; -}; - struct ve_spc_drvdata { void __iomem *baseaddr; /* @@ -104,12 +49,6 @@ struct ve_spc_drvdata { * It corresponds to A15 processors MPIDR[15:8] bitfield */ u32 a15_clusid; - uint32_t cur_rsp_mask; - uint32_t cur_rsp_stat; - struct semaphore sem; - struct completion done; - struct ve_spc_opp *opps[MAX_CLUSTERS]; - int num_opps[MAX_CLUSTERS]; }; static struct ve_spc_drvdata *info; @@ -218,232 +157,8 @@ void ve_spc_powerdown(u32 cluster, bool enable) writel_relaxed(enable, info->baseaddr + pwdrn_reg); } -static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster) -{ - return cluster_is_a15(cluster) ? - STANDBYWFI_STAT_A15_CPU_MASK(cpu) - : STANDBYWFI_STAT_A7_CPU_MASK(cpu); -} - -/** - * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) - * - * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster - * @cluster: mpidr[15:8] bitfield describing cluster affinity level - * - * @return: non-zero if and only if the specified CPU is in WFI - * - * Take care when interpreting the result of this function: a CPU might - * be in WFI temporarily due to idle, and is not necessarily safely - * parked. - */ -int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) -{ - int ret; - u32 mask = standbywfi_cpu_mask(cpu, cluster); - - if (cluster >= MAX_CLUSTERS) - return 1; - - ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT); - - pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n", - __func__, STANDBYWFI_STAT, ret, mask); - - return ret & mask; -} - -static int ve_spc_get_performance(int cluster, u32 *freq) -{ - struct ve_spc_opp *opps = info->opps[cluster]; - u32 perf_cfg_reg = 0; - u32 perf; - - perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7; - - perf = readl_relaxed(info->baseaddr + perf_cfg_reg); - if (perf >= info->num_opps[cluster]) - return -EINVAL; - - opps += perf; - *freq = opps->freq; - - return 0; -} - -/* find closest match to given frequency in OPP table */ -static int ve_spc_round_performance(int cluster, u32 freq) -{ - int idx, max_opp = info->num_opps[cluster]; - struct ve_spc_opp *opps = info->opps[cluster]; - u32 fmin = 0, fmax = ~0, ftmp; - - freq /= 1000; /* OPP entries in kHz */ - for (idx = 0; idx < max_opp; idx++, opps++) { - ftmp = opps->freq; - if (ftmp >= freq) { - if (ftmp <= fmax) - fmax = ftmp; - } else { - if (ftmp >= fmin) - fmin = ftmp; - } - } - if (fmax != ~0) - return fmax * 1000; - else - return fmin * 1000; -} - -static int ve_spc_find_performance_index(int cluster, u32 freq) -{ - int idx, max_opp = info->num_opps[cluster]; - struct ve_spc_opp *opps = info->opps[cluster]; - - for (idx = 0; idx < max_opp; idx++, opps++) - if (opps->freq == freq) - break; - return (idx == max_opp) ? -EINVAL : idx; -} - -static int ve_spc_waitforcompletion(int req_type) -{ - int ret = wait_for_completion_interruptible_timeout( - &info->done, usecs_to_jiffies(TIMEOUT_US)); - if (ret == 0) - ret = -ETIMEDOUT; - else if (ret > 0) - ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO; - return ret; -} - -static int ve_spc_set_performance(int cluster, u32 freq) -{ - u32 perf_cfg_reg, perf_stat_reg; - int ret, perf, req_type; - - if (cluster_is_a15(cluster)) { - req_type = CA15_DVFS; - perf_cfg_reg = PERF_LVL_A15; - perf_stat_reg = PERF_REQ_A15; - } else { - req_type = CA7_DVFS; - perf_cfg_reg = PERF_LVL_A7; - perf_stat_reg = PERF_REQ_A7; - } - - perf = ve_spc_find_performance_index(cluster, freq); - - if (perf < 0) - return perf; - - if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US))) - return -ETIME; - - init_completion(&info->done); - info->cur_rsp_mask = RESPONSE_MASK(req_type); - - writel(perf, info->baseaddr + perf_cfg_reg); - ret = ve_spc_waitforcompletion(req_type); - - info->cur_rsp_mask = 0; - up(&info->sem); - - return ret; -} - -static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data) -{ - int ret; - - if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US))) - return -ETIME; - - init_completion(&info->done); - info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG); - - /* Set the control value */ - writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS); - ret = ve_spc_waitforcompletion(SPC_SYS_CFG); - - if (ret == 0) - *data = readl(info->baseaddr + SYSCFG_RDATA); - - info->cur_rsp_mask = 0; - up(&info->sem); - - return ret; -} - -static irqreturn_t ve_spc_irq_handler(int irq, void *data) -{ - struct ve_spc_drvdata *drv_data = data; - uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS); - - if (info->cur_rsp_mask & status) { - info->cur_rsp_stat = status; - complete(&drv_data->done); - } - - return IRQ_HANDLED; -} - -/* - * +--------------------------+ - * | 31 20 | 19 0 | - * +--------------------------+ - * | u_volt | freq(kHz) | - * +--------------------------+ - */ -#define MULT_FACTOR 20 -#define VOLT_SHIFT 20 -#define FREQ_MASK (0xFFFFF) -static int ve_spc_populate_opps(uint32_t cluster) -{ - uint32_t data = 0, off, ret, idx; - struct ve_spc_opp *opps; - - opps = kzalloc(sizeof(*opps) * MAX_OPPS, GFP_KERNEL); - if (!opps) - return -ENOMEM; - - info->opps[cluster] = opps; - - off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE; - for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) { - ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data); - if (!ret) { - opps->freq = (data & FREQ_MASK) * MULT_FACTOR; - opps->u_volt = data >> VOLT_SHIFT; - } else { - break; - } - } - info->num_opps[cluster] = idx; - - return ret; -} - -static int ve_init_opp_table(struct device *cpu_dev) +int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid) { - int cluster = topology_physical_package_id(cpu_dev->id); - int idx, ret = 0, max_opp = info->num_opps[cluster]; - struct ve_spc_opp *opps = info->opps[cluster]; - - for (idx = 0; idx < max_opp; idx++, opps++) { - ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); - if (ret) { - dev_warn(cpu_dev, "failed to add opp %lu %lu\n", - opps->freq, opps->u_volt); - return ret; - } - } - return ret; -} - -int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq) -{ - int ret; info = kzalloc(sizeof(*info), GFP_KERNEL); if (!info) { pr_err(SPCLOG "unable to allocate mem\n"); @@ -453,25 +168,6 @@ int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq) info->baseaddr = baseaddr; info->a15_clusid = a15_clusid; - if (irq <= 0) { - pr_err(SPCLOG "Invalid IRQ %d\n", irq); - kfree(info); - return -EINVAL; - } - - init_completion(&info->done); - - readl_relaxed(info->baseaddr + PWC_STATUS); - - ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH - | IRQF_ONESHOT, "vexpress-spc", info); - if (ret) { - pr_err(SPCLOG "IRQ %d request failed\n", irq); - kfree(info); - return -ENODEV; - } - - sema_init(&info->sem, 1); /* * Multi-cluster systems may need this data when non-coherent, during * cluster power-up/power-down. Make sure driver info reaches main @@ -482,103 +178,3 @@ int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq) return 0; } - -struct clk_spc { - struct clk_hw hw; - int cluster; -}; - -#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw) -static unsigned long spc_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_spc *spc = to_clk_spc(hw); - u32 freq; - - if (ve_spc_get_performance(spc->cluster, &freq)) - return -EIO; - - return freq * 1000; -} - -static long spc_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *parent_rate) -{ - struct clk_spc *spc = to_clk_spc(hw); - - return ve_spc_round_performance(spc->cluster, drate); -} - -static int spc_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_spc *spc = to_clk_spc(hw); - - return ve_spc_set_performance(spc->cluster, rate / 1000); -} - -static struct clk_ops clk_spc_ops = { - .recalc_rate = spc_recalc_rate, - .round_rate = spc_round_rate, - .set_rate = spc_set_rate, -}; - -static struct clk *ve_spc_clk_register(struct device *cpu_dev) -{ - struct clk_init_data init; - struct clk_spc *spc; - - spc = kzalloc(sizeof(*spc), GFP_KERNEL); - if (!spc) { - pr_err("could not allocate spc clk\n"); - return ERR_PTR(-ENOMEM); - } - - spc->hw.init = &init; - spc->cluster = topology_physical_package_id(cpu_dev->id); - - init.name = dev_name(cpu_dev); - init.ops = &clk_spc_ops; - init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE; - init.num_parents = 0; - - return devm_clk_register(cpu_dev, &spc->hw); -} - -static int __init ve_spc_clk_init(void) -{ - int cpu; - struct clk *clk; - - if (!info) - return 0; /* Continue only if SPC is initialised */ - - if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) { - pr_err("failed to build OPP table\n"); - return -ENODEV; - } - - for_each_possible_cpu(cpu) { - struct device *cpu_dev = get_cpu_device(cpu); - if (!cpu_dev) { - pr_warn("failed to get cpu%d device\n", cpu); - continue; - } - clk = ve_spc_clk_register(cpu_dev); - if (IS_ERR(clk)) { - pr_warn("failed to register cpu%d clock\n", cpu); - continue; - } - if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) { - pr_warn("failed to register cpu%d clock lookup\n", cpu); - continue; - } - - if (ve_init_opp_table(cpu_dev)) - pr_warn("failed to initialise cpu%d opp table\n", cpu); - } - - platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0); - return 0; -} -module_init(ve_spc_clk_init); diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h index 793d065..5f7e4a4 100644 --- a/arch/arm/mach-vexpress/spc.h +++ b/arch/arm/mach-vexpress/spc.h @@ -15,11 +15,10 @@ #ifndef __SPC_H_ #define __SPC_H_ -int __init ve_spc_init(void __iomem *base, u32 a15_clusid, int irq); +int __init ve_spc_init(void __iomem *base, u32 a15_clusid); void ve_spc_global_wakeup_irq(bool set); void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); void ve_spc_powerdown(u32 cluster, bool enable); -int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster); #endif diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index 29e7785..e6eb481 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -12,12 +12,10 @@ * published by the Free Software Foundation. */ -#include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of_address.h> -#include <linux/of_irq.h> #include <linux/spinlock.h> #include <linux/errno.h> #include <linux/irqchip/arm-gic.h> @@ -33,17 +31,11 @@ #include "spc.h" /* SCC conf registers */ -#define RESET_CTRL 0x018 -#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu))) -#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu))) - #define A15_CONF 0x400 #define A7_CONF 0x500 #define SYS_INFO 0x700 #define SPC_BASE 0xb00 -static void __iomem *scc; - /* * We can't use regular spinlocks. In the switcher case, it is possible * for an outbound CPU to call power_down() after its inbound counterpart @@ -164,7 +156,32 @@ static void tc2_pm_down(u64 residency) : : "r" (0x400) ); } - v7_exit_coherency_flush(all); + /* + * We need to disable and flush the whole (L1 and L2) cache. + * Let's do it in the safest possible way i.e. with + * no memory access within the following sequence + * including the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. + */ + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_all \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); cci_disable_port_by_cpu(mpidr); @@ -180,7 +197,26 @@ static void tc2_pm_down(u64 residency) arch_spin_unlock(&tc2_pm_lock); - v7_exit_coherency_flush(louis); + /* + * We need to disable and flush only the L1 cache. + * Let's do it in the safest possible way as above. + */ + asm volatile( + "str fp, [sp, #-4]! \n\t" + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" + "bic r0, r0, #"__stringify(CR_C)" \n\t" + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" + "isb \n\t" + "bl v7_flush_dcache_louis \n\t" + "clrex \n\t" + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" + "isb \n\t" + "dsb \n\t" + "ldr fp, [sp], #4" + : : : "r0","r1","r2","r3","r4","r5","r6","r7", + "r9","r10","lr","memory"); } __mcpm_cpu_down(cpu, cluster); @@ -197,55 +233,6 @@ static void tc2_pm_power_down(void) tc2_pm_down(0); } -static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster) -{ - u32 mask = cluster ? - RESET_A7_NCORERESET(cpu) - : RESET_A15_NCORERESET(cpu); - - return !(readl_relaxed(scc + RESET_CTRL) & mask); -} - -#define POLL_MSEC 10 -#define TIMEOUT_MSEC 1000 - -static int tc2_pm_power_down_finish(unsigned int cpu, unsigned int cluster) -{ - unsigned tries; - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); - - for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) { - /* - * Only examine the hardware state if the target CPU has - * caught up at least as far as tc2_pm_down(): - */ - if (ACCESS_ONCE(tc2_pm_use_count[cpu][cluster]) == 0) { - pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n", - __func__, cpu, cluster, - readl_relaxed(scc + RESET_CTRL)); - - /* - * We need the CPU to reach WFI, but the power - * controller may put the cluster in reset and - * power it off as soon as that happens, before - * we have a chance to see STANDBYWFI. - * - * So we need to check for both conditions: - */ - if (tc2_core_in_reset(cpu, cluster) || - ve_spc_cpu_in_wfi(cpu, cluster)) - return 0; /* success: the CPU is halted */ - } - - /* Otherwise, wait and retry: */ - msleep(POLL_MSEC); - } - - return -ETIMEDOUT; /* timeout */ -} - static void tc2_pm_suspend(u64 residency) { unsigned int mpidr, cpu, cluster; @@ -288,11 +275,10 @@ static void tc2_pm_powered_up(void) } static const struct mcpm_platform_ops tc2_pm_power_ops = { - .power_up = tc2_pm_power_up, - .power_down = tc2_pm_power_down, - .power_down_finish = tc2_pm_power_down_finish, - .suspend = tc2_pm_suspend, - .powered_up = tc2_pm_powered_up, + .power_up = tc2_pm_power_up, + .power_down = tc2_pm_power_down, + .suspend = tc2_pm_suspend, + .powered_up = tc2_pm_powered_up, }; static bool __init tc2_pm_usage_count_init(void) @@ -325,7 +311,8 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) static int __init tc2_pm_init(void) { - int ret, irq; + int ret; + void __iomem *scc; u32 a15_cluster_id, a7_cluster_id, sys_info; struct device_node *np; @@ -349,15 +336,13 @@ static int __init tc2_pm_init(void) tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf; tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf; - irq = irq_of_parse_and_map(np, 0); - /* * A subset of the SCC registers is also used to communicate * with the SPC (power controller). We need to be able to * drive it very early in the boot process to power up * processors, so we initialize the SPC driver here. */ - ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq); + ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id); if (ret) return ret; diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 4f8b8cb..95a469e 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -1,10 +1,12 @@ /* * Versatile Express V2M Motherboard Support */ +#include <linux/clocksource.h> #include <linux/device.h> #include <linux/amba/bus.h> #include <linux/amba/mmci.h> #include <linux/io.h> +#include <linux/clocksource.h> #include <linux/smp.h> #include <linux/init.h> #include <linux/of_address.h> @@ -20,6 +22,7 @@ #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/vexpress.h> +#include <linux/clk-provider.h> #include <linux/clkdev.h> #include <asm/mach-types.h> @@ -419,8 +422,16 @@ void __init v2m_dt_init_early(void) pr_warning("vexpress: DT HBI (%x) is not matching " "hardware (%x)!\n", dt_hbi, hbi); } +} - versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000); +static void __init v2m_dt_timer_init(void) +{ + of_clk_init(NULL); + + clocksource_of_init(); + + versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), + 24000000); } static const struct of_device_id v2m_dt_bus_match[] __initconst = { @@ -447,5 +458,6 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") .smp_init = smp_init_ops(vexpress_smp_init_ops), .map_io = v2m_dt_map_io, .init_early = v2m_dt_init_early, + .init_time = v2m_dt_timer_init, .init_machine = v2m_dt_init, MACHINE_END diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig index 927be93..9b25293 100644 --- a/arch/arm/mach-vt8500/Kconfig +++ b/arch/arm/mach-vt8500/Kconfig @@ -5,6 +5,7 @@ config ARCH_VT8500 select CLKDEV_LOOKUP select CLKSRC_OF select GENERIC_CLOCKEVENTS + select HAVE_CLK select VT8500_TIMER select PINCTRL help diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h new file mode 100644 index 0000000..087787a --- /dev/null +++ b/arch/arm/mach-vt8500/common.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-vt8500/dt_common.h + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H +#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H + +#include <linux/of.h> + +/* defined in drivers/clk/clk-vt8500.c */ +void __init vtwm_clk_init(void __iomem *pmc_base); + +#endif diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 4a73464..eefaa60 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -18,6 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <linux/clocksource.h> #include <linux/io.h> #include <linux/pm.h> #include <linux/reboot.h> @@ -32,6 +33,8 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> +#include "common.h" + #define LEGACY_GPIO_BASE 0xD8110000 #define LEGACY_PMC_BASE 0xD8130000 @@ -159,6 +162,8 @@ void __init vt8500_init(void) else pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__); + vtwm_clk_init(pmc_base); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } @@ -175,6 +180,7 @@ DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") .dt_compat = vt8500_dt_compat, .map_io = vt8500_map_io, .init_machine = vt8500_init, + .init_time = clocksource_of_init, .restart = vt8500_restart, MACHINE_END diff --git a/arch/arm/mach-w90x900/include/mach/gpio.h b/arch/arm/mach-w90x900/include/mach/gpio.h new file mode 100644 index 0000000..5385a42 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/gpio.h @@ -0,0 +1,30 @@ +/* + * linux/arch/arm/mach-w90p910/include/mach/gpio.h + * + * Generic w90p910 GPIO handling + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_W90P910_GPIO_H +#define __ASM_ARCH_W90P910_GPIO_H + +#include <mach/hardware.h> +#include <asm/irq.h> + +static inline int gpio_to_irq(unsigned gpio) +{ + return gpio; +} +#define gpio_to_irq gpio_to_irq + +static inline int irq_to_gpio(unsigned irq) +{ + return irq; +} + +#endif diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 6b04260..04f8a4a 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -13,6 +13,5 @@ config ARCH_ZYNQ select HAVE_SMP select SPARSE_IRQ select CADENCE_TTC_TIMER - select ARM_GLOBAL_TIMER help Support for Xilinx Zynq ARM Cortex A9 Platform diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 9a7bd13..5f25256 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -44,10 +44,6 @@ static struct of_device_id zynq_of_bus_ids[] __initdata = { {} }; -static struct platform_device zynq_cpuidle_device = { - .name = "cpuidle-zynq", -}; - /** * zynq_init_machine - System specific initialization, intended to be * called from board specific initialization. @@ -60,8 +56,6 @@ static void __init zynq_init_machine(void) l2x0_of_init(0x02060000, 0xF0F0FFFF); of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); - - platform_device_register(&zynq_cpuidle_device); } static void __init zynq_timer_init(void) diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1f8fed9..cd2c88e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -952,9 +952,3 @@ config ARCH_HAS_BARRIERS help This option allows the use of custom mandatory barriers included via the mach/barriers.h file. - -config ARCH_SUPPORTS_BIG_ENDIAN - bool - help - This option specifies the architecture can support big endian - operation. diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index 3815a82..8074199 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -38,8 +38,9 @@ ENTRY(v6_early_abort) bne do_DataAbort bic r1, r1, #1 << 11 @ clear bit 11 of FSR ldr r3, [r4] @ read aborted ARM instruction - ARM_BE8(rev r3, r3) - +#ifdef CONFIG_CPU_ENDIAN_BE8 + rev r3, r3 +#endif do_ldrd_abort tmp=ip, insn=r3 tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 9240364..6f4585b 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -25,7 +25,6 @@ #include <asm/cp15.h> #include <asm/system_info.h> #include <asm/unaligned.h> -#include <asm/opcodes.h> #include "fault.h" @@ -763,25 +762,21 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) if (thumb_mode(regs)) { u16 *ptr = (u16 *)(instrptr & ~1); fault = probe_kernel_address(ptr, tinstr); - tinstr = __mem_to_opcode_thumb16(tinstr); if (!fault) { if (cpu_architecture() >= CPU_ARCH_ARMv7 && IS_T32(tinstr)) { /* Thumb-2 32-bit */ u16 tinst2 = 0; fault = probe_kernel_address(ptr + 1, tinst2); - tinst2 = __mem_to_opcode_thumb16(tinst2); - instr = __opcode_thumb32_compose(tinstr, tinst2); + instr = (tinstr << 16) | tinst2; thumb2_32b = 1; } else { isize = 2; instr = thumb2arm(tinstr); } } - } else { + } else fault = probe_kernel_address(instrptr, instr); - instr = __mem_to_opcode_arm(instr); - } if (fault) { type = TYPE_FAULT; diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index f6b6bfa..1272ed2 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -9,7 +9,6 @@ * * DMA uncached mapping support. */ -#include <linux/bootmem.h> #include <linux/module.h> #include <linux/mm.h> #include <linux/gfp.h> @@ -160,11 +159,9 @@ EXPORT_SYMBOL(arm_coherent_dma_ops); static u64 get_coherent_dma_mask(struct device *dev) { - u64 mask = (u64)DMA_BIT_MASK(32); + u64 mask = (u64)arm_dma_limit; if (dev) { - unsigned long max_dma_pfn; - mask = dev->coherent_dma_mask; /* @@ -176,32 +173,10 @@ static u64 get_coherent_dma_mask(struct device *dev) return 0; } - max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); - - /* - * If the mask allows for more memory than we can address, - * and we actually have that much memory, then fail the - * allocation. - */ - if (sizeof(mask) != sizeof(dma_addr_t) && - mask > (dma_addr_t)~0 && - dma_to_pfn(dev, ~0) > max_dma_pfn) { - dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", - mask); - dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); - return 0; - } - - /* - * Now check that the mask, when translated to a PFN, - * fits within the allowable addresses which we can - * allocate. - */ - if (dma_to_pfn(dev, mask) < max_dma_pfn) { - dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", - mask, - dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, - arm_dma_pfn_limit + 1); + if ((~mask) & (u64)arm_dma_limit) { + dev_warn(dev, "coherent DMA mask %#llx is smaller " + "than system GFP_DMA mask %#llx\n", + mask, (u64)arm_dma_limit); return 0; } } @@ -712,7 +687,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { - pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); + pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); void *memory; if (dma_alloc_from_coherent(dev, size, handle, &memory)) @@ -725,7 +700,7 @@ void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, static void *arm_coherent_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { - pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); + pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); void *memory; if (dma_alloc_from_coherent(dev, size, handle, &memory)) @@ -1032,27 +1007,8 @@ void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, */ int dma_supported(struct device *dev, u64 mask) { - unsigned long limit; - - /* - * If the mask allows for more memory than we can address, - * and we actually have that much memory, then we must - * indicate that DMA to this device is not supported. - */ - if (sizeof(mask) != sizeof(dma_addr_t) && - mask > (dma_addr_t)~0 && - dma_to_pfn(dev, ~0) > arm_dma_pfn_limit) - return 0; - - /* - * Translate the device's DMA mask to a PFN limit. This - * PFN number includes the page which we can DMA to. - */ - limit = dma_to_pfn(dev, mask); - - if (limit < arm_dma_pfn_limit) + if (mask < (u64)arm_dma_limit) return 0; - return 1; } EXPORT_SYMBOL(dma_supported); diff --git a/arch/arm/mm/extable.c b/arch/arm/mm/extable.c index 312e15e..9d28562 100644 --- a/arch/arm/mm/extable.c +++ b/arch/arm/mm/extable.c @@ -9,13 +9,8 @@ int fixup_exception(struct pt_regs *regs) const struct exception_table_entry *fixup; fixup = search_exception_tables(instruction_pointer(regs)); - if (fixup) { + if (fixup) regs->ARM_pc = fixup->fixup; -#ifdef CONFIG_THUMB2_KERNEL - /* Clear the IT state to avoid nasty surprises in the fixup */ - regs->ARM_cpsr &= ~PSR_IT_MASK; -#endif - } return fixup != NULL; } diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index ff379ac..2a5907b 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -65,7 +65,7 @@ static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address, return ret; } -#if USE_SPLIT_PTE_PTLOCKS +#if USE_SPLIT_PTLOCKS /* * If we are using split PTE locks, then we need to take the page * lock here. Otherwise we are using shared mm->page_table_lock @@ -84,10 +84,10 @@ static inline void do_pte_unlock(spinlock_t *ptl) { spin_unlock(ptl); } -#else /* !USE_SPLIT_PTE_PTLOCKS */ +#else /* !USE_SPLIT_PTLOCKS */ static inline void do_pte_lock(spinlock_t *ptl) {} static inline void do_pte_unlock(spinlock_t *ptl) {} -#endif /* USE_SPLIT_PTE_PTLOCKS */ +#endif /* USE_SPLIT_PTLOCKS */ static int adjust_pte(struct vm_area_struct *vma, unsigned long address, unsigned long pfn) diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c index 8e0e52e..83cb3ac 100644 --- a/arch/arm/mm/idmap.c +++ b/arch/arm/mm/idmap.c @@ -10,7 +10,6 @@ #include <asm/system_info.h> pgd_t *idmap_pgd; -phys_addr_t (*arch_virt_to_idmap) (unsigned long x); #ifdef CONFIG_ARM_LPAE static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end, @@ -68,9 +67,8 @@ static void identity_mapping_add(pgd_t *pgd, const char *text_start, unsigned long addr, end; unsigned long next; - addr = virt_to_idmap(text_start); - end = virt_to_idmap(text_end); - pr_info("Setting up static identity map for 0x%lx - 0x%lx\n", addr, end); + addr = virt_to_phys(text_start); + end = virt_to_phys(text_end); prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF; @@ -92,6 +90,8 @@ static int __init init_static_idmap(void) if (!idmap_pgd) return -ENOMEM; + pr_info("Setting up static identity map for 0x%p - 0x%p\n", + __idmap_text_start, __idmap_text_end); identity_mapping_add(idmap_pgd, __idmap_text_start, __idmap_text_end, 0); diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 3e8f106..18ec4c5 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -76,6 +76,14 @@ static int __init parse_tag_initrd2(const struct tag *tag) __tagtable(ATAG_INITRD2, parse_tag_initrd2); +#ifdef CONFIG_OF_FLATTREE +void __init early_init_dt_setup_initrd_arch(u64 start, u64 end) +{ + phys_initrd_start = start; + phys_initrd_size = end - start; +} +#endif /* CONFIG_OF_FLATTREE */ + /* * This keeps memory configuration data used by a couple memory * initialization functions, as well as show_mem() for the skipping @@ -209,7 +217,6 @@ EXPORT_SYMBOL(arm_dma_zone_size); * so a successful GFP_DMA allocation will always satisfy this. */ phys_addr_t arm_dma_limit; -unsigned long arm_dma_pfn_limit; static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole, unsigned long dma_size) @@ -232,7 +239,6 @@ void __init setup_dma_zone(const struct machine_desc *mdesc) arm_dma_limit = PHYS_OFFSET + arm_dma_zone_size - 1; } else arm_dma_limit = 0xffffffff; - arm_dma_pfn_limit = arm_dma_limit >> PAGE_SHIFT; #endif } @@ -344,11 +350,6 @@ void __init arm_memblock_init(struct meminfo *mi, memblock_reserve(__pa(_stext), _end - _stext); #endif #ifdef CONFIG_BLK_DEV_INITRD - /* FDT scan will populate initrd_start */ - if (initrd_start) { - phys_initrd_start = __virt_to_phys(initrd_start); - phys_initrd_size = initrd_end - initrd_start; - } if (phys_initrd_size && !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) { pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n", @@ -420,10 +421,12 @@ void __init bootmem_init(void) * This doesn't seem to be used by the Linux memory manager any * more, but is used by ll_rw_block. If we can get rid of it, we * also get rid of some of the stuff above as well. + * + * Note: max_low_pfn and max_pfn reflect the number of _pages_ in + * the system, not the maximum PFN. */ - min_low_pfn = min; - max_low_pfn = max_low; - max_pfn = max_high; + max_low_pfn = max_low - PHYS_PFN_OFFSET; + max_pfn = max_high - PHYS_PFN_OFFSET; } /* @@ -529,7 +532,7 @@ static inline void free_area_high(unsigned long pfn, unsigned long end) static void __init free_highpages(void) { #ifdef CONFIG_HIGHMEM - unsigned long max_low = max_low_pfn; + unsigned long max_low = max_low_pfn + PHYS_PFN_OFFSET; struct memblock_region *mem, *res; /* set highmem page free */ diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index d5a982d..d5a4e9a 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -81,10 +81,8 @@ extern __init void add_static_vm_early(struct static_vm *svm); #ifdef CONFIG_ZONE_DMA extern phys_addr_t arm_dma_limit; -extern unsigned long arm_dma_pfn_limit; #else #define arm_dma_limit ((phys_addr_t)~0) -#define arm_dma_pfn_limit (~0ul >> PAGE_SHIFT) #endif extern phys_addr_t arm_lowmem_limit; diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 5e85ed3..0c63562 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -146,7 +146,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, info.flags = VM_UNMAPPED_AREA_TOPDOWN; info.length = len; - info.low_limit = FIRST_USER_ADDRESS; + info.low_limit = PAGE_SIZE; info.high_limit = mm->mmap_base; info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0; info.align_offset = pgoff << PAGE_SHIFT; @@ -202,11 +202,13 @@ int valid_phys_addr_range(phys_addr_t addr, size_t size) } /* - * Do not allow /dev/mem mappings beyond the supported physical range. + * We don't use supersection mappings for mmap() on /dev/mem, which + * means that we can't map the memory area above the 4G barrier into + * userspace. */ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) { - return (pfn + (size >> PAGE_SHIFT)) <= (1 + (PHYS_MASK >> PAGE_SHIFT)); + return !(pfn + (size >> PAGE_SHIFT) > 0x00100000); } #ifdef CONFIG_STRICT_DEVMEM diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 580ef2d..b1d17ee 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -28,8 +28,6 @@ #include <asm/highmem.h> #include <asm/system_info.h> #include <asm/traps.h> -#include <asm/procinfo.h> -#include <asm/memory.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -558,8 +556,8 @@ static void __init build_mem_type_table(void) mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; break; } - pr_info("Memory policy: %sData cache %s\n", - ecc_mask ? "ECC enabled, " : "", cp->policy); + printk("Memory policy: ECC %sabled, Data cache %s\n", + ecc_mask ? "en" : "dis", cp->policy); for (i = 0; i < ARRAY_SIZE(mem_types); i++) { struct mem_type *t = &mem_types[i]; @@ -1317,86 +1315,6 @@ static void __init map_lowmem(void) } } -#ifdef CONFIG_ARM_LPAE -/* - * early_paging_init() recreates boot time page table setup, allowing machines - * to switch over to a high (>4G) address space on LPAE systems - */ -void __init early_paging_init(const struct machine_desc *mdesc, - struct proc_info_list *procinfo) -{ - pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags; - unsigned long map_start, map_end; - pgd_t *pgd0, *pgdk; - pud_t *pud0, *pudk, *pud_start; - pmd_t *pmd0, *pmdk; - phys_addr_t phys; - int i; - - if (!(mdesc->init_meminfo)) - return; - - /* remap kernel code and data */ - map_start = init_mm.start_code; - map_end = init_mm.brk; - - /* get a handle on things... */ - pgd0 = pgd_offset_k(0); - pud_start = pud0 = pud_offset(pgd0, 0); - pmd0 = pmd_offset(pud0, 0); - - pgdk = pgd_offset_k(map_start); - pudk = pud_offset(pgdk, map_start); - pmdk = pmd_offset(pudk, map_start); - - mdesc->init_meminfo(); - - /* Run the patch stub to update the constants */ - fixup_pv_table(&__pv_table_begin, - (&__pv_table_end - &__pv_table_begin) << 2); - - /* - * Cache cleaning operations for self-modifying code - * We should clean the entries by MVA but running a - * for loop over every pv_table entry pointer would - * just complicate the code. - */ - flush_cache_louis(); - dsb(); - isb(); - - /* remap level 1 table */ - for (i = 0; i < PTRS_PER_PGD; pud0++, i++) { - set_pud(pud0, - __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER)); - pmd0 += PTRS_PER_PMD; - } - - /* remap pmds for kernel mapping */ - phys = __pa(map_start) & PMD_MASK; - do { - *pmdk++ = __pmd(phys | pmdprot); - phys += PMD_SIZE; - } while (phys < map_end); - - flush_cache_all(); - cpu_switch_mm(pgd0, &init_mm); - cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET); - local_flush_bp_all(); - local_flush_tlb_all(); -} - -#else - -void __init early_paging_init(const struct machine_desc *mdesc, - struct proc_info_list *procinfo) -{ - if (mdesc->init_meminfo) - mdesc->init_meminfo(); -} - -#endif - /* * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 55764a7..34d4ab2 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -18,7 +18,6 @@ #include <asm/mach/arch.h> #include <asm/cputype.h> #include <asm/mpu.h> -#include <asm/procinfo.h> #include "mm.h" @@ -297,15 +296,6 @@ void __init sanity_check_meminfo(void) } /* - * early_paging_init() recreates boot time page table setup, allowing machines - * to switch over to a high (>4G) address space on LPAE systems - */ -void __init early_paging_init(const struct machine_desc *mdesc, - struct proc_info_list *procinfo) -{ -} - -/* * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. */ diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index 1046b37..0acb089 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -87,8 +87,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm) init_pud = pud_offset(init_pgd, 0); init_pmd = pmd_offset(init_pud, 0); init_pte = pte_offset_map(init_pmd, 0); - set_pte_ext(new_pte + 0, init_pte[0], 0); - set_pte_ext(new_pte + 1, init_pte[1], 0); + set_pte_ext(new_pte, *init_pte, 0); pte_unmap(init_pte); pte_unmap(new_pte); } diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 45dc29f..1128064 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -220,7 +220,9 @@ __v6_setup: #endif /* CONFIG_MMU */ adr r5, v6_crval ldmia r5, {r5, r6} - ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r6, r6, #1 << 25 @ big-endian page tables +#endif mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index bd17819..c63d9bd 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -92,7 +92,7 @@ ENDPROC(cpu_v7_dcache_clean_area) /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ .globl cpu_v7_suspend_size -.equ cpu_v7_suspend_size, 4 * 9 +.equ cpu_v7_suspend_size, 4 * 8 #ifdef CONFIG_ARM_CPU_SUSPEND ENTRY(cpu_v7_do_suspend) stmfd sp!, {r4 - r10, lr} @@ -101,17 +101,13 @@ ENTRY(cpu_v7_do_suspend) stmia r0!, {r4 - r5} #ifdef CONFIG_MMU mrc p15, 0, r6, c3, c0, 0 @ Domain ID -#ifdef CONFIG_ARM_LPAE - mrrc p15, 1, r5, r7, c2 @ TTB 1 -#else mrc p15, 0, r7, c2, c0, 1 @ TTB 1 -#endif mrc p15, 0, r11, c2, c0, 2 @ TTB control register #endif mrc p15, 0, r8, c1, c0, 0 @ Control register mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control - stmia r0, {r5 - r11} + stmia r0, {r6 - r11} ldmfd sp!, {r4 - r10, pc} ENDPROC(cpu_v7_do_suspend) @@ -122,19 +118,16 @@ ENTRY(cpu_v7_do_resume) ldmia r0!, {r4 - r5} mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID - ldmia r0, {r5 - r11} + ldmia r0, {r6 - r11} #ifdef CONFIG_MMU mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r6, c3, c0, 0 @ Domain ID -#ifdef CONFIG_ARM_LPAE - mcrr p15, 0, r1, ip, c2 @ TTB 0 - mcrr p15, 1, r5, r7, c2 @ TTB 1 -#else +#ifndef CONFIG_ARM_LPAE ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) ALT_UP(orr r1, r1, #TTB_FLAGS_UP) +#endif mcr p15, 0, r1, c2, c0, 0 @ TTB 0 mcr p15, 0, r7, c2, c0, 1 @ TTB 1 -#endif mcr p15, 0, r11, c2, c0, 2 @ TTB control register ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR @@ -374,7 +367,9 @@ __v7_setup: #endif adr r5, v7_crval ldmia r5, {r5, r6} - ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables +#ifdef CONFIG_CPU_ENDIAN_BE8 + orr r6, r6, #1 << 25 @ big-endian page tables +#endif #ifdef CONFIG_SWP_EMULATE orr r5, r5, #(1 << 10) @ set SW bit in "clear" bic r6, r6, #(1 << 10) @ clear it in "mmuset" diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index 9ed155a..99b44e0 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -19,7 +19,6 @@ #include <linux/if_vlan.h> #include <asm/cacheflush.h> #include <asm/hwcap.h> -#include <asm/opcodes.h> #include "bpf_jit_32.h" @@ -114,11 +113,8 @@ static u32 jit_udiv(u32 dividend, u32 divisor) static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx) { - inst |= (cond << 28); - inst = __opcode_to_mem_arm(inst); - if (ctx->target != NULL) - ctx->target[ctx->idx] = inst; + ctx->target[ctx->idx] = inst | (cond << 28); ctx->idx++; } diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index 224e56c..a99dc15 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -5,6 +5,7 @@ obj-y := # IOP32X +obj-$(CONFIG_ARCH_IOP32X) += gpio.o obj-$(CONFIG_ARCH_IOP32X) += i2c.o obj-$(CONFIG_ARCH_IOP32X) += pci.o obj-$(CONFIG_ARCH_IOP32X) += setup.o @@ -15,6 +16,7 @@ obj-$(CONFIG_ARCH_IOP32X) += pmu.o obj-$(CONFIG_ARCH_IOP32X) += restart.o # IOP33X +obj-$(CONFIG_ARCH_IOP33X) += gpio.o obj-$(CONFIG_ARCH_IOP33X) += i2c.o obj-$(CONFIG_ARCH_IOP33X) += pci.o obj-$(CONFIG_ARCH_IOP33X) += setup.o diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c new file mode 100644 index 0000000..697de6d --- /dev/null +++ b/arch/arm/plat-iop/gpio.c @@ -0,0 +1,93 @@ +/* + * arch/arm/plat-iop/gpio.c + * GPIO handling for Intel IOP3xx processors. + * + * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include <linux/device.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/gpio.h> +#include <linux/export.h> +#include <asm/hardware/iop3xx.h> +#include <mach/gpio.h> + +void gpio_line_config(int line, int direction) +{ + unsigned long flags; + + local_irq_save(flags); + if (direction == GPIO_IN) { + *IOP3XX_GPOE |= 1 << line; + } else if (direction == GPIO_OUT) { + *IOP3XX_GPOE &= ~(1 << line); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_config); + +int gpio_line_get(int line) +{ + return !!(*IOP3XX_GPID & (1 << line)); +} +EXPORT_SYMBOL(gpio_line_get); + +void gpio_line_set(int line, int value) +{ + unsigned long flags; + + local_irq_save(flags); + if (value == GPIO_LOW) { + *IOP3XX_GPOD &= ~(1 << line); + } else if (value == GPIO_HIGH) { + *IOP3XX_GPOD |= 1 << line; + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_set); + +static int iop3xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + gpio_line_config(gpio, GPIO_IN); + return 0; +} + +static int iop3xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level) +{ + gpio_line_set(gpio, level); + gpio_line_config(gpio, GPIO_OUT); + return 0; +} + +static int iop3xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio) +{ + return gpio_line_get(gpio); +} + +static void iop3xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) +{ + gpio_line_set(gpio, value); +} + +static struct gpio_chip iop3xx_chip = { + .label = "iop3xx", + .direction_input = iop3xx_gpio_direction_input, + .get = iop3xx_gpio_get_value, + .direction_output = iop3xx_gpio_direction_output, + .set = iop3xx_gpio_set_value, + .base = 0, + .ngpio = IOP3XX_N_GPIOS, +}; + +static int __init iop3xx_gpio_setup(void) +{ + return gpiochip_add(&iop3xx_chip); +} +arch_initcall(iop3xx_gpio_setup); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 01619c2..0376606 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1965,6 +1965,7 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) static struct irqaction omap24xx_dma_irq = { .name = "DMA", .handler = omap2_dma_irq_handler, + .flags = IRQF_DISABLED }; #else diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 2861b15..fb92abb 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -336,11 +336,8 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer) if (timer->posted) return; - if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { - timer->posted = OMAP_TIMER_NONPOSTED; - __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0); + if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) return; - } __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED, 0); diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 6d95d60..7dfba93 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -382,6 +382,11 @@ config S5P_DEV_TV help Compile in platform device definition for TV interface +config S5P_DEV_USB_EHCI + bool + help + Compile in platform device definition for USB EHCI + config S3C24XX_PWM bool "PWM device support" select PWM @@ -390,6 +395,11 @@ config S3C24XX_PWM Support for exporting the PWM timer blocks via the pwm device system +config S5P_SETUP_MIPIPHY + bool + help + Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices + config S3C_SETUP_CAMIF bool help diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 9267d29..498c7c2 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o +obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o # DMA support diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c index be4ad0b..d51f956 100644 --- a/arch/arm/plat-samsung/dev-backlight.c +++ b/arch/arm/plat-samsung/dev-backlight.c @@ -70,7 +70,6 @@ static struct samsung_bl_drvdata samsung_dfl_bl_data __initdata = { .max_brightness = 255, .dft_brightness = 255, .pwm_period_ns = 78770, - .enable_gpio = -1, .init = samsung_bl_init, .exit = samsung_bl_exit, }, @@ -122,10 +121,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, samsung_bl_data->lth_brightness = bl_data->lth_brightness; if (bl_data->pwm_period_ns) samsung_bl_data->pwm_period_ns = bl_data->pwm_period_ns; - if (bl_data->enable_gpio >= 0) - samsung_bl_data->enable_gpio = bl_data->enable_gpio; - if (bl_data->enable_gpio_flags) - samsung_bl_data->enable_gpio_flags = bl_data->enable_gpio_flags; if (bl_data->init) samsung_bl_data->init = bl_data->init; if (bl_data->notify) diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 99a3590..8ce0ac0 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -32,7 +32,6 @@ #include <linux/ioport.h> #include <linux/platform_data/s3c-hsudc.h> #include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/dma-s3c24xx.h> #include <media/s5p_hdmi.h> @@ -50,6 +49,7 @@ #include <plat/devs.h> #include <plat/adc.h> #include <linux/platform_data/ata-samsung_cf.h> +#include <linux/platform_data/usb-ehci-s5p.h> #include <plat/fb.h> #include <plat/fb-s3c2410.h> #include <plat/hdmi.h> @@ -1359,6 +1359,39 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) } #endif /* CONFIG_PLAT_S3C24XX */ +/* USB EHCI Host Controller */ + +#ifdef CONFIG_S5P_DEV_USB_EHCI +static struct resource s5p_ehci_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_USB_HOST), +}; + +struct platform_device s5p_device_ehci = { + .name = "s5p-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_ehci_resource), + .resource = s5p_ehci_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd) +{ + struct s5p_ehci_platdata *npd; + + npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata), + &s5p_device_ehci); + + if (!npd->phy_init) + npd->phy_init = s5p_usb_phy_init; + if (!npd->phy_exit) + npd->phy_exit = s5p_usb_phy_exit; +} +#endif /* CONFIG_S5P_DEV_USB_EHCI */ + /* USB HSOTG */ #ifdef CONFIG_S3C_DEV_USB_HSOTG @@ -1466,10 +1499,8 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, pd.num_cs = num_cs; pd.src_clk_nr = src_clk_nr; pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; -#if defined(CONFIG_PL330_DMA) +#ifdef CONFIG_PL330_DMA pd.filter = pl330_filter; -#elif defined(CONFIG_S3C24XX_DMAC) - pd.filter = s3c24xx_dma_filter; #endif s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0); diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 335beb3..4fb1f03 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -87,12 +87,8 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) #endif #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) -# define soc_is_s3c6400() is_samsung_s3c6400() -# define soc_is_s3c6410() is_samsung_s3c6410() # define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410()) #else -# define soc_is_s3c6400() 0 -# define soc_is_s3c6410() 0 # define soc_is_s3c64xx() 0 #endif diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index eece188..0dc4ac4 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -75,6 +75,7 @@ extern struct platform_device s3c_device_usb_hsotg; extern struct platform_device s3c_device_usb_hsudc; extern struct platform_device s3c_device_wdt; +extern struct platform_device s5p_device_ehci; extern struct platform_device s5p_device_fimc0; extern struct platform_device s5p_device_fimc1; extern struct platform_device s5p_device_fimc2; diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index aa9511b..50a3ea0 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -11,18 +11,12 @@ * published by the Free Software Foundation. */ -/* - * NOTE: Code in this file is not used on S3C64xx when booting with - * Device Tree support. - */ - #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/serial_core.h> #include <linux/platform_device.h> -#include <linux/of.h> #include <mach/hardware.h> @@ -154,12 +148,8 @@ static int __init s3c_arch_init(void) // do the correct init for cpu - if (cpu == NULL) { - /* Not needed when booting with device tree. */ - if (of_have_populated_dt()) - return 0; + if (cpu == NULL) panic("s3c_arch_init: NULL cpu\n"); - } ret = (cpu->init)(); if (ret != 0) diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c new file mode 100644 index 0000000..66df315 --- /dev/null +++ b/arch/arm/plat-samsung/setup-mipiphy.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + * + * S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/export.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <mach/regs-clock.h> + +static int __s5p_mipi_phy_control(int id, bool on, u32 reset) +{ + static DEFINE_SPINLOCK(lock); + void __iomem *addr; + unsigned long flags; + u32 cfg; + + id = max(0, id); + if (id > 1) + return -EINVAL; + + addr = S5P_MIPI_DPHY_CONTROL(id); + + spin_lock_irqsave(&lock, flags); + + cfg = __raw_readl(addr); + cfg = on ? (cfg | reset) : (cfg & ~reset); + __raw_writel(cfg, addr); + + if (on) { + cfg |= S5P_MIPI_DPHY_ENABLE; + } else if (!(cfg & (S5P_MIPI_DPHY_SRESETN | + S5P_MIPI_DPHY_MRESETN) & ~reset)) { + cfg &= ~S5P_MIPI_DPHY_ENABLE; + } + + __raw_writel(cfg, addr); + spin_unlock_irqrestore(&lock, flags); + + return 0; +} + +int s5p_csis_phy_enable(int id, bool on) +{ + return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); +} +EXPORT_SYMBOL(s5p_csis_phy_enable); + +int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) +{ + return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); +} +EXPORT_SYMBOL(s5p_dsim_phy_enable); diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index 40f27e5..2677bc3 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -10,7 +10,6 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/assembler.h> /* * Realview/Versatile Express specific entry point for secondary CPUs. @@ -18,7 +17,6 @@ * until we're ready for them to initialise. */ ENTRY(versatile_secondary_startup) - ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 bic r0, #0xff000000 adr r4, 1f diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 2f37e1d..52b8f40 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -642,9 +642,9 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp, static int vfp_hotplug(struct notifier_block *b, unsigned long action, void *hcpu) { - if (action == CPU_DYING || action == CPU_DYING_FROZEN) - vfp_current_hw_state[(long)hcpu] = NULL; - else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) + if (action == CPU_DYING || action == CPU_DYING_FROZEN) { + vfp_force_reload((long)hcpu, current_thread_info()); + } else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) vfp_enable(NULL); return NOTIFY_OK; } diff --git a/arch/arm/xen/Makefile b/arch/arm/xen/Makefile index 1296952..4384103 100644 --- a/arch/arm/xen/Makefile +++ b/arch/arm/xen/Makefile @@ -1 +1 @@ -obj-y := enlighten.o hypercall.o grant-table.o p2m.o mm.o +obj-y := enlighten.o hypercall.o grant-table.o diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c deleted file mode 100644 index b0e77de..0000000 --- a/arch/arm/xen/mm.c +++ /dev/null @@ -1,65 +0,0 @@ -#include <linux/bootmem.h> -#include <linux/gfp.h> -#include <linux/export.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <linux/dma-mapping.h> -#include <linux/vmalloc.h> -#include <linux/swiotlb.h> - -#include <xen/xen.h> -#include <xen/interface/memory.h> -#include <xen/swiotlb-xen.h> - -#include <asm/cacheflush.h> -#include <asm/xen/page.h> -#include <asm/xen/hypercall.h> -#include <asm/xen/interface.h> - -int xen_create_contiguous_region(phys_addr_t pstart, unsigned int order, - unsigned int address_bits, - dma_addr_t *dma_handle) -{ - if (!xen_initial_domain()) - return -EINVAL; - - /* we assume that dom0 is mapped 1:1 for now */ - *dma_handle = pstart; - return 0; -} -EXPORT_SYMBOL_GPL(xen_create_contiguous_region); - -void xen_destroy_contiguous_region(phys_addr_t pstart, unsigned int order) -{ - return; -} -EXPORT_SYMBOL_GPL(xen_destroy_contiguous_region); - -struct dma_map_ops *xen_dma_ops; -EXPORT_SYMBOL_GPL(xen_dma_ops); - -static struct dma_map_ops xen_swiotlb_dma_ops = { - .mapping_error = xen_swiotlb_dma_mapping_error, - .alloc = xen_swiotlb_alloc_coherent, - .free = xen_swiotlb_free_coherent, - .sync_single_for_cpu = xen_swiotlb_sync_single_for_cpu, - .sync_single_for_device = xen_swiotlb_sync_single_for_device, - .sync_sg_for_cpu = xen_swiotlb_sync_sg_for_cpu, - .sync_sg_for_device = xen_swiotlb_sync_sg_for_device, - .map_sg = xen_swiotlb_map_sg_attrs, - .unmap_sg = xen_swiotlb_unmap_sg_attrs, - .map_page = xen_swiotlb_map_page, - .unmap_page = xen_swiotlb_unmap_page, - .dma_supported = xen_swiotlb_dma_supported, - .set_dma_mask = xen_swiotlb_set_dma_mask, -}; - -int __init xen_mm_init(void) -{ - if (!xen_initial_domain()) - return 0; - xen_swiotlb_init(1, false); - xen_dma_ops = &xen_swiotlb_dma_ops; - return 0; -} -arch_initcall(xen_mm_init); diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c deleted file mode 100644 index b31ee1b2..0000000 --- a/arch/arm/xen/p2m.c +++ /dev/null @@ -1,209 +0,0 @@ -#include <linux/bootmem.h> -#include <linux/gfp.h> -#include <linux/export.h> -#include <linux/rwlock.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <linux/dma-mapping.h> -#include <linux/vmalloc.h> -#include <linux/swiotlb.h> - -#include <xen/xen.h> -#include <xen/interface/memory.h> -#include <xen/swiotlb-xen.h> - -#include <asm/cacheflush.h> -#include <asm/xen/page.h> -#include <asm/xen/hypercall.h> -#include <asm/xen/interface.h> - -struct xen_p2m_entry { - unsigned long pfn; - unsigned long mfn; - unsigned long nr_pages; - struct rb_node rbnode_mach; - struct rb_node rbnode_phys; -}; - -static rwlock_t p2m_lock; -struct rb_root phys_to_mach = RB_ROOT; -EXPORT_SYMBOL_GPL(phys_to_mach); -static struct rb_root mach_to_phys = RB_ROOT; - -static int xen_add_phys_to_mach_entry(struct xen_p2m_entry *new) -{ - struct rb_node **link = &phys_to_mach.rb_node; - struct rb_node *parent = NULL; - struct xen_p2m_entry *entry; - int rc = 0; - - while (*link) { - parent = *link; - entry = rb_entry(parent, struct xen_p2m_entry, rbnode_phys); - - if (new->mfn == entry->mfn) - goto err_out; - if (new->pfn == entry->pfn) - goto err_out; - - if (new->pfn < entry->pfn) - link = &(*link)->rb_left; - else - link = &(*link)->rb_right; - } - rb_link_node(&new->rbnode_phys, parent, link); - rb_insert_color(&new->rbnode_phys, &phys_to_mach); - goto out; - -err_out: - rc = -EINVAL; - pr_warn("%s: cannot add pfn=%pa -> mfn=%pa: pfn=%pa -> mfn=%pa already exists\n", - __func__, &new->pfn, &new->mfn, &entry->pfn, &entry->mfn); -out: - return rc; -} - -unsigned long __pfn_to_mfn(unsigned long pfn) -{ - struct rb_node *n = phys_to_mach.rb_node; - struct xen_p2m_entry *entry; - unsigned long irqflags; - - read_lock_irqsave(&p2m_lock, irqflags); - while (n) { - entry = rb_entry(n, struct xen_p2m_entry, rbnode_phys); - if (entry->pfn <= pfn && - entry->pfn + entry->nr_pages > pfn) { - read_unlock_irqrestore(&p2m_lock, irqflags); - return entry->mfn + (pfn - entry->pfn); - } - if (pfn < entry->pfn) - n = n->rb_left; - else - n = n->rb_right; - } - read_unlock_irqrestore(&p2m_lock, irqflags); - - return INVALID_P2M_ENTRY; -} -EXPORT_SYMBOL_GPL(__pfn_to_mfn); - -static int xen_add_mach_to_phys_entry(struct xen_p2m_entry *new) -{ - struct rb_node **link = &mach_to_phys.rb_node; - struct rb_node *parent = NULL; - struct xen_p2m_entry *entry; - int rc = 0; - - while (*link) { - parent = *link; - entry = rb_entry(parent, struct xen_p2m_entry, rbnode_mach); - - if (new->mfn == entry->mfn) - goto err_out; - if (new->pfn == entry->pfn) - goto err_out; - - if (new->mfn < entry->mfn) - link = &(*link)->rb_left; - else - link = &(*link)->rb_right; - } - rb_link_node(&new->rbnode_mach, parent, link); - rb_insert_color(&new->rbnode_mach, &mach_to_phys); - goto out; - -err_out: - rc = -EINVAL; - pr_warn("%s: cannot add pfn=%pa -> mfn=%pa: pfn=%pa -> mfn=%pa already exists\n", - __func__, &new->pfn, &new->mfn, &entry->pfn, &entry->mfn); -out: - return rc; -} - -unsigned long __mfn_to_pfn(unsigned long mfn) -{ - struct rb_node *n = mach_to_phys.rb_node; - struct xen_p2m_entry *entry; - unsigned long irqflags; - - read_lock_irqsave(&p2m_lock, irqflags); - while (n) { - entry = rb_entry(n, struct xen_p2m_entry, rbnode_mach); - if (entry->mfn <= mfn && - entry->mfn + entry->nr_pages > mfn) { - read_unlock_irqrestore(&p2m_lock, irqflags); - return entry->pfn + (mfn - entry->mfn); - } - if (mfn < entry->mfn) - n = n->rb_left; - else - n = n->rb_right; - } - read_unlock_irqrestore(&p2m_lock, irqflags); - - return INVALID_P2M_ENTRY; -} -EXPORT_SYMBOL_GPL(__mfn_to_pfn); - -bool __set_phys_to_machine_multi(unsigned long pfn, - unsigned long mfn, unsigned long nr_pages) -{ - int rc; - unsigned long irqflags; - struct xen_p2m_entry *p2m_entry; - struct rb_node *n = phys_to_mach.rb_node; - - if (mfn == INVALID_P2M_ENTRY) { - write_lock_irqsave(&p2m_lock, irqflags); - while (n) { - p2m_entry = rb_entry(n, struct xen_p2m_entry, rbnode_phys); - if (p2m_entry->pfn <= pfn && - p2m_entry->pfn + p2m_entry->nr_pages > pfn) { - rb_erase(&p2m_entry->rbnode_mach, &mach_to_phys); - rb_erase(&p2m_entry->rbnode_phys, &phys_to_mach); - write_unlock_irqrestore(&p2m_lock, irqflags); - kfree(p2m_entry); - return true; - } - if (pfn < p2m_entry->pfn) - n = n->rb_left; - else - n = n->rb_right; - } - write_unlock_irqrestore(&p2m_lock, irqflags); - return true; - } - - p2m_entry = kzalloc(sizeof(struct xen_p2m_entry), GFP_NOWAIT); - if (!p2m_entry) { - pr_warn("cannot allocate xen_p2m_entry\n"); - return false; - } - p2m_entry->pfn = pfn; - p2m_entry->nr_pages = nr_pages; - p2m_entry->mfn = mfn; - - write_lock_irqsave(&p2m_lock, irqflags); - if ((rc = xen_add_phys_to_mach_entry(p2m_entry) < 0) || - (rc = xen_add_mach_to_phys_entry(p2m_entry) < 0)) { - write_unlock_irqrestore(&p2m_lock, irqflags); - return false; - } - write_unlock_irqrestore(&p2m_lock, irqflags); - return true; -} -EXPORT_SYMBOL_GPL(__set_phys_to_machine_multi); - -bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn) -{ - return __set_phys_to_machine_multi(pfn, mfn, 1); -} -EXPORT_SYMBOL_GPL(__set_phys_to_machine); - -static int p2m_init(void) -{ - rwlock_init(&p2m_lock); - return 0; -} -arch_initcall(p2m_init); |