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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2008-02-08 23:33:45 (GMT) |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2008-02-08 23:33:45 (GMT) |
commit | 04a94babd68952a4e3cdd54ebf8ce8891f9b0f2e (patch) | |
tree | 9d4a01f6b6d0093397c2122c4d85abbb57f3e349 /arch/blackfin/Kconfig | |
parent | 765cdb6cef63c0b41c3f6c9285769080b3f41bb0 (diff) | |
parent | 920e526f93009a81e09809edb7a755a5b22e907d (diff) | |
download | linux-fsl-qoriq-04a94babd68952a4e3cdd54ebf8ce8891f9b0f2e.tar.xz |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (24 commits)
[Blackfin] arch: import defines for BF547 -- it is just like the BF548, but no CAN
[Blackfin] arch: fix build fails only include header files when enabled
[Blackfin] arch: declare default INSTALL_PATH for Blackfin ports
[Blackfin] arch: Encourage users to use the spidev character driver: Provide platform support
[Blackfin] arch: Enable UART2 and UART3 for bf548
[Blackfin] arch: Enable NET2272 on BF561-EZkit - remove request_mem_region
[Blackfin] arch:Fix BUG [#3876] pfbutton test for BTN3 on bf533 don't show complete info
[Blackfin] arch: remove duplicated definitions of the line discipline numbers N_* in asm-blackfin/termios.h
[Blackfin] arch: fix building with mtd uclinux by putting the mtd_phys option into the function it actually gets used in
[Blackfin] arch: simpler header and update dates
[Blackfin] arch: move the init sections to the end of memory
[Blackfin] arch: change the trace buffer control start/stop logic in the exception handlers
[Blackfin] arch: fix typo in printk message
[Blackfin] arch: this is an ezkit, not a stamp, so fixup the init function name
[Blackfin] arch: add slightly better help text for CPLB_INFO
[Blackfin] arch: Fix BUG - Enable ISP1362 driver to work ok with BF561
[Blackfin] arch: Fix header file information
[Blackfin] arch: Add Support for ISP1362
[Blackfin] arch: add support for cmdline partitioning to the BF533-STAMP flash map driver and enable it as a module by default
[Blackfin] arch: hook up set_irq_wake in Blackfin's irq code
...
Diffstat (limited to 'arch/blackfin/Kconfig')
-rw-r--r-- | arch/blackfin/Kconfig | 49 |
1 files changed, 29 insertions, 20 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index ba21e33..368bc7f 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -544,7 +544,7 @@ config EXCPT_IRQ_SYSC_L1 default y help If enabled, the entire ASM lowlevel exception and interrupt entry code - (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. + (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. (less latency) config DO_IRQ_L1 @@ -904,29 +904,38 @@ config ARCH_SUSPEND_POSSIBLE depends on !SMP choice - prompt "Select PM Wakeup Event Source" - default PM_WAKEUP_GPIO_BY_SIC_IWR + prompt "Default Power Saving Mode" depends on PM - help - If you have a GPIO already configured as input with the corresponding PORTx_MASK - bit set - "Specify Wakeup Event by SIC_IWR value" + default PM_BFIN_SLEEP_DEEPER +config PM_BFIN_SLEEP_DEEPER + bool "Sleep Deeper" + help + Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic + power dissipation by disabling the clock to the processor core (CCLK). + Furthermore, Standby sets the internal power supply voltage (VDDINT) + to 0.85 V to provide the greatest power savings, while preserving the + processor state. + The PLL and system clock (SCLK) continue to operate at a very low + frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, + the SDRAM is put into Self Refresh Mode. Typically an external event + such as GPIO interrupt or RTC activity wakes up the processor. + Various Peripherals such as UART, SPORT, PPI may not function as + normal during Sleep Deeper, due to the reduced SCLK frequency. + When in the sleep mode, system DMA access to L1 memory is not supported. + +config PM_BFIN_SLEEP + bool "Sleep" + help + Sleep Mode (High Power Savings) - The sleep mode reduces power + dissipation by disabling the clock to the processor core (CCLK). + The PLL and system clock (SCLK), however, continue to operate in + this mode. Typically an external event or RTC activity will wake + up the processor. When in the sleep mode, + system DMA access to L1 memory is not supported. +endchoice -config PM_WAKEUP_GPIO_BY_SIC_IWR - bool "Specify Wakeup Event by SIC_IWR value" config PM_WAKEUP_BY_GPIO bool "Cause Wakeup Event by GPIO" -config PM_WAKEUP_GPIO_API - bool "Configure Wakeup Event by PM GPIO API" - -endchoice - -config PM_WAKEUP_SIC_IWR - hex "Wakeup Events (SIC_IWR)" - depends on PM_WAKEUP_GPIO_BY_SIC_IWR - default 0x8 if (BF537 || BF536 || BF534) - default 0x80 if (BF533 || BF532 || BF531) - default 0x80 if (BF54x) - default 0x80 if (BF52x) config PM_WAKEUP_GPIO_NUMBER int "Wakeup GPIO number" |