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| author | Tang Yuantian <yuantian.tang@freescale.com> | 2013-05-15 07:57:42 (GMT) |
|---|---|---|
| committer | Fleming Andrew-AFLEMING <AFLEMING@freescale.com> | 2013-05-17 00:59:05 (GMT) |
| commit | 22aa129f370428d35ff49f98ad7e6b842414a764 (patch) | |
| tree | 043b3bdd976d90b141a73c703cf5ef9707abc94f /arch/score/boot | |
| parent | c47024d3af17ce4ec80339ca819f442c986b6f54 (diff) | |
| download | linux-fsl-qoriq-22aa129f370428d35ff49f98ad7e6b842414a764.tar.xz | |
powerpc/mpc85xx: Update the clockgen node in dts
According to the e500mc hardware specification, the e500mc core
can run at e500mc core complex PLL/1, PLL/2.
So, for safety sake, we remove the PLL/4 on the platforms
p2041rdb, p3041ds and p5020ds which can take PLL/4 as input clock.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I9e8f68a8c8f8714e4c17a055949943ad8261f8f6
Reviewed-on: http://git.am.freescale.net:8181/2503
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Diffstat (limited to 'arch/score/boot')
0 files changed, 0 insertions, 0 deletions