diff options
| author | Chao Fu <B44548@freescale.com> | 2014-09-28 02:36:11 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:37:32 (GMT) |
| commit | 58bb64ef5ae667aad702dabd6929b56c9a5c0ed2 (patch) | |
| tree | 1756f858eec86296b0617752d0082566430d86d5 /drivers/mtd | |
| parent | 29875e3645e20e47cc6b0c05443b2ee37a58ff21 (diff) | |
| download | linux-fsl-qoriq-58bb64ef5ae667aad702dabd6929b56c9a5c0ed2.tar.xz | |
mtd: spi-nor: add DDR quad read support for Micron
This patch adds the DDR(or DTR) quad read support for the Micron
SPI NOR flash.
Tested with n25q256a.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: https://patchwork.kernel.org/patch/4075011/
Change-Id: Ib226886ff8d9e80d6aa5fb72dc86278188b2e3a3
Reviewed-on: http://git.am.freescale.net:8181/20131
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 792354a..67b6fce 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -856,6 +856,9 @@ static int set_ddr_quad_mode(struct spi_nor *nor, u32 jedec_id) return status; } return status; + case CFI_MFR_ST: /* Micron, actually */ + /* DTR quad read works with the Extended SPI protocol. */ + return 0; default: return -EINVAL; } @@ -1055,6 +1058,8 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, case SPI_NOR_DDR_QUAD: if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) { /* Spansion */ nor->read_opcode = SPINOR_OP_READ_1_4_4_D; + } else if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { + nor->read_opcode = SPINOR_OP_READ_1_1_4_D; } else { dev_err(dev, "DDR Quad Read is not supported.\n"); return -EINVAL; |