diff options
-rw-r--r-- | drivers/staging/tidspbridge/core/tiomap3430.c | 18 | ||||
-rw-r--r-- | drivers/staging/tidspbridge/core/tiomap3430_pwr.c | 126 | ||||
-rw-r--r-- | drivers/staging/tidspbridge/core/tiomap_io.c | 2 | ||||
-rw-r--r-- | drivers/staging/tidspbridge/rmgr/node.c | 4 |
4 files changed, 44 insertions, 106 deletions
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 48f1d7c..b8b320e 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -555,24 +555,18 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt, dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg; /*PM_IVA2GRPSEL_PER = 0xC0;*/ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA8)); + temp = readl(resources->dw_per_pm_base + 0xA8); temp = (temp & 0xFFFFFF30) | 0xC0; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) = - (u32) temp; + writel(temp, resources->dw_per_pm_base + 0xA8); /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + 0xA4)); + temp = readl(resources->dw_per_pm_base + 0xA4); temp = (temp & 0xFFFFFF3F); - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) = - (u32) temp; + writel(temp, resources->dw_per_pm_base + 0xA4); /*CM_SLEEPDEP_PER |= 0x04; */ - temp = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_base) + 0x44)); + temp = readl(resources->dw_per_base + 0x44); temp = (temp & 0xFFFFFFFB) | 0x04; - *((reg_uword32 *) ((u32) (resources->dw_per_base) + 0x44)) = - (u32) temp; + writel(temp, resources->dw_per_base + 0x44); /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */ (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c index 2b3ce64..384b833 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c +++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c @@ -430,12 +430,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) switch (clock_id) { case BPWR_GP_TIMER5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK; @@ -443,18 +439,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER6: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK; @@ -462,18 +452,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER7: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK; @@ -481,18 +465,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER8: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK; @@ -500,18 +478,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP1: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK; @@ -519,18 +491,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4); break; case BPWR_MCBSP2: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK; @@ -538,18 +504,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP3: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK; @@ -557,18 +517,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP4: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK; @@ -576,18 +530,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK; @@ -595,10 +543,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; } } diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index 3f6d084..4153eef 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c @@ -439,7 +439,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) omap_mbox_restore_ctx(dev_context->mbox); /* Access MMU SYS CONFIG register to generate a short wakeup */ - temp = *(reg_uword32 *) (resources->dw_dmmu_base + 0x10); + temp = readl(resources->dw_dmmu_base + 0x10); dev_context->dw_brd_state = BRD_RUNNING; } else if (dev_context->dw_brd_state == BRD_RETENTION) { diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c index d53d340..6bb65ea 100644 --- a/drivers/staging/tidspbridge/rmgr/node.c +++ b/drivers/staging/tidspbridge/rmgr/node.c @@ -623,9 +623,7 @@ func_cont: ul_gpp_mem_base = (u32) host_res->dw_mem_base[1]; off_set = pul_value - dynext_base; ul_stack_seg_addr = ul_gpp_mem_base + off_set; - ul_stack_seg_val = (u32) *((reg_uword32 *) - ((u32) - (ul_stack_seg_addr))); + ul_stack_seg_val = readl(ul_stack_seg_addr); dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr =" " 0x%x\n", __func__, ul_stack_seg_val, |