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path: root/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
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Diffstat (limited to 'drivers/staging/tidspbridge/core/tiomap3430_pwr.c')
-rw-r--r--drivers/staging/tidspbridge/core/tiomap3430_pwr.c126
1 files changed, 36 insertions, 90 deletions
diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
index 2b3ce64..384b833 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
@@ -430,12 +430,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
switch (clock_id) {
case BPWR_GP_TIMER5:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
@@ -443,18 +439,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER6:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
@@ -462,18 +452,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER7:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
@@ -481,18 +465,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_GP_TIMER8:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
@@ -500,18 +478,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP1:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_core_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_core_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
@@ -519,18 +491,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4);
break;
case BPWR_MCBSP2:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
@@ -538,18 +504,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP3:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
@@ -557,18 +517,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP4:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_per_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
@@ -576,18 +530,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
case BPWR_MCBSP5:
- iva2_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_core_pm_base) +
- 0xA8));
- mpu_grpsel = (u32) *((reg_uword32 *)
- ((u32) (resources->dw_core_pm_base) +
- 0xA4));
+ iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
+ mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4);
if (enable) {
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
@@ -595,10 +543,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK;
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK;
}
- *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8))
- = iva2_grpsel;
- *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4))
- = mpu_grpsel;
+ writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8);
+ writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
break;
}
}
generated by cgit v0.10.2 at 2024-08-20 19:30:35 (GMT)