diff options
| author | Nishanth Menon <nm@ti.com> | 2010-07-12 22:56:02 (GMT) |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-07-22 17:50:15 (GMT) |
| commit | 7124cb171108dea386b2c81334605da1d6f4554a (patch) | |
| tree | d4cb7637779e758e13c2a456cecad95523c50eea /drivers/staging/tidspbridge/core/tiomap3430_pwr.c | |
| parent | 2094f12d440c5a9fae032932266fa4a44135194c (diff) | |
| download | linux-fsl-qoriq-7124cb171108dea386b2c81334605da1d6f4554a.tar.xz | |
staging: tidspbridge: remove custom typedef reg_uword32
use readl, writel to get and set the register instead.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/tidspbridge/core/tiomap3430_pwr.c')
| -rw-r--r-- | drivers/staging/tidspbridge/core/tiomap3430_pwr.c | 126 |
1 files changed, 36 insertions, 90 deletions
diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c index 2b3ce64..384b833 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c +++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c @@ -430,12 +430,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) switch (clock_id) { case BPWR_GP_TIMER5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT5_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK; @@ -443,18 +439,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT5_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT5_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER6: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT6_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK; @@ -462,18 +452,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT6_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT6_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER7: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT7_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK; @@ -481,18 +465,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT7_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT7_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_GP_TIMER8: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_GPT8_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK; @@ -500,18 +478,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_GPT8_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_GPT8_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP1: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK; @@ -519,18 +491,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4); break; case BPWR_MCBSP2: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK; @@ -538,18 +504,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP2_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP2_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP3: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK; @@ -557,18 +517,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP3_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP3_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP4: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_per_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK; @@ -576,18 +530,12 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP4_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP4_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_per_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; case BPWR_MCBSP5: - iva2_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA8)); - mpu_grpsel = (u32) *((reg_uword32 *) - ((u32) (resources->dw_core_pm_base) + - 0xA4)); + iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8); + mpu_grpsel = readl(resources->dw_per_pm_base + 0xA4); if (enable) { iva2_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK; mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK; @@ -595,10 +543,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable) mpu_grpsel |= OMAP3430_GRPSEL_MCBSP5_MASK; iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP5_MASK; } - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA8)) - = iva2_grpsel; - *((reg_uword32 *) ((u32) (resources->dw_core_pm_base) + 0xA4)) - = mpu_grpsel; + writel(iva2_grpsel, resources->dw_per_pm_base + 0xA8); + writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4); break; } } |