summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-12-11crypto: testmgr - Fix DMA-API warningTadeusz Struk
With DMA-API debug enabled testmgr triggers a "DMA-API: device driver maps memory from stack" warning, when tested on a crypto HW accelerator. Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit 9bac019dad8098a77cce555d929f678e22111783) Change-Id: I709ed7e293287b840abb25de21cbe4b1732e8402 Reviewed-on: http://git.am.freescale.net:8181/17737 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11crypto: caam - Correct the dma mapping for sg tableRuchika Gupta
At few places in caamhash and caamalg, after allocating a dmable buffer for sg table , the buffer was being modified. As per definition of DMA_FROM_DEVICE ,afer allocation the memory should be treated as read-only by the driver. This patch shifts the allocation of dmable buffer for sg table after it is populated by the driver, making it read-only as per the DMA API's requirement. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit 1da2be33ad4c30a2b1d5fe3053b5b7f63e6e2baa) Change-Id: I485040b955e27772c20623f037e8a5167404c18d Reviewed-on: http://git.am.freescale.net:8181/17736 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11crypto: caam - Add definition of rd/wr_reg64 for little endian platformRuchika Gupta
CAAM IP has certain 64 bit registers . 32 bit architectures cannot force atomic-64 operations. This patch adds definition of these atomic-64 operations for little endian platforms. The definitions which existed previously were for big endian platforms. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit ef94b1d834aace7101de77c3a7c2631b9ae9c5f6) Change-Id: Ieb2e1cccb475f380f44735b6b6d633514e9ab3e3 Reviewed-on: http://git.am.freescale.net:8181/17735 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11crypto: caam - Configuration for platforms with virtualization enabled in CAAMRuchika Gupta
For platforms with virtualization enabled 1. The job ring registers can be written to only is the job ring has been started i.e STARTR bit in JRSTART register is 1 2. For DECO's under direct software control, with virtualization enabled PL, BMT, ICID and SDID values need to be provided. These are provided by selecting a Job ring in start mode whose parameters would be used for the DECO access programming. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit 17157c90a8abf9323ee2a3daac7ad9f696642dda) Conflicts: drivers/crypto/caam/ctrl.c drivers/crypto/caam/intern.h Change-Id: I8adb64fd4ba06f1007ae6838ad4f5b3ecd04bdc9 Reviewed-on: http://git.am.freescale.net:8181/17734 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11crypto: caam - Correct definition of registers in memory mapRuchika Gupta
Some registers like SECVID, CHAVID, CHA Revision Number, CTPR were defined as 64 bit resgisters. The IP provides a DWT bit(Double word Transpose) to transpose the two words when a double word register is accessed. However setting this bit would also affect the operation of job descriptors as well as other registers which are truly double word in nature. So, for the IP to work correctly on big-endian as well as little-endian SoC's, change is required to access all 32 bit registers as 32 bit quantities. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit eb1139cd437afadc63f58159c111e3f166bddb51) Conflicts: drivers/crypto/caam/ctrl.c Change-Id: I4b9e3c8a438e6ce485a09dd485a1c463ec38953a Reviewed-on: http://git.am.freescale.net:8181/17733 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11crypto: caam - Define setbits32() and clrbits32() for ARM in the Freescale ↵Victoria Milhoan (b42089)
CAAM driver The kernel defines setbits32() and clrbits32() macros only for Power-based architectures. This patch modifies the Freescale CAAM driver to add macros for use on ARM architectures. Signed-off-by: Victoria Milhoan (b42089) <vicki.milhoan@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> (cherry picked from commit 54fbc7392ac344cb94c44a2d8e1e0a16c950a5cd) Change-Id: Ia8065d9722bf5b7e60fd269d345b0b8c95ee96da Reviewed-on: http://git.am.freescale.net:8181/17732 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11crypto: caam - writel() arguments are swappedDan Carpenter
My guess is that this little endian configuration is never found in real life, but if it were then the writel() arguments are in the wrong order so the driver would crash immediately. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit f829e7a32c9434e31e565bc79f5804a7a984c10f) Change-Id: I8aa8e70dca9affa5da01b80e1968381beeb460eb Reviewed-on: http://git.am.freescale.net:8181/17731 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: add alias for the clockgen sysclk nodeJingchang Lu
This add an alias named sysclk for the sysclk node for fdt fixup procedure locating it uniquely. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I7e6bd6cb4d81fe44c73944be91cab3fe56810094 Reviewed-on: http://git.am.freescale.net:8181/19199 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11clk: ppc-corenet: rename to ppc-qoriq for better representionJingchang Lu
The IP is shared on PPC and ARM, rename it to qoriq for better represention. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ib02baa7731d9d1d9955ffde9860deb517d8d7ca8 Reviewed-on: http://git.am.freescale.net:8181/17836 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
2014-12-11tty: of_serial: add of support for Freescale 64-byte FIFO UARTJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I667cb31ce4b5e8f5c2a4c5f2b88e677eb991b9b3 Reviewed-on: http://git.am.freescale.net:8181/17834 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11clk: ppc-corenet: remove "fsl,sys-clock" compatible added by LS1Jingchang Lu
The "fixed-clock" could handle the sysclk node properly. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I1b7fdf0be4f19a32d14240566e17bae2152578d6 Reviewed-on: http://git.am.freescale.net:8181/17832 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: change sysclk compatible to "fixed-clock"Jingchang Lu
The sysclk could be well probed by "fixed-clock" compatible, no custom compatible is needed any more. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I17a21e20ced4304e716e5a9ba07ff56b2adb45a7 Reviewed-on: http://git.am.freescale.net:8181/17833 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: remove the tbi node from SoC level dtsJingchang Lu
remove the tbi node which will be added to boards level dts. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I1b7893526e63d0207637f2ae0576c9d5f62a6a06 Reviewed-on: http://git.am.freescale.net:8181/17829 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-twr: add aliases for enet phyJingchang Lu
This add aliases for enet phy to make it be found easily in u-boot on dynamically change the enet "phy-handle" and "phy-connection-type" property. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I60e19aa48856c9b9048415d1c8924b626d70332a Reviewed-on: http://git.am.freescale.net:8181/17831 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-qds: add tbi node and aliases for enet phyJingchang Lu
This move the tbi node to boards level device tree source. And add aliases for enet phy to make it be found easily by u-boot on dynamically change the enet "phy-handle" and "phy-connection-type" property. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I80748fdbbeab06cb5804128600369317dbececd6 Reviewed-on: http://git.am.freescale.net:8181/17830 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021AJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I2deac22e04a04c2523c7839d5974a41288e5bb2b Reviewed-on: http://git.am.freescale.net:8181/17837 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: change duart compatible to "fsl,16550-FIFO64"Jingchang Lu
this patch change the duart compatible to 64-byte FIFO mode. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I4d306671daed4262a6f354a3507304d82468c41d Reviewed-on: http://git.am.freescale.net:8181/17835 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: configs: add Freescale LS1021A initial defconfigJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ia3ba1dbeb66d4c929cfe19122d221a2af36377f8 Reviewed-on: http://git.am.freescale.net:8181/17838 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dmaengine: fsl-edma: add dma memcpy supportJingchang Lu
The eDMA channel support the mem2mem copy with the always on slot number 63. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
2014-12-11dmaengine: fsl-edma: swap 8-/16-bit registers offset in big-endian modeJingchang Lu
As the IP design, all 8-bit and 16-bit registers offset adddress should be swapped in big-endian mode opposite to little-endian mode. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
2014-12-11dmaengine: fsl-edma: fix dmamux index calculating errorJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream: https://patchwork.kernel.org/patch/4457391/
2014-12-11dma: fix eDMA driver as a subsys_initcallYuan Yao
Because of some driver base on DMA, changed the initcall order as subsys_initcall. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> --- This patch is pulled back from upstream: commit 8edc51c197b8f409bef7b21755254e6f3ce7ed23
2014-12-11dma: fsl-edma: fix static checker warning of NULL dereferenceJingchang Lu
The static checker reports following warning: drivers/dma/fsl-edma.c:732 fsl_edma_xlate() error: we previously assumed 'chan' could be null (see line 737) The changes of the loop cursor in the iteration may result in NULL dereference when dma_get_slave_channel failed but loop will continue. So use list_for_each_entry_safe() instead of list_for_each_entry() to against this. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> --- This patch is pulled back from upstream: commit 178c81e58e91559fd2c6b1cae43c8f573a2ead36
2014-12-11dma: Add Freescale eDMA engine driver supportJingchang Lu
Add Freescale enhanced direct memory(eDMA) controller support. This module can be found on Vybrid and LS-1 SoCs. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com> --- This patch is pulled back from upstream: commit d6be34fbd39b7d577d25cb4edec538e8990ba07c
2014-12-11tty: serial: fsl_lpuart: add 32-bit register interface supportJingchang Lu
This add the big-endian 32-bit register version LPUART support. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream: https://patchwork.kernel.org/patch/4544291/
2014-12-11dt-binding: fsl-lpuart: use exact SoC revision to document bindingJingchang Lu
use exact SoC revision instead of wildcard describing to make the binding more clearer. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream: https://patchwork.kernel.org/patch/4544291/
2014-12-11ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464481/
2014-12-11ARM: imx: Add initial support for Freescale LS1021AJingchang Lu
The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464451/
2014-12-11dt-bindings: arm: add Freescale LS1021A SoC specific devict tree bindingJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
2014-12-11ARM: dts: Add initial LS1021A TWR board dts supportJingchang Lu
Signed-off-by: Chen Lu <B46807@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464461/
2014-12-11ARM: dts: Add initial LS1021A QDS board dts supportJingchang Lu
Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464471/
2014-12-11ARM: dts: Add SoC level device tree support for LS1021AJingchang Lu
Add Freescale LS1021A SoC device tree support Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464491/
2014-12-11clk: ppc-corenet: Add CLK_OF_DECLARE supportJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
2014-12-11clk: ppc-corenet: Fix Section mismatch warningJingchang Lu
WARNING: drivers/built-in.o(.data+0x10258): Section mismatch in reference from the variable ppc_corenet_clk_driver to the (unknown reference) .init.rodata:(unknown) The variable ppc_corenet_clk_driver references the (unknown reference) __initconst (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch is pulled back from upstream: commit da788acb28386aa896224e784954bb73c99ff26c
2014-12-11ARM: call of_clk_init from default time_init handlerSebastian Hesselbarth
Most DT ARM machs require common clock providers initialized before timers. Currently, arch/arm machs use .init_time to call of_clk_init right before clocksource_of_init. This prevents to remove that callback and use the default one instead. This patch adds a call to of_clk_init() to the default .init_time callback for COMMON_CLK enabled machs to allow to remove custom callbacks where applicable. While at it, also reorder includes alphabetically. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- This patch is pulled back from upstream: commit 4178bac4f6e955869395b30246687d41183a5edb
2014-12-11powerpc/e6500: Work around erratum A-008139Scott Wood
Erratum A-008139 can cause duplicate TLB entries if an indirect entry is overwritten using tlbwe while the other thread is using it to do a lookup. Work around this by using tlbilx to invalidate prior to overwriting. To avoid the need to save another register to hold MAS1 during the workaround code, TID clearing has been moved from tlb_miss_kernel_e6500 until after the SMT section. Signed-off-by: Scott Wood <scottwood@freescale.com> (cherry picked from commit 48cd9b5d590aee1664170968a9eae068e36761eb) Change-Id: I34cc02219f9081dbf8ff7729677a995b7a8bb4c5 Reviewed-on: http://git.am.freescale.net:8181/19463 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-12-11Merge commit '60cce3da4a8393d1e15bf1a9dbe3956a8aaabbaf'Rich Schmitt
2014-12-11offline_port: fix dt parser for tx frame queuesMarian Cristian Rotariu
With the current implementation the user has the possibility to initialize some queues that exit the offline port. The format of the device tree format is: fsl,qman-frame-queues-egress = <base_id1 count1 ... base_idn countn>; fsl,qman-channel-ids-egress = <channel_id1 ... channel_idn>; Intuitively, the base_id1, count1 frame queues batch are placed in the channel_id1 QMan channel. Because the list_add() adds an entry at the beginning of the list, the map between the frame queues and their channel ID is reversed. This patch adds a particular entry at the end of the fq list using list_add_tail() function. Signed-off-by: Marian Cristian Rotariu <marian.rotariu@freescale.com> Change-Id: I8d3a2fd3c36f63d15837ffe90bf6e4e8b041a3e5 Reviewed-on: http://git.am.freescale.net:8181/20154 Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Tested-by: Marian Cristian Rotariu <marian.rotariu@freescale.com>
2014-10-19fmd: force port down when qbmi busyMandy Lavi
Change-Id: I17411cd51bb88c5294bbdf97b8bd18609a00a7f6 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/17708 Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com> Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Tested-by: Mandy Lavi <Mandy.Lavi@freescale.com>
2014-10-19fmd: add new dtsi file for fmanV3LMandy Lavi
Change-Id: I65f6c770784cdf4ff8e5a16283597aec86daee56 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/17428 Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com> Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Tested-by: Mandy Lavi <Mandy.Lavi@freescale.com>
2014-10-08fmd: add total-fifo-size attribute to binding docMandy Lavi
Change-Id: I1e757f85419d66bfca4bbf6d4097a871c3b68bc8 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/16878 Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Tested-by: Mandy Lavi <Mandy.Lavi@freescale.com>
2014-10-08dpaa_eth: accept minimum MTU of at least 68Madalin Bucur
RFC 791 states that the minimum MTU needs to be 68 in order to allow datagram forwarding without further fragmentation. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: I4f9602c49a5a9aaac0030f511a6abbf32954f82f Reviewed-on: http://git.am.freescale.net:8181/17073 Reviewed-by: Ruxandra Ioana Radulescu <ruxandra.radulescu@freescale.com>
2014-10-08dpaa_eth: add required and active PAUSE frame settingsCristian Bercaru
Because the pause frame settings of a MAC device are forced to false when the link goes half-duplex and cannot be restored if autonegotiation is disabled, this patch introduces 2 sets of settings: requested and active. Requested settings are introduced by the users, via user-space programs such as ethtool, whereas active settings reflect whether FMan truly enables/disables PAUSE frames on TX/RX. Requested settings can only be changed by the user. Active settings can be changed by events such as auto-negotiation or a change in link duplexity and are derived from requested settings. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: I5ea563614b28d6ba1827b571097861d39ff8751a Reviewed-on: http://git.am.freescale.net:8181/15553 Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-10-08dpaa_eth: change type of PAUSE frame settings to booleanCristian Bercaru
This patch changes the type of PAUSE frames settings to boolean because they only accept the values true/false. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: I6a3926054d4821f12937e96198c8435df38bf95c Reviewed-on: http://git.am.freescale.net:8181/15552 Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-10-08fmd: use proper return valueMadalin Bucur
Channel value is uint16_t, return adequate type. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: I4295b7f706e9db36ac9d6d02b8896fa11067f612 Reviewed-on: http://git.am.freescale.net:8181/18840 Reviewed-by: Marian Cristian Rotariu <marian.rotariu@freescale.com>
2014-10-08fmd: fix casting warningMandy Lavi
Coverity issue Change-Id: If0a7e1dffa09e3513b7ccb13a1dc09bf91056238 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/18831 Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Tested-by: Mandy Lavi <Mandy.Lavi@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-10-08dpaa_eth: add explicit cast where neededMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: I20f1609771d66778acfbbca65e6d0b8ceecb326a Reviewed-on: http://git.am.freescale.net:8181/19077 Reviewed-by: Marian Cristian Rotariu <marian.rotariu@freescale.com>
2014-10-08dpaa_eth: fix dpa_bp_drain()Madalin Bucur
The continue jumps to the end of the loop, condition is evaluated and if ret is not > 0 the loop ends. Setting ret to 1 to continue processing until pool is drained. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: If0acf0eba9e1fc814ef61b939d717819a48c7e29 Reviewed-on: http://git.am.freescale.net:8181/19071 Reviewed-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Reviewed-by: Marian Cristian Rotariu <marian.rotariu@freescale.com>
2014-10-08dpaa_eth: add explicit cast where neededMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: Idc795a681df8b11532e1fdbd2f18c365bfa8a671 Reviewed-on: http://git.am.freescale.net:8181/19007 Reviewed-by: Marian Cristian Rotariu <marian.rotariu@freescale.com>
2014-10-08dpaa_eth: add static qualifierMadalin Bucur
Add static qualifier for several functions. Change channel parameter type to uint16_t. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: I759e8174d9bfe915ee11f25f572160d33bf4a9d3 Reviewed-on: http://git.am.freescale.net:8181/18843 Reviewed-by: Marian Cristian Rotariu <marian.rotariu@freescale.com>
generated by cgit v0.10.2 at 2024-08-30 11:12:45 (GMT)