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Before entering deep sleep, interrupts should be masked. Or,
unexpected interrupts may block the process of deep sleep.
So, mask interrupts by the following steps:
1. Mask interrupts to RCPM
2. Disable the GIC
This will make deep sleep more stable.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I601062f8406324a308ef44491fed7cf479eaeba9
Reviewed-on: http://git.am.freescale.net:8181/39602
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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* set the bit 0 of the target address of long jump to 1 for THUMB mode
* compile the resume entry code in arm instruction set
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I01a96158ac39e14dcaebc7305b03eb277712011b
Reviewed-on: http://git.am.freescale.net:8181/23209
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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LS1 supports deep sleep feature that can switch off most parts of
the SoC when it is in deep sleep state.
The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
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Patch Sent Upstream
url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296411.html
Change-Id: If96ace364c21786cc88ea4979d7cbb4e177da0a2
Reviewed-on: http://git.am.freescale.net:8181/21920
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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