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2014-04-05powerpc/t104x: enable wakeup sourcesChenhui Zhao
Set the register IPPDEXPCR (IP Powerdown Exception Control Register) to enable IP blocks which work as wakeup source when sleep/deep sleep. Change-Id: Id95cb920cab90e12851995d039bd866e6388f8ae Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10711 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/t104x: fix typoChenhui Zhao
"fsl,p104xrdb-cpld" -> "fsl,t104xrdb-cpld" Change-Id: I30d83d1867022485008b48c3d7d601040b840621 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10710 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/pm: support deep sleep feature on T104xChenhui Zhao
T104x has deep sleep feature, which can switch off most parts of the SoC when it is in deep sleep mode. This way, it becomes more energy-efficient. The DDR controller will also be powered off in deep sleep. Therefore, the last stage (the latter part of fsl_dp_enter_low) will run without DDR access. This piece of code and related TLBs are prefetched in advance. Due to the different initialization code between 32-bit and 64-bit, they have seperate resume entry and precedure. The feature supports 32-bit and 64-bit kernel mode. Change-Id: I9b9b9188fdc67167030658b6cc1d0a1cbe7e2180 Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10709 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/85xx: support sleep feature on QorIQ SoCs with RCPMChenhui Zhao
In sleep mode, the clocks of e500 cores and unused IP blocks is turned off. The IP blocks which are allowed to wake up the processor are still running. The sleep mode is equal to the Standby state in Linux. Use the command to enter sleep mode: echo standby > /sys/power/state Change-Id: I1cf82fddc34a9c0ad3cb66ae554e5521805365e6 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10707 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/rcpm: add RCPM driverChenhui Zhao
There is a RCPM (Run Control/Power Management) in Freescale QorIQ series processors. The device performs tasks associated with device run control and power management. The driver implements some features: mask/unmask irq, enter/exit low power states, freeze time base, etc. There are two versions of register map in RCPM, which is specified by the compatible entry in the RCPM node of device tree. Change-Id: I113211311c7241df95f067103d0ed81ada26d2ed Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10706 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04powerpc/cache: add cache flush operation for various e500Chenhui Zhao
Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at init time. The callback function will flush all caches in the current cpu. Change-Id: Id6da30ac5490cac5f5669909df2152f0ee952086 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10705 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04powerpc/suspend: disable irq by hardware when suspendChenhui Zhao
In 64-bit mode, kernel just clears the irq soft-enable flag in struct paca_struct to disable external irqs. But, in the case of suspend, irqs should be disabled by hardware. Therefore, use hard_irq_disable() instead of local_irq_disable(). Change-Id: I743ec4971a9e1a9b5a3c2b463324588d48af65af Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10704 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03powerpc/e6500: remove rev1 defconfigScott Wood
The SDK no longer supports rev1. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ief0e72d5305b16f994df3beca58134dd96e8aff7 Reviewed-on: http://git.am.freescale.net:8181/10273 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03powerpc/e6500: Remove A-004801 workaroundScott Wood
The SDK no longer supports e6500 rev1. This reverts commit 38043080bb90f931efbe56a3f407c18206985f18 "powerpc/e6500: extend TLB miss lock to invalidations" and commit b9e282e1347b771b736a84e6b0a1048c551e6a6c "powerpc/e6500: add kconfig option for erratum A-004801" Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I749f497cbb6b96d045434065b869b253f01d6575 Reviewed-on: http://git.am.freescale.net:8181/10272 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03Revert "powerpc/mpc85xx/e6500: work around CPU erratum A-006198"Scott Wood
This reverts commit f4c0e693ccc3422c5b809e7cc8f59b7637e3b7ab. rev1 is no longer supported in the SDK, and the workaround for A-006198 conflicts with machine check support. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I64e1ce19eb59a6bba8649156597cc49ff9b62b1e Reviewed-on: http://git.am.freescale.net:8181/10271 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-01uio: add support to map SRAM to userspaceHou Zhiqiang
This driver config the L2 Cache to be SRAM mode and map the SRAM to user space. The size and the address of SRAM are passed in the U-boot command line as format: cache-sram=addr,size. Please notice that this driver is exclusive with config FSL_85XX_CACHE_SRAM. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Change-Id: Ib0433acd459413fec5f5218751b0db79309895fd Reviewed-on: http://git.am.freescale.net:8181/10295 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Po Liu <Po.Liu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31powerpc/mpic: supply a .disable callbackChenhui Zhao
Currently MPIC provides .mask, but not .disable. This means that effectively disable_irq() soft-disables the interrupt, and you get a .mask call if an interrupt actually occurs. I'm not sure if this was intended as a performance benefit (it seems common to omit .disable on powerpc interrupt controllers, but nowhere else), but it interacts badly with threaded/workqueue interrupts (including KVM reflection). In such cases, where the real interrupt handler does a disable_irq_nosync(), schedules defered handling, and returns, we get two interrupts for every real interrupt. The second interrupt does nothing but see that IRQ_DISABLED is set, and decide that it would be a good idea to actually call .mask. In the sleep case, disable all irqs of IP blocks using .disable() when entering sleep. Change-Id: I8f57e20a87acae115d0a8a006d31ffdedb42c295 Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10507 Reviewed-by: Yang Li <LeoLi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31powerpc: set the correct ksp_limit on ppc32 when switching to irq stackKevin Hao
Guenter Roeck has got the following call trace on a p2020 board: Kernel stack overflow in process eb3e5a00, r1=eb79df90 CPU: 0 PID: 2838 Comm: ssh Not tainted 3.13.0-rc8-juniper-00146-g19eca00 #4 task: eb3e5a00 ti: c0616000 task.ti: ef440000 NIP: c003a420 LR: c003a410 CTR: c0017518 REGS: eb79dee0 TRAP: 0901 Not tainted (3.13.0-rc8-juniper-00146-g19eca00) MSR: 00029000 <CE,EE,ME> CR: 24008444 XER: 00000000 GPR00: c003a410 eb79df90 eb3e5a00 00000000 eb05d900 00000001 65d87646 00000000 GPR08: 00000000 020b8000 00000000 00000000 44008442 NIP [c003a420] __do_softirq+0x94/0x1ec LR [c003a410] __do_softirq+0x84/0x1ec Call Trace: [eb79df90] [c003a410] __do_softirq+0x84/0x1ec (unreliable) [eb79dfe0] [c003a970] irq_exit+0xbc/0xc8 [eb79dff0] [c000cc1c] call_do_irq+0x24/0x3c [ef441f20] [c00046a8] do_IRQ+0x8c/0xf8 [ef441f40] [c000e7f4] ret_from_except+0x0/0x18 --- Exception: 501 at 0xfcda524 LR = 0x10024900 Instruction dump: 7c781b78 3b40000a 3a73b040 543c0024 3a800000 3b3913a0 7ef5bb78 48201bf9 5463103a 7d3b182e 7e89b92e 7c008146 <3ba00000> 7e7e9b78 48000014 57fff87f Kernel panic - not syncing: kernel stack overflow CPU: 0 PID: 2838 Comm: ssh Not tainted 3.13.0-rc8-juniper-00146-g19eca00 #4 Call Trace: The reason is that we have used the wrong register to calculate the ksp_limit in commit cbc9565ee826 (powerpc: Remove ksp_limit on ppc64). Just fix it. As suggested by Benjamin Herrenschmidt, also add the C prototype of the function in the comment in order to avoid such kind of errors in the future. Cc: stable@vger.kernel.org # 3.12 Reported-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Kevin Hao <haokexin@gmail.com>
2014-03-28dts b4/t4: Added generic ethernet node for oNIC and two oh portsVakul Garg
OH ports serve as tx/rx points for oNIC Signed-off-by: Sandeep Singh <sandeep@freescale.com> Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: I7896a19ea05f6b09ee8559e7a2895be9c8c0de3d Reviewed-on: http://git.am.freescale.net:8181/10007 Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com> Reviewed-by: Marian Cristian Rotariu <marian.rotariu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/dts: Add 1588 timer node for eTSECYangbo Lu
Add 1588 timer node in files: arch/powerpc/boot/dts/bsc9131rdb.dtsi arch/powerpc/boot/dts/bsc9132qds.dtsi arch/powerpc/boot/dts/p1010rdb.dtsi arch/powerpc/boot/dts/p1020rdb-pd.dtsi arch/powerpc/boot/dts/p1021rdb-pc.dtsi arch/powerpc/boot/dts/p1022ds.dtsi arch/powerpc/boot/dts/p1025twr.dtsi arch/powerpc/boot/dts/p2020rdb-pc.dtsi Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Change-Id: I8b402cb7cca0f97ccec2b3ee2e948dee833f98c1 Reviewed-on: http://git.am.freescale.net:8181/10400 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/booke64: Critical and machine check exception supportScott Wood
Add special state saving for critical and machine check exceptions. Most of this code could be used to handle debug exceptions taken from kernel space, but actually doing so is outside the scope of this patch. The various critical and machine check exceptions now point to their real handlers, rather than hanging the kernel. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Id3ef3d2c17b582508f36c10a4d0e96e540ca5284 Reviewed-on: http://git.am.freescale.net:8181/10269 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/booke64: Add crit/mc/debug support to EXCEPTION_COMMONScott Wood
Use the proper scratch SPRG and PACA region. Introduce level-specific macros to simplify usage and avoid needing to do a bunch of token pasting throughout EXCEPTION_COMMON(). Now that EXCEPTION_COMMON_DBG() is properly using the debug scratch register, there's no more need for the caller to move the value to the GEN scratch first. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I0abdf08d724e0238bdc1eee44bd5a72fa88f7b22 Reviewed-on: http://git.am.freescale.net:8181/10268 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/booke64: Remove ints from EXCEPTION_COMMONScott Wood
The ints parameter was used to optionally insert RECONCILE_IRQ_STATE into EXCEPTION_COMMON. However, since it came at the end of EXCEPTION_COMMON, there was no real benefit for it to be there as opposed to being called separately by the caller of EXCEPTION_COMMON. The ints parameter was causing some hassle when trying to add an extra macro layer. Besides avoiding that, moving "ints" to the caller makes the code simpler by: - avoiding the asymmetry where INTS_RESTORE_HARD is called separately by the individual exception, but INTS_DISABLE was not - removing the no-op INTS_KEEP - not having an unnecessary macro parameter It also turned out to be necessary to delay the INTS_DISABLE in the case of special level exceptions until after we saved the old value of PACAIRQHAPPENED. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I18dcc5f81c8fe7a830147e70eadebe64e2c4a218 Reviewed-on: http://git.am.freescale.net:8181/10267 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/booke64: Use SPRG_TLB_EXFRAME on bolted handlersScott Wood
While bolted handlers (including e6500) do not need to deal with a TLB miss recursively causing another TLB miss, nested TLB misses can still happen with crit/mc/debug exceptions -- so we still need to honor SPRG_TLB_EXFRAME. We don't need to spend time modifying it in the TLB miss fastpath, though -- the special level exception will handle that. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Cc: kvm-ppc@vger.kernel.org Change-Id: I56f8a4007275654a03e29010e7e64d70db46bf1c Reviewed-on: http://git.am.freescale.net:8181/10266 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/booke64: Use SPRG7 for VDSOScott Wood
Previously SPRG3 was marked for use by both VDSO and critical interrupts (though critical interrupts were not fully implemented). In commit 8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad ("powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int"), Mihai Caraman made an attempt to resolve this conflict by restoring the VDSO value early in the critical interrupt, but this has some issues: - It's incompatible with EXCEPTION_COMMON which restores r13 from the by-then-overwritten scratch (this cost me some debugging time). - It forces critical exceptions to be a special case handled differently from even machine check and debug level exceptions. - It didn't occur to me that it was possible to make this work at all (by doing a final "ld r13, PACA_EXCRIT+EX_R13(r13)") until after I made (most of) this patch. :-) It might be worth investigating using a load rather than SPRG on return from all exceptions (except TLB misses where the scratch never leaves the SPRG) -- it could save a few cycles. Until then, let's stick with SPRG for all exceptions. Since we cannot use SPRG4-7 for scratch without corrupting the state of a KVM guest, move VDSO to SPRG7 on book3e. Since neither SPRG4-7 nor critical interrupts exist on book3s, SPRG3 is still used for VDSO there. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Cc: Anton Blanchard <anton@samba.org> Cc: Paul Mackerras <paulus@samba.org> Cc: kvm-ppc@vger.kernel.org Change-Id: Ibc9f776435583a75c04e7662d5a863cae3b2ab6b Reviewed-on: http://git.am.freescale.net:8181/10265 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/e6500: Make TLB lock recursiveScott Wood
Once special level interrupts are supported, we may take nested TLB misses -- so allow the same thread to acquire the lock recursively. The lock will not be effective against the nested TLB miss handler trying to write the same entry as the interrupted TLB miss handler, but that's also a problem on non-threaded CPUs that lack TLB write conditional. This will be addressed in the patch that enables crit/mc support by invalidating the TLB on return from level exceptions. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I1c485fe78f289e038c318863f175b5fdc345afe6 Reviewed-on: http://git.am.freescale.net:8181/10264 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/booke64: Fix exception numbersScott Wood
altivec_unavailable was commented as 0xf20 but the code uses 0x200. Note that 0xf20 is also used by ap_unavailable. altivec_assist was commented as 0x1700 but the code uses 0x220. critical_input was commented as 0x580 but the code uses 0x100. machine_check was commented and implemented as 0x200, which conflicts with altivec_assist (it only builds because MC_EXCEPTION_PROLOG is commented out). Changed to the fixed IVOR value of 0x000. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Iddc30b69eb4aa8ab804f6023e2cf9e36105aa1d3 Reviewed-on: http://git.am.freescale.net:8181/10263 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/book3e: store crit/mc/dbg exception thread infoTiejun Chen
We need to store thread info to these exception thread info like something we already did for PPC32. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I4c41e2a6b7b9994a8f2015a175f8b5e5454af223 Reviewed-on: http://git.am.freescale.net:8181/10261 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/book3e: initialize crit/mc/dbg kernel stack pointersTiejun Chen
We already allocated critical/machine/debug check exceptions, but we also should initialize those associated kernel stack pointers for use by special exceptions in the PACA. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ide9ef2f6b0c1dc43041d908a923cabcd7fe5f492 Reviewed-on: http://git.am.freescale.net:8181/10260 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/mpic_timer: fix convert ticks to time subtraction overflowWang Dongsheng
In some cases tmp_sec may be greater than ticks, because in the process of calculation ticks and tmp_sec will be rounded. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I9bad7ea037144da4e1b3a00e6af52f8687f01ffe Reviewed-on: http://git.am.freescale.net:8181/10341 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/mpic_timer: fix the time is not accurate caused by GTCRR toggle bitWang Dongsheng
When the timer GTCCR toggle bit is inverted, we calculated the rest of the time is not accurate. So we need to ignore this bit. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I6b5228af46a31184b50b8feb7f5da64858fdc054 Reviewed-on: http://git.am.freescale.net:8181/10340 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/p1022ds: add a interrupt for rtc nodeWang Dongsheng
Add an external interrupt for rtc node. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ic3c180401a848ee6515912ab2ec6419fbc79b432 Reviewed-on: http://git.am.freescale.net:8181/10339 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-28powerpc/p1022ds: fix rtc compatible stringWang Dongsheng
RTC Hardware(ds3232) and rtc compatible string does not match. Change "dallas,ds1339" to "dallas,ds3232". Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Id86048db4f618ac4a97aec2d70c10404cface0b7 Reviewed-on: http://git.am.freescale.net:8181/10338 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-26T1040RDB/dts: Add UCC hdlc node for QUICC EngineZhao Qiang
T1040RDB don't have the UCC uart port, change UCC uart node to UCC hdlc node. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I5608746d9e31f1dd74b5574e6dd4f95963f0f8cb Reviewed-on: http://git.am.freescale.net:8181/10008 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10279
2014-03-26t1040qds/dts: Add qe node for t1040Zhao Qiang
add qe node into file arch/powerpc/boot/dts/fsl/t1040si-post.dtsi Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I7de5a4fe3c30130d3b00e3e9dd84a6193b38caf4 Reviewed-on: http://git.am.freescale.net:8181/10278 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/fsl-booke: Add T1042RDB_PI board supportPriyanka Jain
T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port Add support for T1040 RDB board: -add device tree -Add entry corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: If3b9122a044312ce458739883aafa65c2436e1e1 Reviewed-on: http://git.am.freescale.net:8181/10136 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/fsl-booke: Add initial T1040RDB board supportPriyanka Jain
T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Add support for T1040 RDB board: -add device tree -add entry in Kconfig to build -Add entry corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Signed-off-by: Alex MARGINEAN <alexandru.marginean@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: I74d0240522572912995754aecfc3b2d15a48f9fe Reviewed-on: http://git.am.freescale.net:8181/10135 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/fsl-booke: Add initial T104x_QDS board supportPriyanka Jain
T104xQDS board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI Express: supporting Gen 1 and Gen 2 - SGMII - QSGMII - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. - IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep (T1040 only) - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - Second port can be converted to OTG mini-AB - SD/MMC Interface - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC - Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - TDM - QE-TDM - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Add support for T104x QDS board (T1040QDS, T1042QDS): -add device tree -add entry is added in corenet_generic.c as it is similar to other corenet platforms. -add entry in Kconfig to build -add t1040_32bit_smp_defconfig, t1040_64bit_smp_defconfig -T1040 has FMANv3, hence CONFIG_FMAN_T4240 needs to be defined. -So corenet32_smp_defconfig and corenet64_smp_defconfig cannot be used. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Signed-off-by: Alex Marginean <alexandru.marginean@freescale.com> Signed-off-by: Razvan Stefanescu <razvan.stefanescu@freescale.com> Signed-off-by: Nikhil Badola <Nikhil.Badola@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: Icfd66c050fbbc39a8693e6b00550736fa9313e12 Reviewed-on: http://git.am.freescale.net:8181/10134 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-25powerpc/mpc85xx:Add T104x device tree supportPriyanka Jain
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA processor cores with high-performance data path acceleration architecture and network peripheral interfaces required for networking & telecommunications. T1042 personality is a reduced personality of T1040 without Integrated 8-port Gigabit Ethernet switch. The T1040/T1042 SoC includes the following function and features: - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration (SEC 5.0) - RegEx Pattern Matching Acceleration (PME 2.2) - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch (T1040 only) - Four 1 Gbps Ethernet controllers - Two RGMII interfaces or one RGMII and one MII interfaces - High speed peripheral interfaces - Four PCI Express 2.0 controllers running at up to 5 GHz - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation - Upto two QSGMII interface - Upto six SGMII interface supporting 1000 Mbps - One SGMII interface supporting upto 2500 Mbps - Additional peripheral interfaces - Two USB 2.0 controllers with integrated PHY - SD/eSDHC/eMMC - eSPI controller - Four I2C controllers - Four UARTs - Four GPIO controllers - Integrated flash controller (IFC) - LCD/ HDMI interface (DIU) with 12 bit dual data rate - TDM interface: QE, SLIC - Multicore programmable interrupt controller (PIC) - Two 8-channel DMA engines - Single source clocking implementation - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com> Signed-off-by: Alex Marginean <alexandru.marginean@freescale.com> Signed-off-by: Razvan Stefanescu <razvan.stefanescu@freescale.com> Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Ganga Negi <ganga.negi@freescale.com> Signed-off-by: Nikhil Badola <Nikhil.Badola@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Change-Id: Ib0a9e1a717080fd246b308a049f0f57beb4fe048 Reviewed-on: http://git.am.freescale.net:8181/10133 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24drivers/net: support hdlc function for QE-UCCZhao Qiang
The driver add hdlc support for Freescale QUICC Engine. It support NMSI and TSA mode. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: Iece969b4934241f0f1cb574c5014600ef63cfb95 Reviewed-on: http://git.am.freescale.net:8181/10113 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24t2080qds/dts: remove nand partitions in dtsShengzhou Liu
we use mtdparts way to setup the partitions of flash devices instead of putting partitions info in dts. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I74abccf2c32f5f4da8cccf4aec3a85814d4718af Reviewed-on: http://git.am.freescale.net:8181/10014 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24QE-TDM: add support to make QE-TDM work on 36bit physical addressJiucheng Xu
Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I3841888a780f6d4d3d38589c5de4cdd3916921ef Reviewed-on: http://git.am.freescale.net:8181/9214 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10110
2014-03-24Corenet: Add QE platform support for CorenetZhao Qiang
There is QE on platform T104x, add support. Call funcs qe_ic_init and qe_init if CONFIG_QUICC_ENGINE is defined. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I7d33f4237aabadfc63d4e55d96ebdb64fb396736 Reviewed-on: http://git.am.freescale.net:8181/10099 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24split function mpc85xx_qe_init() into two functions.Zhao Qiang
micro QE is a kind of cutted QE, it has only 2 UCCs while normal QE has up to 8 UCCs. micro QE doesn't have par_io, it doesn't need to init par_io for micro QE. Split function mpc85xx_qe_init() into mpc85xx_qe_init() and mpc85xx_qe_par_io_init(). Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I267d044d6b0c6ff1c4bba984566d430e6b3dc682 Reviewed-on: http://git.am.freescale.net:8181/10098 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/85xx: Add QE common init functionZhao Qiang
Define a QE init function in common file, and avoid the same codes being duplicated in board files. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I394c2eac02ef40fb923b5ee5f74e919065f8a4ac Reviewed-on: http://git.am.freescale.net:8181/10106 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/t4240: Change t4240 USB controller versionNikhil Badola
Change USB controller version to 2.5 in compatible string for T4240 rev2.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I92aa23cee236c13547b59bf62ef68f1d6002f2ff Reviewed-on: http://git.am.freescale.net:8181/9638 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/t2080: Change t2080 USB controller version Nikhil Badola
Change USB controller version to 2.5 in compatible string for T2080 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289 Reviewed-on: http://git.am.freescale.net:8181/7459 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit cd37bcac41666cccb7fdf84e475967630848d257) Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289 Reviewed-on: http://git.am.freescale.net:8181/9835 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21phy: add freescale XFI 10GBASE-KR driverShaohui Xie
To support freescale XFI 10GBASE-KR, the driver comply with IEEE802.3-2008 to do auto-negotiation and link training with link partner(LP) which has capability of 10GBASE-KR. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I1847226078017b4ca74a39f0d611a96f66921d23 Reviewed-on: http://git.am.freescale.net:8181/9918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Heinz Wrobel <Heinz.Wrobel@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/p1010rdb:update dts for pcie interrupt-mapZhao Qiang
p1010rdb-pb use the irq[4:5] for inta and intb to pcie, it is active-high, so set it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I29db41b4a8b5a67c18151099884edda6de4d9d1a Reviewed-on: http://git.am.freescale.net:8181/9915 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/p1010rdb:update mtd of nand to adapt to both old andZhao Qiang
new p1010rdb P1010rdb-pa and p1010rdb-pb have different mtd of nand. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Move the nand-mtd from p1010rdb.dtsi to p1010rdb-pa.dtsi. Modify p1010rdb-pb's nand-mtd, which can be overwrote from u-boot by set mtdparts. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I9e5652b9aa3136299bd6f8bbee529a153031240b Reviewed-on: http://git.am.freescale.net:8181/9914 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-19powerpc/mpc85xx: Add deep sleep support for IFCPrabhakar Kushwaha
Add support of suspend, resume function to support deep sleep. Also make sure of SRAM initialization during resume. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Change-Id: Ia3d484ff272d6c7feebb74a5ad95f74fb91cdd68 Reviewed-on: http://git.am.freescale.net:8181/9444 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 82a066c3f93441a7e80c1a603ff185ee4d16bf25) Reviewed-on: http://git.am.freescale.net:8181/9928
2014-03-18iommu/fsl: PAMU driver changes for DSP stasing support.Varun Sethi
Modifications to PAMU driver for supporting DSP stashing. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1462806c85f0f398a332ac321bb7b67a8cabc1bb Reviewed-on: http://git.am.freescale.net:8181/9617 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18e6500/defconfig: Enabled FSL_UIO_DMAVakul Garg
To enable direct access of DMA channels from user space, CONFIG_UIO_FSL_DMA needs to be turned on. User space DMA driver is used by applications using ipc and usdpaa sdk submodules. Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: Id874ead3d373281614f7638a52b1dc074a648ebe Reviewed-on: http://git.am.freescale.net:8181/9817 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Naveen Burmi <NaveenBurmi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18powerpc/p1010rdb:update dts to adapt to both old and new p1010rdbZhao Qiang
P1010rdb-pa and p1010rdb-pb have different phy interrupts. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I2e80e63576396a8fe726a6306246b16c25744cff Reviewed-on: http://git.am.freescale.net:8181/5607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9593 Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: add MSIX supportMinghuan Lian
1. The patch initializes MSIX trap outbound window, the application can map this window and trigger the MSIX interrupt. 2. The patch initializes MSIX inbound window which is used to store MSIX vector and PBA data. 3. Add sysfs node to display MSIX vector setting for example: # cat /sys/class/pci_ep/pci0-pf0/msix MSIX venctor 0: control:0x0 data:0x0000406c addr:0x00000000fee00000 MSIX venctor 1: control:0x0 data:0x0000407c addr:0x00000000fee00000 MSIX venctor 2: control:0x0 data:0x0000408c addr:0x00000000fee00000 MSIX venctor 3: control:0x0 data:0x0000409c addr:0x00000000fee00000 MSIX venctor 4: control:0x0 data:0x000040ac addr:0x00000000fee00000 MSIX venctor 5: control:0x0 data:0x00000000 addr:0x0000000000000000 MSIX venctor 6: control:0x0 data:0x00000000 addr:0x0000000000000000 MSIX venctor 7: control:0x0 data:0x00000000 addr:0x0000000000000000 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I18a6f9056b3c630bba91f5f1dfef2eee01995926 Reviewed-on: http://git.am.freescale.net:8181/9605 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
generated by cgit v0.10.2 at 2024-07-16 12:15:34 (GMT)