Age | Commit message (Collapse) | Author |
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Make sure the SPI Flash into reset state.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: I627606256571b80ba80a5a84a25b52685e799b0c
Reviewed-on: http://git.am.freescale.net:8181/36725
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
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Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
arch/arm/kvm/mmu.c
arch/arm/mm/proc-v7-3level.S
arch/powerpc/kernel/vdso32/getcpu.S
drivers/crypto/caam/error.c
drivers/crypto/caam/sg_sw_sec4.h
drivers/usb/host/ehci-fsl.c
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In case of interrupt arrive immediately after requesting irq,
kernel will panic due to uninitialized variable.
Fix below exception:
Unable to handle kernel NULL pointer dereference
at virtual address 00000000
pgd = 80003000
[00000000] *pgd=80000080004003, *pmd=00000000
Internal error: Oops: 206 [#1] SMP THUMB2
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.19-rt30+ #138
task: ef07c000 ti: ef080000 task.ti: ef080000
PC is at __swait_wake_locked+0x10/0x4e
LR is at complete+0x21/0x2e
pc : [<8002ee4a>] lr : [<8002f2bb>] psr: 400001b3
sp : ef081d00 ip : 0000001f fp : ef080000
r10: 00000001 r9 : 00000000 r8 : 00000003
r7 : ef0329ac r6 : 80000193 r5 : 00000000 r4 : ef0329ac
r3 : 00000000 r2 : 00000001 r1 : 00000003 r0 : ef0329ac
Flags: nZcv IRQs off FIQs on Mode SVC_32 ISA Thumb Segment kernel
Control: 70c53c7d Table: 80003000 DAC: 02851004
Process swapper/0 (pid: 1, stack limit = 0xef080248)
Stack: (0xef081d00 to 0xef082000)
1d00: ef0329ac ef0329a8 80000193 ef081d20
00000000 00000000 804c252c 8002f2bb
1d20: 80000000 804d6a13 ef3cc2c0 ef011c00
000000a3 801c3c1d 801c3bdb 8003b8b7
1d40: ef011c00 ef3cc2c0 802e1ed0 00000000
ef011c00 8049cd7c 00000000 ef081de4
1d60: 803f6b32 815115d0 804c252c 8003b9b9
00000000 ef011c00 8049cd7c 8003d5cf
1d80: 000000a3 8003b3fb 000000a3 8000ca3d
f0002000 ef081db0 804a8c8c 800083df
1da0: 802e1ed0 00000133 ffffffff 802e245b
804fd8fc 60000113 00000066 00001dc5
1dc0: 804fd8fc 60000113 00000000 00000000
803f6b32 815115d0 804c252c ef080000
1de0: 0000001f ef081df8 8023cb13 802e1ed0
00000133 ffffffff ef032010 ef005e10
1e00: ef005e00 00000000 00000000 8023cb23
f02c0000 801c4123 00000000 ef111280
1e20: ef032010 ef3caf40 ef3caf40 800b44ff
ef07c000 00000000 ef3caf40 ef111300
1e40: ef269f80 800b4b37 804c256c 8023cce7
ef063684 00000003 ef111300 00000000
1e60: 804fbbd4 ef005e10 00000000 ef005e10
ef005e44 804fbbd4 804c2364 80482039
1e80: 000000ad 00000000 ef080000 80198371
ef005e10 ef005e44 804c2364 00000000
1ea0: 80482039 801984a5 00000000 804c2364
80198471 8019742d ef06365c ef110434
1ec0: 804c2364 804bfb30 ef269f80 80197e3b
803f6bae 803f6bb3 00000071 804c2364
1ee0: 80490ad0 8049b374 804d6d40 8019882d
00000000 00000006 80490ad0 800085f5
1f00: ef105300 ef105580 00000000 ef105580
802ea500 803d4d54 00000000 800aeae1
1f20: 804ae908 00000113 80471461 815188d2
815188da 80028f35 00000000 80447320
1f40: 00000000 000000ad 00000006 00000006
00000001 00000006 80490ad0 8049b374
1f60: 804d6d40 804d6d40 000000ad 80490adc
00000000 8047192d 00000006 00000006
1f80: 80471461 00000000 00000000 802db775
00000000 00000000 00000000 00000000
1fa0: 00000000 802db77b 00000000 8000c219
00000000 00000000 00000000 00000000
1fc0: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
1fe0: 00000000 00000000 00000000 00000000
00000013 00000000 deadbeef deadbeef
[<8002ee4a>] (__swait_wake_locked+0x10/0x4e)
from [<8002f2bb>] (complete+0x21/0x2e)
[<8002f2bb>] (complete+0x21/0x2e)
from [<801c3c1d>] (fsl_qspi_irq_handler+0x43/0x46)
[<801c3c1d>] (fsl_qspi_irq_handler+0x43/0x46)
from [<8003b8b7>] (handle_irq_event_percpu+0x33/0x104)
[<8003b8b7>] (handle_irq_event_percpu+0x33/0x104)
from [<8003b9b9>] (handle_irq_event+0x31/0x48)
[<8003b9b9>] (handle_irq_event+0x31/0x48)
from [<8003d5cf>] (handle_fasteoi_irq+0x6b/0xa4)
[<8003d5cf>] (handle_fasteoi_irq+0x6b/0xa4)
from [<8003b3fb>] (generic_handle_irq+0x13/0x1c)
[<8003b3fb>] (generic_handle_irq+0x13/0x1c)
from [<8000ca3d>] (handle_IRQ+0x3d/0x60)
[<8000ca3d>] (handle_IRQ+0x3d/0x60)
from [<800083df>] (gic_handle_irq+0x2b/0x44)
[<800083df>] (gic_handle_irq+0x2b/0x44)
from [<802e245b>] (__irq_svc+0x3b/0x5c)
Exception stack(0xef081db0 to 0xef081df8)
1da0: 804fd8fc 60000113 00000066 00001dc5
1dc0: 804fd8fc 60000113 00000000 00000000
803f6b32 815115d0 804c252c ef080000
1de0: 0000001f ef081df8 8023cb13 802e1ed0 00000133 ffffffff
[<802e245b>] (__irq_svc+0x3b/0x5c)
from [<802e1ed0>] (_raw_spin_unlock_irqrestore+0x16/0x18)
[<802e1ed0>] (_raw_spin_unlock_irqrestore+0x16/0x18)
from [<8023cb13>] (of_find_property+0x29/0x32)
[<8023cb13>] (of_find_property+0x29/0x32)
from [<8023cb23>] (of_get_property+0x7/0xc)
[<8023cb23>] (of_get_property+0x7/0xc)
from [<801c4123>] (fsl_qspi_probe+0x197/0x5b0)
[<801c4123>] (fsl_qspi_probe+0x197/0x5b0)
from [<80198371>] (driver_probe_device+0x65/0x140)
[<80198371>] (driver_probe_device+0x65/0x140)
from [<801984a5>] (__driver_attach+0x35/0x48)
[<801984a5>] (__driver_attach+0x35/0x48)
from [<8019742d>] (bus_for_each_dev+0x3b/0x46)
[<8019742d>] (bus_for_each_dev+0x3b/0x46)
from [<80197e3b>] (bus_add_driver+0x8b/0x164)
[<80197e3b>] (bus_add_driver+0x8b/0x164)
from [<8019882d>] (driver_register+0x4b/0x76)
[<8019882d>] (driver_register+0x4b/0x76)
from [<800085f5>] (do_one_initcall+0x65/0xd4)
[<800085f5>] (do_one_initcall+0x65/0xd4)
from [<8047192d>] (kernel_init_freeable+0xbd/0x150)
[<8047192d>] (kernel_init_freeable+0xbd/0x150)
from [<802db77b>] (kernel_init+0x7/0x90)
[<802db77b>] (kernel_init+0x7/0x90)
from [<8000c219>] (ret_from_fork+0x11/0x38)
Code: 4607 4688 4692 46a9 (681e) 1f1c
---[ end trace 2857aa3b399c215c ]---
Kernel panic - not syncing: Fatal exception in interrupt
CPU1: stopping
CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 3.12.19-rt30+ #138
[<80010829>] (unwind_backtrace+0x1/0x88)
from [<8000e53b>] (show_stack+0xb/0xc)
[<8000e53b>] (show_stack+0xb/0xc)
from [<802df461>] (dump_stack+0x4d/0x60)
[<802df461>] (dump_stack+0x4d/0x60)
from [<8000ff23>] (handle_IPI+0x7f/0xd0)
[<8000ff23>] (handle_IPI+0x7f/0xd0)
from [<800083ef>] (gic_handle_irq+0x3b/0x44)
[<800083ef>] (gic_handle_irq+0x3b/0x44)
from [<802e245b>] (__irq_svc+0x3b/0x5c)
Exception stack(0xef09bfa0 to 0xef09bfe8)
bfa0: ffffffed 00000000 01087000 00000000
ef09a000 ef09a010 80000000 804d7054
bfc0: 80003010 410fc075 00000000 00000000
00000008 ef09bfe8 8000cc21 8000cc22
bfe0: 60000133 ffffffff
[<802e245b>] (__irq_svc+0x3b/0x5c)
from [<8000cc22>] (arch_cpu_idle+0x1a/0x20)
[<8000cc22>] (arch_cpu_idle+0x1a/0x20)
from [<8003b395>] (cpu_startup_entry+0x7d/0xc4)
[<8003b395>] (cpu_startup_entry+0x7d/0xc4)
from [<80008485>] (__enable_mmu+0x1/0x1c)
Signed-off-by: Haikun Wang <b53464@freescale.com>
Change-Id: If47a75274ae794a504cee0fca02920c9af1a29c1
Reviewed-on: http://git.am.freescale.net:8181/30121
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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For the QuadSPI SPI NOR flash driver, quad reading is used. This patch will
add quad reading support for ST's flash n25q128a13 on LS1021A TWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: Icf3c1334825fb9a0fe957bc6b75fa4dfd54c6960
Reviewed-on: http://git.am.freescale.net:8181/24670
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Add the addr_width information of spi_nor delivery to SPI controller.
For the Freescale eSPI controller, the address width is needed to do
the correct operations.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: I6c3afe1ceab7d792ceaba0a2c94d2baac1ecbe56
Reviewed-on: http://git.am.freescale.net:8181/24585
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Add the rescanning and initialization of SPI flash, to make the SPI
flash in the correct state. Because if the Power Management system
truns off power supply for SPI flash when system suspending, the SPI
flash will return to the reset state after system resume.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: Ifa38f33f894ab43ce99cb8848e40c2193c0c1aa6
Reviewed-on: http://git.am.freescale.net:8181/24154
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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As subpage write is enabled by default for all drivers, nand_write_subpage_hwecc
causes a crash if the driver did not register ecc->hwctl or ecc->calculate.
This behavior was introduced in
commit 837a6ba4f3b6d23026674e6af6b6849a4634fff9
"mtd: nand: subpage write support for hardware based ECC schemes".
This fixes a crash by emulating subpage write support by padding sub-page data
with 0xff on either sides to make it full page compatible.
Reported-by: Helmut Schaa <helmut.schaa@googlemail.com>
Tested-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Cc: <stable@vger.kernel.org> # 3.10.x+
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit f034d87def51f026b735d1e2877e9387011b2ba3)
Change-Id: I55b0ea1eea0ffdfa6410d0a239e2a773bfdd490d
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/20798
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Some new Micron SPI N25Q512 chips require reading the flag
status register to determine when operations have completed.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Change-Id: I52a87e1ae55da75248108d6db39f027318bacf22
Reviewed-on: http://git.am.freescale.net:8181/22632
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Nand driver miss a depend, so add depends on MEMORY.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Ia6d25836dff0f513eb63ee7089626f2728d26f3f
Reviewed-on: http://git.am.freescale.net:8181/22414
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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IFC registers can be of type Little Endian
or big Endian depending upon Freescale SoC.
Here SoC defines the register type of
IFC IP.So update accessors functions with
common IFC accessors functions to take
care both type of endianness.
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
---
This patch is under reviewing at url - https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg741449.html
Change-Id: Ib6d4669a94afa50e71ce522a008232fa21b0bc19
Reviewed-on: http://git.am.freescale.net:8181/20971
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Freescale IFC controller has been used for mpc8xxx.
It will be used for ARM-based SoC as well. This patch
moves the driver to driver/memory and fix the header
file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall()
to make sure this module has been loaded before
MTD partition parsing starts.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Cherry-picked from:d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc
Change-Id: I3cc83c716adf27a4988b818d57706980dbbefdea
Reviewed-on: http://git.am.freescale.net:8181/20970
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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FSL Quadspi module register bitwise is big-endian, but on ohter paltform
is little endian.
Add functions for Quadspi register read/write for bitwise:
qspi_readl
qpsi_writel
Add devtype for LS1021:
struct fsl_qspi_devtype_data ls1_data
Signed-off-by: Chao Fu <B44548@freescale.com>
The upstream status of this patch can be found at: http://patchwork.ozlabs.org/patch/399388/
Change-Id: Ib1a8bc11a52e8d9bb1021c8956a5783d3915de2e
Reviewed-on: http://git.am.freescale.net:8181/20296
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Currently, we read 5 bytes for ID, but s25fl128s has the same ext_id(0x4d01)
with s25fl129p1. The s25fl128s can support the DDR Quad read, while s25fl129p1
does not. So we have to distinguish the two NOR flashs.
This patch reads out 6 bytes for the ID, and use the 6 bytes ID to search the
right flash_info.
The detail of the patch is:
[1] change the "ext_id" from u16 to u32.
We can store two bytes or three bytes with the @ext_id now.
[2] search the right flash_info with the 6byte ID and the new @ext_id.
We use "matched" variable to track the legacy two bytes @ext_id.
If the flash_info's @ext_id is three bytes, we will use the
sixth byte of the ID to check it.
[3] add the new item to spi_nor_ids for s25fl128s.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: http://patchwork.ozlabs.org/patch/353244/
Change-Id: Id27774eefbf9e1a8f80e1dcd8fb0d3f9363923c1
Reviewed-on: http://git.am.freescale.net:8181/20134
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add DDR quad read opcode and LUT sequence for Micron N25Q256A.
The performace :
=================================================
mtd_speedtest: MTD device: 1
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 33554432, eraseblock size 65536,
page size 512, count of eraseblocks 512, pages per eraseblock 128, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 2426 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 32157 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 2362 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17741 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 2384 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 24058 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 1927529 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 2184533 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 2184533 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: finished
=================================================
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: https://patchwork.kernel.org/patch/4075001/
Change-Id: Ice094cec23114af5cda5dd4b24c3b2e60719fd6a
Reviewed-on: http://git.am.freescale.net:8181/20132
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds the DDR(or DTR) quad read support for the Micron
SPI NOR flash.
Tested with n25q256a.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: https://patchwork.kernel.org/patch/4075011/
Change-Id: Ib226886ff8d9e80d6aa5fb72dc86278188b2e3a3
Reviewed-on: http://git.am.freescale.net:8181/20131
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the DDR quad read support for the fsl-quadspi driver.
Check the "spi-nor,ddr-quad-read-dummy" DT property, if the DT node is exit,
it means we could enable the DDR quad read.
(1) Test this patch with imx6sx-sdb board (Spansion s25fl128s)
The clock rate is 66MHz.
(2) The information of NOR flash:
-----------------------------------------------
root@imx6qdlsolo:~# mtdinfo /dev/mtd0
mtd0
Name: 21e4000.qspi
Type: nor
Eraseblock size: 65536 bytes, 64.0 KiB
Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB)
Minimum input/output unit size: 1 byte
Sub-page size: 1 byte
Character device major/minor: 90:0
Bad blocks are allowed: false
Device is writable: true
-----------------------------------------------
(3) Test this patch set with UBIFS & bonnie++:
-----------------------------------------------
ubiattach /dev/ubi_ctrl -m 0
ubimkvol /dev/ubi0 -N test -m
mount -t ubifs ubi0:test tmp
bonnie++ -d tmp -u 0 -s 10 -r 5
-----------------------------------------------
(4) Test this patch with mtd_speedtest.ko
root@imx6qdlsolo:~# insmod mtd_speedtest.ko dev=0
=================================================
mtd_speedtest: MTD device: 0
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 16777216, eraseblock size 65536, page size 512,
count of eraseblocks 256, pages per eraseblock 128, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 665 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 49799 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 662 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 24236 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 657 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 32637 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 518 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 506 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 503 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 501 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 498 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 496 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 495 KiB/s
mtd_speedtest: finished
=================================================
(5) Conclusion:
The DDR quad read could be 49799 KiB/s.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074991/
Change-Id: I80c58bec32659d375c4656402e0c3d3ce3ba2e55
Reviewed-on: http://git.am.freescale.net:8181/20130
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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We can get the read/write/erase opcode from the spi nor framework now.
What's more is that we can get the correct dummy cycles.
This patch uses the information stored in the spi_nor{} to remove the
hardcode in the fsl_qspi_init_lut().
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found: https://patchwork.kernel.org/patch/4074971/
Change-Id: I32f982872df1729582f4122ac0dede934d749a04
Reviewed-on: http://git.am.freescale.net:8181/20129
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds the DDR quad read support by the following:
[1] add SPI_NOR_DDR_QUAD read mode.
[2] add DDR Quad read opcodes:
SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D
[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
Currently it only works for Spansion NOR.
[3] about the dummy cycles.
We set the dummy with 8 for DDR quad read by default.
The m25p80.c can not support the DDR quad read, but the SPI NOR controller
can set the dummy value in its child DT node, and the SPI NOR framework
can parse it out.
Test this patch for Spansion s25fl128s NOR flash.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074961
Change-Id: Id67e247e357bdd8bea99816e31f603898671d968
Reviewed-on: http://git.am.freescale.net:8181/20125
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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serial_flash_cmds.h defines our opcodes a little differently. Let's
borrow its naming, since it's borrowed from the SFDP standard, and it's
more extensible.
This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode
listing.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
(cherry picked from commit 58b89a1f4c2a65b10b8f7b90b6ff2161b19bb0d1)
Change-Id: Id3eff06b36acaa388d2581af59abc569c6a7f474
Reviewed-on: http://git.am.freescale.net:8181/20058
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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We need the SPI NOR child node to store some specific features, such as the
dummy cycles for the DDR Quad read.
But now, we only have the @dev field in the spi_nor{}. The @dev may points to a
spi_device{} for m25p80, while it may points to a platform_deivice{} for the
SPI NOR controller, such as fsl_quadspi.c.
It is not convenient for us to get come information from the SPI NOR flash.
This patch adds a new field @np to spi_nor{}, it points to the child node for
the SPI NOR flash.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The patch was pending at: https://patchwork.kernel.org/patch/4074931/
Change-Id: I0613744ca972ddc7481d82488d3e4c4e74c67652
Reviewed-on: http://git.am.freescale.net:8181/20057
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8.
The dummy cycles is actually 8 for SPI fast/dual/quad read.
This patch makes preparations for the DDR quad read, it fixes the wrong dummy
value for both the spi-nor.c and m25p80.c.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074921/
Change-Id: I7ca208d1964812f77f66708c659d826c39baff4d
Reviewed-on: http://git.am.freescale.net:8181/20056
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Commit 03e296f613affcc2671c1e86d8c25ecad867204e ("mtd: m25p80: use the SPI
nor framework") accidentally removed support for Dual SPI read transfers.
Add it back.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 8848e161b79421e340bb13facc11d89570b77940)
Change-Id: Ia4651487c4ca9f76063c7ec2bb8e04644e21b1df
Reviewed-on: http://git.am.freescale.net:8181/20055
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Qualify these with a better namespace, and prepare them for use in more
drivers.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
(cherry picked from commit b02e7f3ef0beb72da8fc64542f0ac977996ec56b)
Change-Id: I50fac2cb23653825b2f8e3ac65dd0ecb35eaf78b
Reviewed-on: http://git.am.freescale.net:8181/20054
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use the new SPI nor framework, and rewrite the m25p80:
(0) remove all the NOR comands.
(1) change the m25p->command to an array.
(2) implement the necessary hooks, such as m25p80_read/m25p80_write.
Tested with the m25p32.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[Brian: rebased]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 03e296f613affcc2671c1e86d8c25ecad867204e)
Change-Id: I8ac0159ab3d572cd12bdc1e5b2b6e6c5057b8359
Reviewed-on: http://git.am.freescale.net:8181/20053
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 6f7db7f3203a0bd48170807adeb53dd401d29110)
Change-Id: I84a2d2385c1196c943d9d6558cedded87885e4f8
Reviewed-on: http://git.am.freescale.net:8181/20052
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit bec44c45c245b38662f1e61bf0bde95fac1e7fb5)
Change-Id: Id9363959c57004a211d216c745c9584da8d2cdd0
Reviewed-on: http://git.am.freescale.net:8181/20051
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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For slightly better readability.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit b2fda1296bb8e213a6bad3937326ae98c4c4773c)
Change-Id: Ifadc84eb60ed11bf59c47691cfe58b6a5ecb2274
Reviewed-on: http://git.am.freescale.net:8181/20050
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>. Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
[Brian: dropped one incorrect hunk]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 3ea5b037e750274659648b58fb97426566a90373)
Change-Id: I9e527be3d3783b665bb659e5e2c977bd4f2b64cc
Reviewed-on: http://git.am.freescale.net:8181/20049
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Spansion s25fl256s1 and s25fl512s support Dual SPI transfers, hence set the
M25P80_DUAL_READ flag.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit f5e00838e83f6fc93f42c7a01b0c612031955b31)
Change-Id: I2e154cafc4e97d1663432bd160d2ec3fc3b98636
Reviewed-on: http://git.am.freescale.net:8181/20048
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add support for Dual SPI read transfers, which is supported by some
Spansion SPI FLASHes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit dbbafb74239e8296bc20f86366b3f38e13650900)
Change-Id: Ic69dfc56d0cd556ee00ab2181d4a88709929d56f
Reviewed-on: http://git.am.freescale.net:8181/20047
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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When using the Quad Read opcode, SPI masters still use Single SPI
transfers, as spi_transfer.rx_nbits defaults to SPI_NBITS_SINGLE.
Use SPI_NBITS_QUAD to fix this.
While an earlier version of commit 3487a63955c34ea508bcf4ca5131ddd953876e2d
("drivers: mtd: m25p80: add quad read support") did this correctly, it was
forgotten in the version that got merged.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 464e906737d6eba2fe63e913e0df4306423b4f61)
Change-Id: Idff0abef064a56cb91958b475359ae0f663efdc0
Reviewed-on: http://git.am.freescale.net:8181/20046
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Spansion s25fl512s supports Quad SPI transfers, hence set the
M25P80_QUAD_READ flag.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit d8d5d10d0f27d1975e71617efff941321a0dc142)
Change-Id: I85800faa7ea1eff351d5e13f11e2f61ee7bb4380
Reviewed-on: http://git.am.freescale.net:8181/20045
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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In the following commit (in -next):
commit 8552b439aba7f32063755d23f79ca27b4d0a3115
drivers: mtd: m25p80: convert "bool" read check into an enum
We converted the boolean 'fast_read' property to become an enum
'flash_read', but at the same time, we changed the conditional path so
that it doesn't choose a default value in some cases (technically, we
choose the correct default simply by virtue of devm_kzalloc(), which
zeroes this out to be a NORMAL read operation, but still...).
Fix this by setting a default for the 'else' clause.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 99ed1a167578f85963a0cdf5fd7b2291eaecc400)
Change-Id: Ic0d5d184ad7cf702a6027271a2a5388b37a1a0ca
Reviewed-on: http://git.am.freescale.net:8181/20044
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add
quad read support") in -next added both the 3-byte OPCODE_QUAD_READ and the
4-byte OPCODE_QUAD_READ_4B, but incorrectly uses OPCODE_QUAD_READ for both
3-byte and 4-byte addressing.
Use OPCODE_QUAD_READ_4B in the 4-byte case to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 7587f64d546d6a05dab0a7d1ac964e7ac12072f0)
Change-Id: I94b049c4e645600e8b692e835f1eb427b1292ab1
Reviewed-on: http://git.am.freescale.net:8181/20043
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add support for Micron m25px16 spi flash chip.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 574926c5bc3d787bb0b935b99d8825b3199ba76b)
Change-Id: Id66a4ca5be6ff4b6ea9debbb0eeba372ceafbb69
Reviewed-on: http://git.am.freescale.net:8181/20042
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Some flash also support quad read mode. Adding support for quad read
mode in m25p80 for Spansion and Macronix flash.
[Tweaked by Brian]
With this patch, quad-read support will override fast-read and
normal-read, if the SPI controller and flash chip both support it.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 3487a63955c34ea508bcf4ca5131ddd953876e2d)
Change-Id: Ib5ea483806cb7237bc23d4219626a198b09aecce
Reviewed-on: http://git.am.freescale.net:8181/20041
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This is a cleanup prior to adding quad read support. This will facilitate
easy addition of more read commands check under an enum rather that defining a
separate bool for it.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 8552b439aba7f32063755d23f79ca27b4d0a3115)
Change-Id: I9c8d509ef64ff555c22bde09bf13f74b65655f4d
Reviewed-on: http://git.am.freescale.net:8181/20040
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Device removal should fail if MTD unregistration fails.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 9650b9bec61d861b6b59d09eb389410b05d196e4)
Change-Id: Ia597ef093f4d1492f9d04c4a7bbaa5be32e5d161
Reviewed-on: http://git.am.freescale.net:8181/20039
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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A new 32Mbit SPI NOR flash from Macronix. Nothing special.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 5ff14821a37c92d139181c3fbc939afa993b959f)
Change-Id: I677b8981e01bbdc7496b86674ab56749959edbeb
Reviewed-on: http://git.am.freescale.net:8181/20038
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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It seems like the following commit was never necessary
commit 5f949137952020214cd167093dd7be448f21c079
Author: Shaohui Xie <Shaohui.Xie@freescale.com>
Date: Fri Oct 14 15:49:00 2011 +0800
mtd: m25p80: don't probe device which has status of 'disabled'
because it duplicates the code in of_platform_device_create_pdata()
which ensures that 'disabled' nodes are never instantiated.
Also, drop the __maybe_unused.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: <devicetree@vger.kernel.org>
(cherry picked from commit dc525ff4705cee2291b1637a650489aca86ac937)
Change-Id: I01e898a2d0cbf26e144e498eea6b0eec53c5cfdf
Reviewed-on: http://git.am.freescale.net:8181/20037
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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No change in the table data.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
(cherry picked from commit 6e5d9bda27000c682a9b38f0466941007e295f82)
Change-Id: I295d6300994b0a7f852cc4a2dcd3441bf2f813cb
Reviewed-on: http://git.am.freescale.net:8181/20035
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Remove the compile-time option for FAST_READ, since we have run-time
support for detecting it. This refactors the logic for enabling
fast-read, such that for DT-enabled devices, we honor the
"m25p,fast-read" property but for non-DT devices, we default to using
FAST_READ whenever the flash device supports it.
Normal READ and FAST_READ differ only in the following:
* FAST_READ supports SPI higher clock frequencies [1]
* number of dummy cycles; FAST_READ requires 8 dummy cycles (whereas
READ requires 0) to allow the flash sufficient setup time, even when
running at higher clock speeds
Thus, for flash chips which support FAST_READ, there is otherwise no
limiting reason why we cannot use the FAST_READ opcode instead of READ.
It simply allows the SPI controller to run at higher clock rates. So
theoretically, nobody should be needing the compile-time option anyway.
[1] I have a Spansion S25FL128S datasheet which says:
"The maximum operating clock frequency for the READ command is 50
MHz."
And:
"The maximum operating clock frequency for FAST READ command is 133
MHz."
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit ddba7c5ad797f4b878f4e177ef300c1f9837cd29)
Change-Id: I205637becab372f43d3e8e741f20d35aac79a5fe
Reviewed-on: http://git.am.freescale.net:8181/20036
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The FIXME and NOTE have already been fixed (we have FAST_READ support).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 1a874e91018ea99d7f012a0824669aa9ed833d6f)
Change-Id: I02d75e34033100678d65466628217bd493e82135
Reviewed-on: http://git.am.freescale.net:8181/20034
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the copyright information for spi-nor.c and spi-nor.h.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: Idde8bf06ec19e581234865b700207ee60e953755
Reviewed-on: http://git.am.freescale.net:8181/15511
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Fix errors like this:
ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined!
ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: I61a5d463500e2646dbb10dbab543550bf1ef009e
Reviewed-on: http://git.am.freescale.net:8181/15510
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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(0) What is the QuadSPI controller?
The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to
one single or two external serial flash devices, each with up to 4
bidirectional data lines.
(1) The QuadSPI controller is driven by the LUT(Look-up Table) registers.
The LUT registers are a look-up-table for sequences of instructions.
A valid sequence consists of four LUT registers.
(2) The definition of the LUT register shows below:
---------------------------------------------------
| INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
---------------------------------------------------
There are several types of INSTRx, such as:
CMD : the SPI NOR command.
ADDR : the address for the SPI NOR command.
DUMMY : the dummy cycles needed by the SPI NOR command.
....
There are several types of PADx, such as:
PAD1 : use a singe I/O line.
PAD2 : use two I/O lines.
PAD4 : use quad I/O lines.
....
(3) Test this driver with the JFFS2 and UBIFS:
For jffs2:
-------------
#flash_eraseall /dev/mtd0
#mount -t jffs2 /dev/mtdblock0 tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5
For ubifs:
-------------
#flash_eraseall /dev/mtd0
#ubiattach /dev/ubi_ctrl -m 0
#ubimkvol /dev/ubi0 -N test -m
#mount -t ubifs ubi0:test tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: Ie32163e49eb62af82bf311e9165363a2f8880841
Reviewed-on: http://git.am.freescale.net:8181/15509
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the spi_nor_match_id() to find the proper spi_device_id with the
NOR flash's name in the spi_nor_ids table.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: I471348a87ccde741055745d14cd25c84b480a803
Reviewed-on: http://git.am.freescale.net:8181/15508
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer.
Before this patch, the layer is like:
MTD
------------------------
m25p80
------------------------
spi bus driver
------------------------
SPI NOR chip
After this patch, the layer is like:
MTD
------------------------
spi-nor
------------------------
m25p80
------------------------
spi bus driver
------------------------
SPI NOR chip
With the spi-nor controller driver(Freescale Quadspi), it looks like:
MTD
------------------------
spi-nor
------------------------
fsl-quadspi
------------------------
SPI NOR chip
New APIs:
spi_nor_scan: used to scan a spi-nor flash.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[Brian: rebased to include additional m25p_ids[] entry]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: I7c22c4c83350eac8c325ccd8292450fde79bb069
Reviewed-on: http://git.am.freescale.net:8181/15507
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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