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| author | Tang Yuantian <Yuantian.Tang@nxp.com> | 2016-08-08 07:07:20 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 16:52:59 (GMT) |
| commit | 4de6ce1594fcff6fa9e626d094fa922f4889e167 (patch) | |
| tree | 365d7229e766c3dd6fc9ad21627586662bc5b4fe /arch/arm/include/asm/arch-fsl-layerscape/soc.h | |
| parent | f0beb49290c4e6af7d88895a15a45bbea38318fe (diff) | |
| download | u-boot-fsl-qoriq-4de6ce1594fcff6fa9e626d094fa922f4889e167.tar.xz | |
armv8: fsl-lsch2: enable snoopable sata read and write
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/soc.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 0729b7f..58e90d8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -61,6 +61,7 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe #define AHCI_PORT_TRANS_CFG 0x08000029 +#define AHCI_PORT_AXICC_CFG 0x3fffffff /* AHCI (sata) register map */ struct ccsr_ahci { |