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author | Mingkai Hu <Mingkai.Hu@freescale.com> | 2015-11-11 09:58:34 (GMT) |
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committer | York Sun <yorksun@freescale.com> | 2015-11-30 17:11:10 (GMT) |
commit | af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e (patch) | |
tree | deb74cf668e12399f6fbf08a4e48434c6d3e3e85 /arch/arm/include/asm/arch-fsl-layerscape/soc.h | |
parent | 06b53010436bd7d4d0da6bdb2f505131a094abc6 (diff) | |
download | u-boot-fsl-qoriq-af523a0d56b272bfd7d2a7ee4eccf07c7bb9529e.tar.xz |
pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/soc.h')
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..8691906 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; |