diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2015-08-15 20:37:50 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-08-26 14:54:09 (GMT) |
| commit | 5fb0151697088e257e0190d414cc7b2e2793b485 (patch) | |
| tree | 27236bb2d0973b0666a0ed59a29640b4b29a9fa2 /arch | |
| parent | 5c113ff79c601d69ce08803c7238679d8c7abd13 (diff) | |
| download | u-boot-fsl-qoriq-5fb0151697088e257e0190d414cc7b2e2793b485.tar.xz | |
x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/dts/bayleybay.dts | 6 | ||||
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 3 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 8f0e192..d646987 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -230,6 +230,12 @@ update@0 { #include "microcode/m0230671117.dtsi" }; + update@1 { +#include "microcode/m0130673322.dtsi" + }; + update@2 { +#include "microcode/m0130679901.dtsi" + }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index daac24e..f4e0a35 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -256,6 +256,9 @@ update@0 { #include "microcode/m0130673322.dtsi" }; + update@1 { +#include "microcode/m0130679901.dtsi" + }; }; }; |