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Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Device Tree really improves code maintainability and is now
available for SPL too.
This is the state-of-the-art implementation in U-boot.
The board files (platform data) are no longer needed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Remove ag101 and ag102 support
Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
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Add nds32 ag101p generic board support.
Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
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Document how pci devices are bound to device drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This is incorrect since we require the -m parameter to the microcode tool.
Update the two examples to show this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The doc has a misleading 'make menuconfig' when building the EFI
application and payload. Clarify this and also update information
on test with QEMU.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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With recent EFI support, the entry point address of coreboot payload
was changed. Now we update the address to use _x86boot_start, which
is the same one for EFI.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
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It is a bit tedious to figure out the interrupt configuration for a new
x86 platform. Add a script which can do this, based on the output of
'pci long'. This may be helpful in some cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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* Explicitly list the targets supported in each section of the
instructions from the x86 README.
* Drop references to 'raw mode', in favor of 'bare mode'.
Signed-off-by: Igor Stoppa <igor.stoppa@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add support for making the visual area of the framebuffer smaller and
drawing a black border around it. This is intended for use with
overscanning monitors (esp. with composite video out), to avoid part
of the picture being invisible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
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We do not need that "regulator-name" property must be provided in dts.
If "regulator-name" property is not provided in dts, node name
will chosen for settings '.name' field of uc_pdata.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
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Add composite video out support.
This only gets enabled on the Mele M3 for now, since that is were it
was tested. It will be enabled on more boards after testing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). The setup is included
in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
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While I2C supports multi-master buses this is difficult to get right.
The implementation on the master side in software is quite complex.
Clock-stretching and the arbitrary time that an I2C transaction can take
make it difficult to share the bus fairly in the face of high traffic.
When one or more masters can be reset independently part-way through a
transaction it is hard to know the state of the bus.
This driver provides a scheme based on two 'claim' GPIOs, one driven by the
AP (Application Processor, meaning the main CPU) and one driven by the EC
(Embedded Controller, a small CPU aimed at handling system tasks). With
these they can communicate and reliably share the bus. This scheme has
minimal overhead and involves very little code. It is used on snow to
permit the EC and the AP to share access to the main system PMIC and
battery. The scheme can survive reboots by either side without difficulty.
This scheme has been tested in the field with millions of devices.
Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
meaning the AP's, and 'their' claim GPIO, meaning the EC's. This terminology
is used by the device tree bindings in Linux also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a new I2C_MUX uclass. Devices in this class can multiplex between
several I2C buses, selecting them one at a time for use by the system.
The multiplexing mechanism is left to the driver to decide - it may be
controlled by GPIOs, for example.
The uclass supports only two methods: select() and deselect().
The current mux state is expected to be stored in the mux itself since
it is the only thing that knows how to make things work. The mux can
record the current state and then avoid switching unless it is necessary.
So select() can be skipped if the mux is already in the correct state.
Also deselect() can be made a nop if required.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Document the development flow on figuring out PIRQ information
during the U-Boot porting.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Add some documentation on the EFI implementation in U-Boot.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The steps required to boot a Linux distribution from U-Boot on x86 are not
very complicated, but it is a good idea to have these written down in an
accessible place.
Document how to examine the boot media from U-Boot, how to load a kernel,
load a ramdisk, set the kernel boot arguments and start the kernel. With
these instructions Ubuntu boots mostly normally on Minnowmax.
Note that the TSC timer does not operate correctly and gives warnings in
the boot log. I expect that ACPI support will solve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Fix a small typo in this binding file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Correct two typos and mention how pci bus will be probed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The board manual desribes ON as boolean 1 and OFF as boolean 0.
Updating README with correct boolean values.
Signed-off-by: Raghav Dogra <raghav@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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FASTBOOT is defined both by CONFIG_USB_FUNCTION_FASTBOOT AND CONFIG_CMD_FASTBOOT, so it doesn't
make much sense to have a CONFIG_USB_FASTBOOT prefix for fastboot-specific options, especially
given that other config options for fastboot use the CONFIG_FASTBOOT prefix.
This replaces the CONFIG_USB_FASTBOOT prefix with CONFIG_FASTBOOT, for consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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USB download gadget functions such as thor and dfu have a separate config option
for the USB gadget part of the code, independent from the command part.
This switches the fastboot USB gadget to the same scheme, for better
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
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This introduces a coherent scheme for naming USB download gadget and functions
config options. The download USB gadget config option is moved to
CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each
function's config option is moved to a CONFIG_USB_FUNCTION_ prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
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We should guide people more strongly towards device tree to avoid the
proliferation of platform data structures. Add documentation to the driver
model README, and also the platform data header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a simple driver which allows use of LEDs attached to GPIOs. The linux
device tree binding is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass <sjg@chromium.org>
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To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Document U-Boot multi-processor support as well as configuration
tables like SFI and MP tables for SMP OS kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The word "partition" is doubled. Keep decent forms for the
following lines.
Also, fix some other typos while we are here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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This patch adds the device tree binding doc for the cadence qspi controller &
also removes the not needed properties from the stv0991 device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
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Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
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This patch adds zynq spi controller nodes in zynq-7000.dtsi.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
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Some AVR32 boards were dropped by the following commits:
9eb45aabe078 (avr32: delete non generic board favr-32-ezkit)
e36930764471 (avr32: delete non generic board hammerhead)
c62d2f8fc5c6 (avr32: delete non generic board mimc200)
e5354b8a9e2a (avr32: delete non generic board's atstk100{3, 4, 6})
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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